JPS6281064A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS6281064A JPS6281064A JP60221666A JP22166685A JPS6281064A JP S6281064 A JPS6281064 A JP S6281064A JP 60221666 A JP60221666 A JP 60221666A JP 22166685 A JP22166685 A JP 22166685A JP S6281064 A JPS6281064 A JP S6281064A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- thin film
- film transistor
- electrodes
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6731—Top-gate only TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6743—Silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6743—Silicon
- H10D30/6746—Amorphous silicon
Landscapes
- Engineering & Computer Science (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
「産業上の利用分野」
この発明は例えば液晶を用いたアクティブ表示素子に用
いられる薄膜トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a thin film transistor used in an active display element using liquid crystal, for example.
「従来の技術」
まず従来の薄膜トランジスタを用いたアクティブ液晶表
示素子を第２図を参照して説明する。ガラスのような透
明基板１１及び１２が近［妾対向して設けられ、その周
縁部にはスペーサ１３が介在され、ごれら透明ｕ＋Ｎ１
１．１２間に液晶１４が１、を人されている。一方の透
明基板１１の内面に表示電極１５が複数形成され、これ
ら各表示電極１５に接してそれぞれスイッチング素子と
して薄膜トランジスタ１６が形成され、その薄１１２ト
ランジスタ１６のドレインは表示電極１５に接続されて
いる。これら複数の表示電極１５と対向して他方の透明
基板１２の内面に透明な共１１１１電極１７が形成され
ている。"Prior Art" First, an active liquid crystal display element using a conventional thin film transistor will be described with reference to FIG. Transparent substrates 11 and 12 such as glass are provided facing each other, and a spacer 13 is interposed at the periphery of the transparent substrates 11 and 12.
1. The liquid crystal 14 is read 1 between 1 and 12. A plurality of display electrodes 15 are formed on the inner surface of one transparent substrate 11, and a thin film transistor 16 is formed as a switching element in contact with each display electrode 15, and the drain of the thin 112 transistor 16 is connected to the display electrode 15. . A transparent common electrode 17 is formed on the inner surface of the other transparent substrate 12, facing the plurality of display electrodes 15.
表示電極１５は例えば画素電極であって第３ｒ７Ｉに示
すように、透明基板ｌｌ上に正方形の表示電極１５が行
及び列に近接配列されており、表示電極１５の各行配列
と近接し、かつこれに沿ってそれぞれゲートバス１８が
形成され、また表示電極１５の各列配列と近接してそれ
に沿ってソースバス１９がそれぞれ形成されている。こ
れら各ゲートハス１８及びソースバス１９の交差点にお
いてＰＪ ｎ’Ｊトランジスタ１６が設けられ、各薄膜
トランジスタ１６のゲートは両バスの交差点位置におい
てゲートハス１８に接続され、各ソースはソースバス１
９にそれぞれ接続され、更に各ドレインは表示電極１５
に接続されている。The display electrodes 15 are, for example, pixel electrodes, and as shown in No. 3r7I, square display electrodes 15 are arranged close to each other in rows and columns on a transparent substrate ll, and are close to each row arrangement of the display electrodes 15 and are arranged close to each other in rows and columns. Gate buses 18 are formed along each column of display electrodes 15, and source buses 19 are formed adjacent to and along each column of display electrodes 15. A PJ n'J transistor 16 is provided at the intersection of each gate lotus 18 and source bus 19, the gate of each thin film transistor 16 is connected to the gate lotus 18 at the intersection of both buses, and each source is connected to the source bus 19.
9, and each drain is connected to a display electrode 15.
It is connected to the.
これらゲートバス１日とソースバス１９との各一つを選
択してそれら間に電圧を印加し、その電圧が印加された
薄膜トランジスタ１６のみが導通し、その導通した薄膜
トランジスタ１６のドレ・インに接続された表示電極１
５に電荷を１積して表示電極１５と共通電極１７との間
の液晶１４の部分においてのみ電圧を印加し、これによ
って表示電極１５の部分のみを光透明或は光遮断とする
ことによって選択的な表示を行う。この表示電極１５に
蓄積した電荷を放電させることによって表示をン肖去さ
せることができる。One of the gate bus 1 and source bus 19 is selected and a voltage is applied between them, and only the thin film transistor 16 to which that voltage is applied becomes conductive, and is connected to the drain and drain of the thin film transistor 16 that is conductive. Display electrode 1
5 is multiplied by 1 charge and a voltage is applied only to the portion of the liquid crystal 14 between the display electrode 15 and the common electrode 17, thereby making only the portion of the display electrode 15 light transparent or light blocking. display. By discharging the charges accumulated in the display electrodes 15, the display can be turned off.
薄膜トランジスタ１６は従来においては例えば第４図及
び第５図に示すように構成されていた。The thin film transistor 16 has conventionally been constructed as shown in FIGS. 4 and 5, for example.
即ち透明基板１１上に表示７ｒＬ掻１５とソースバス１
９とがＩＴＯのような透明導電膜によって形成され、表
示電極Ｉ５及びソースハス１９の互に平行近接した部分
間にまたがってアモルファスシリコンのような半導体［
２１が形成され、更にその上に窒化シリコンなどのゲー
ト絶縁膜２２が形成される。このゲート絶縁膜２２上に
おいて半導体１２１を介して表示電Ｊｆｆｉ１５及びソ
ースバス１９とそれぞれ一部重なってゲート電極２３が
形成される。ゲート電極２３の一端はゲートバス１８に
接続される。このようにしてゲート電極２３とそれぞれ
対向した表示？１ｉｉ１５、ソースハス１９はそれぞれ
ドレイン電極１５ａ１ソース電極１９ａを構成し、これ
ら電極１５ａ、１９ａ、半導体層２１、ゲート絶縁膜２
２、ゲート電極２３によって７Ｊ−膜１ランジスタｌＧ
が構成される。ゲート電極２３及びゲートハス１８は同
時に形成され、例えばアルミニウムによって構成される
。That is, the display 7rL scratch 15 and the source bus 1 are displayed on the transparent substrate 11.
9 is formed of a transparent conductive film such as ITO, and a semiconductor film such as amorphous silicon is formed across the parallel and adjacent portions of the display electrode I5 and the source layer 19.
21 is formed, and a gate insulating film 22 made of silicon nitride or the like is further formed thereon. A gate electrode 23 is formed on the gate insulating film 22 so as to partially overlap the display electrode Jffi 15 and the source bus 19 via the semiconductor 121. One end of the gate electrode 23 is connected to the gate bus 18. Displays facing the gate electrodes 23 in this way? 1ii15 and source lotus 19 constitute drain electrode 15a1 and source electrode 19a, respectively, and these electrodes 15a, 19a, semiconductor layer 21, and gate insulating film 2
2, 7J-film 1 transistor lG by gate electrode 23
is configured. The gate electrode 23 and the gate lotus 18 are formed at the same time and are made of aluminum, for example.
またドレイン５ｉｔ１１５ ａ及びソース電極１９ａ上
にはそれぞれオーミ、り接触層２４．２５が形成されて
いた。オーミック接触層２４．２５は例えばｎプラスの
アモルファスシリコンで構成されている。その不純物と
しては例えばリンが用いられている。更にこれら薄膜ト
ランジスタ１６の全体を覆って、例えばシリコン千）化
膜よりなる保護層２６が形成されている。Further, ohmic contact layers 24 and 25 were formed on the drain electrode 115a and the source electrode 19a, respectively. The ohmic contact layers 24, 25 are made of n-plus amorphous silicon, for example. For example, phosphorus is used as the impurity. Further, a protective layer 26 made of, for example, a silicon chloride film is formed to cover the entire thin film transistors 16.
「発明が解決しようとする問題点」
第５図に示したように従来の薄膜トランジスタにおいて
は、ドレイン電極１５ ａ 、ソース電掘１９ａとなる
べき透明電極を透明基板１１上に形成し、その上にオー
ミック接触層２４．２５となるべきｎプラスのアモルフ
ァスシリコン層を形成し、その後ｎプラスアモルファス
シリコン層と透明電極とを所定のパターンにエツチング
して表示電極１５、ソースハス１９を形成していた。従
ってオーミ／り接触ＪＷ２４．２５は第５図に示すよう
にドレイン電極１５ａ、ソース電極１９ａの上側におい
てのみ形成されており、従ってこれら電極１５ａ、１９
ａと半導体層２１との接触部分の幅ｗｌ、ｗ２が小さく
なるに従って、これら電極１５ａ、１９ａと半導体層２
１とのオーミ・７り接触が十分とならず、ドレイン、ソ
ース間に直列に挿入される抵抗、いわゆるＲｓが大きく
なる。またこのように従来においてはオーミック接触層
２４．２５を特に形成しているためその膜厚分だけ、ソ
ース、ドレイン間の抵抗ｎｓが大きな値となっていた。"Problems to be Solved by the Invention" As shown in FIG. 5, in the conventional thin film transistor, transparent electrodes to become the drain electrode 15a and the source electrode 19a are formed on the transparent substrate 11, and An n-plus amorphous silicon layer to serve as the ohmic contact layers 24 and 25 was formed, and then the n-plus amorphous silicon layer and the transparent electrode were etched into a predetermined pattern to form the display electrode 15 and the source layer 19. Therefore, the ohmic contact JW24.25 is formed only above the drain electrode 15a and the source electrode 19a as shown in FIG.
As the widths wl and w2 of the contact portions between the electrodes 15a and 19a and the semiconductor layer 21 become smaller, the widths between the electrodes 15a and 19a and the semiconductor layer 2 become smaller.
The ohmic contact with 1 is not sufficient, and the resistance inserted in series between the drain and the source, so-called Rs, becomes large. Furthermore, in the conventional method, since the ohmic contact layers 24 and 25 are particularly formed, the resistance ns between the source and the drain becomes large by the thickness thereof.
更に従来においてドレイン電ＪＭ １５ ａ 、 ソ
ース電極＋９２は透明電極であるが、例えば酸化錫やＩ
ＴＯ（酸化インジュウム及び酸化錫）で構成されており
、この透明電極上に、オーミック接触層２４．２５や半
導体層２１を、例えばプラズマＣＶＤ法（プラズマ化学
的気相成長法）によって形成するが、これら層を形成中
に透明電極１５ａ５１９ａ中のインジュウムや錫などの
構成元素が半４体層２１やオーミ、り接触層２４．２５
内に拡散し、不純物となり、半導体層２１がＰ形層とな
り、また透明電極１５ａ、１９ａ中の酸化物が半導体層
２１、オーミック接触Ｎ２４，２５に入り、酸化シリコ
ンを形成したり、更にインジュウムや錫がオーミック接
触層２４．２５に入るとｎプラス層に対してＰ形不純物
が入ったことになり、オーミック接触の効果を下げてし
まい、従って前記Ｒｓ が大きくなる。これらの点より
薄膜トランジスタの特性の良好なものが得られなかった
。Furthermore, conventionally, the drain electrode JM 15 a and the source electrode +92 are transparent electrodes, but they are made of transparent electrodes such as tin oxide or I
It is composed of TO (indium oxide and tin oxide), and the ohmic contact layers 24 and 25 and the semiconductor layer 21 are formed on this transparent electrode by, for example, plasma CVD (plasma chemical vapor deposition). While forming these layers, constituent elements such as indium and tin in the transparent electrode 15a519a are removed from the semi-quadramic layer 21, ohmic contact layer 24, 25, etc.
The semiconductor layer 21 becomes a P-type layer, and the oxides in the transparent electrodes 15a and 19a enter the semiconductor layer 21 and the ohmic contacts N24 and 25, forming silicon oxide, and further forming indium and other impurities. When tin enters the ohmic contact layer 24, 25, a P-type impurity enters into the n-plus layer, which reduces the effectiveness of the ohmic contact and therefore increases the Rs. Due to these points, thin film transistors with good characteristics could not be obtained.
この発明の目的はソース電極、ドレイン電極間と半導体
層とのオーミック接触が良好な薄膜トランジスタを提供
することにある。An object of the present invention is to provide a thin film transistor with good ohmic contact between a source electrode and a drain electrode and a semiconductor layer.
「問題点を解決するための手段」
この発明によればソース電極及びドレイン電極と半導体
層との全接触域にわたってオーミック接触層が形成され
る。従ってこれら半導体層とこれら電極とは良好なオー
ミック接触状態となり、いわゆるＲｓが小さなものが得
られる。特に好ましくはドレイン電極及びソース電極と
してリンやホウ素などをｌＪ２：敗したものを用いると
よい。つまりリンやホウ素を含む透明電極を形成し、又
は従来の透明電極を形成した後これらに対してリンある
いはホウ素を拡散し、その後ドレイン電極、ソース電極
の形状にエツチングし、更に半導体層を形成し、またゲ
ート絶縁膜、ゲート電極を順次形成する。この場合、特
にオーミック接触層を形成する工程を設けることはない
が、半導体層を形成する際に先にソース電極、ドレイン
電極にＦＩＬ敗したリン又はホウ素が半導体層との接触
面に析出し半導体層に入り、オーミック接触層が自動的
に形成される。"Means for Solving the Problems" According to the present invention, an ohmic contact layer is formed over the entire contact area between the source electrode and the drain electrode and the semiconductor layer. Therefore, these semiconductor layers and these electrodes are in a good ohmic contact state, so that what is called a small Rs can be obtained. Particularly preferably, phosphorus, boron, or the like is used as the drain electrode and the source electrode. In other words, after forming a transparent electrode containing phosphorus or boron, or forming a conventional transparent electrode, phosphorus or boron is diffused into these electrodes, and then etched into the shape of a drain electrode and source electrode, and then a semiconductor layer is formed. In addition, a gate insulating film and a gate electrode are sequentially formed. In this case, there is no particular step of forming an ohmic contact layer, but when forming the semiconductor layer, the phosphorus or boron that has been subjected to FIL to the source and drain electrodes is precipitated on the contact surface with the semiconductor layer. layer and an ohmic contact layer is automatically formed.
ソース電極、ドレイン電極に含ませる元素としてはリン
、ホウ素に限らず、ひ素、ビスマス、アンチモンなどの
５族元素や、アルミニウム、ガリウムなどの３族元素で
もよい。The elements contained in the source electrode and the drain electrode are not limited to phosphorus and boron, but may also be group 5 elements such as arsenic, bismuth, and antimony, and group 3 elements such as aluminum and gallium.
「実施例」
以下この発明による薄膜トランジスタをその製法と共に
説明する。第１図Ａに示すようにガラスなどの透明基板
１１上にＩＴＯなどの透明導電膜３１が形成され、その
透明導電膜３１を工・ノチング処理して所定のパターン
に形成し、第１図已に示すようにドレイン電極１５ａ、
ソース電極１９ａをそれぞれ形成する。更にこの実
施例においてはこれら透明電極１５ａ、１９ａに対して
リンを含有させる。即ちこれら基板１１．電極１５ａ、
１９ａの表面にリン含を層３２を形成する。このリンを
含有させるには例えばプラズマＣＶＤ法によって行うこ
とができ、基板１１を２００℃乃至３００°Ｃとし、Ｐ
Ｉ−１、ガスをアルゴンガスで５０００ｐｐｍ 、に
稀釈し、１ＯＣＣＺ分の速度で供給し、圧力１０” Ｔ
ｏｒｒの雰囲気で２０Ｗの高周波電力によりプラズマ化
学的気相成長を数分間行うことによりリンを含有させる
。"Example" The thin film transistor according to the present invention will be described below along with its manufacturing method. As shown in FIG. 1A, a transparent conductive film 31 such as ITO is formed on a transparent substrate 11 such as glass, and the transparent conductive film 31 is processed and notched to form a predetermined pattern. As shown in FIG.
Source electrodes 19a are respectively formed. Furthermore, in this embodiment, these transparent electrodes 15a and 19a contain phosphorus. That is, these substrates 11. electrode 15a,
A phosphorus-containing layer 32 is formed on the surface of 19a. The inclusion of phosphorus can be carried out, for example, by a plasma CVD method, in which the substrate 11 is heated to 200°C to 300°C, and P
I-1, the gas was diluted to 5000 ppm with argon gas, fed at a rate of 1 OCCZ, and the pressure was 10" T.
Phosphorus is incorporated by performing plasma chemical vapor deposition for several minutes with a high frequency power of 20 W in an atmosphere of
このようにリン含有層３２を形成した後、第１図Ｃに示
すように従来と同様に例えばアモルファスシリコンの半
導体１２１を形成し、その上にチノ化シリコンのゲート
絶縁膜２２を形成し、更にその上にゲート電極２３を形
成し、その後エツチングにより所定のパターンとする。After forming the phosphorus-containing layer 32 in this manner, as shown in FIG. A gate electrode 23 is formed thereon, and then etched into a predetermined pattern.
次に第１図りに示すように保護層２Ｇを例えばチ、化シ
リコンにより形成する。Next, as shown in the first diagram, a protective layer 2G is formed of silicon oxide, for example.
半導体層２１は高周波プラズマＣＶＤ法によって基板を
２００℃乃至３００℃として形成されるが、その際にリ
ン含有層３２のリンが半導体層２１に拡散し、半導体層
２１と電極１５ａ、１９ａとの全接触１面にわたってそ
れぞれリンを含むオーミ７り接触層３３．３４が形成さ
れる。このように形成されるためこのオーミ、り接触層
３３は非常にごく薄いが確実に形成され、しかも半導体
層２１と電極１５ａ及び１９ａとが互に接触してる全域
にわたって形成され、良好なオーミック１妄触が得られ
、従って前記Ｒｓの小さな薄膜トランジスタが得られる
。また半導体１２１の厚さもｉ？Ｖ くすることができ
、この点からもＲｓを小さくすることができる。The semiconductor layer 21 is formed by high-frequency plasma CVD at a temperature of 200° C. to 300° C., but at this time, phosphorus in the phosphorus-containing layer 32 diffuses into the semiconductor layer 21, and the entire contact between the semiconductor layer 21 and the electrodes 15a and 19a is Ohmic contact layers 33 and 34 each containing phosphorus are formed over one surface of the contact. Since the ohmic contact layer 33 is formed in this manner, it is formed reliably although it is very thin, and is formed over the entire area where the semiconductor layer 21 and the electrodes 15a and 19a are in contact with each other, resulting in a good ohmic contact layer 33. Therefore, a thin film transistor with a small Rs can be obtained. Also, the thickness of the semiconductor 121 is also i? V can be made smaller, and Rs can also be made smaller from this point of view.
また、ガラス基板１１に拡散したリンがガラス基板１１
の表面に現われるため、特に電極１５ａ。In addition, the phosphorus diffused into the glass substrate 11
Especially since it appears on the surface of the electrode 15a.
１９８間のチャネル部分において、ガラス基板Ｉｆ中の
ナトリウムなどが現われても、そのナトリウムがリンに
よっていわゆるゲッタリングされて安定に動作する薄膜
トランジスタが得られる。Even if sodium or the like in the glass substrate If appears in the channel portion between 198 and 198, the sodium is gettered by phosphorus, resulting in a thin film transistor that operates stably.
更に半導体層２１を形成中において透明電極＋５ａ、１
９ａ中のインジュウムや錫がリンと結合し、これらが半
導体層２１に拡散するのが防止される。なお必要に応し
て半導体層２１を所定の形状にエツチングする際に透明
電極１５ａ、１９ａ上のリン含有層３２を除去してもよ
い。透明電極中にリンを拡散させるにはプラズマＣＶＤ
法に限らず熱拡散を行ってもよく、或いは透明電極の形
成時にリンを同時に含有させることもできる。またリン
の他にホウ素を透明ＴｒＬ極に含有させてもよい。Furthermore, during the formation of the semiconductor layer 21, transparent electrodes +5a, 1
Indium and tin in 9a combine with phosphorus and are prevented from diffusing into the semiconductor layer 21. Note that, if necessary, the phosphorus-containing layer 32 on the transparent electrodes 15a and 19a may be removed when the semiconductor layer 21 is etched into a predetermined shape. Plasma CVD is used to diffuse phosphorus into the transparent electrode.
The method is not limited to this method, and thermal diffusion may be used, or phosphorus may be added at the same time as the transparent electrode is formed. Further, in addition to phosphorus, boron may be contained in the transparent TrL electrode.
「発明の効果」
以上述べたようにこの発明によれば透明電極と半導体層
の全接触域にわたってオーミック接触層が形成されてい
るためＲｓ の小さなものが得られる。また透明電極と
してリンやホウ素を含有したものを用いて作ることによ
って前記Ｒｓを小さく、しかも安定な薄膜トランジスタ
が得られる。"Effects of the Invention" As described above, according to the present invention, since the ohmic contact layer is formed over the entire contact area between the transparent electrode and the semiconductor layer, a small Rs can be obtained. Further, by using a transparent electrode containing phosphorus or boron, it is possible to reduce Rs and obtain a stable thin film transistor.
第１図はこの発明による薄膜トランジスタの一例の製造
工程を示す断面図、第２図は液晶表示素子の断面の一部
を示す図、第３図は薄膜トランジスタの電気回路を示す
回路図、第４図は第３図中の表示電極、薄膜トランジス
タの平面図、第５図は第４図のＡＡ線拡大断面図である
。
１１：ｉ３明基１反、１５ａニドレイン電１侃、１９ａ
：ソース電極、２１：半導体層、２２：ゲート絶縁膜、
２３：ゲート電極、３２ニリン含有層、３３．３４ニオ
−ミック接触層。
特許出願人 星電：！Ｓ？！！造株式会社代 理
人 草 野 卓か １ 図
１９ａ １５ａ
オ ２ 図FIG. 1 is a cross-sectional view showing the manufacturing process of an example of a thin film transistor according to the present invention, FIG. 2 is a view showing a part of a cross section of a liquid crystal display element, FIG. 3 is a circuit diagram showing an electric circuit of the thin film transistor, and FIG. 3 is a plan view of the display electrode and thin film transistor in FIG. 3, and FIG. 5 is an enlarged sectional view taken along the line AA in FIG. 4. 11: i3 ming group 1 anti, 15a nidorein 1 kan, 19a
: source electrode, 21: semiconductor layer, 22: gate insulating film,
23: Gate electrode, 32 Niline-containing layer, 33.34 Niomic contact layer. Patent applicant Seiden:! S? ! ! Zozo Co., Ltd. Representative
Figure 19a 15a Figure 2
Claims (3)
形成され、これらソース電極及びドレイン電極間にわた
って半導体層が形成され、その半導体層上にゲート絶縁
膜が形成され、そのゲート絶縁膜上にゲート電極が形成
され、上記半導体層と上記ソース電極及びドレイン電極
との間にその全域にわたってオーミック接触層が形成さ
れている薄膜トランジスタ。(1) A source electrode and a drain electrode are formed separated from each other, a semiconductor layer is formed between the source electrode and the drain electrode, a gate insulating film is formed on the semiconductor layer, and a gate insulating film is formed on the gate insulating film. A thin film transistor, wherein an electrode is formed, and an ohmic contact layer is formed over the entire area between the semiconductor layer and the source and drain electrodes.
レイン電極との対向側面と上記ゲート絶縁膜側の面とに
わたってそれぞれ形成されていることを特徴とする特許
請求の範囲第１項記載の薄膜トランジスタ。(2) The thin film transistor according to claim 1, wherein the ohmic contact layer is formed over a side surface facing the source electrode and the drain electrode and a surface facing the gate insulating film.
又は３族の元素を含む透明電極であることを特徴とする
特許請求の範囲第１項記載の薄膜トランジスタ。(3) The thin film transistor according to claim 1, wherein the drain electrode and the source electrode are transparent electrodes each containing a group 5 or 3 element.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60221666A JPH0622244B2 (en) | 1985-10-04 | 1985-10-04 | Thin film transistor and manufacturing method thereof |
| EP86113674A EP0217406B1 (en) | 1985-10-04 | 1986-10-03 | Thin-film transistor and method of fabricating the same |
| AT86113674T ATE77177T1 (en) | 1985-10-04 | 1986-10-03 | THIN FILM TRANSISTOR AND METHOD FOR ITS MANUFACTURE. |
| DE8686113674T DE3685623T2 (en) | 1985-10-04 | 1986-10-03 | THIN FILM TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF. |
| KR1019860008313A KR900000066B1 (en) | 1985-10-04 | 1986-10-04 | Manufacturing method of film transistor |
| US07/222,296 US4864376A (en) | 1985-10-04 | 1988-07-22 | Thin-film transistor and method of fabricating the same |
| US07/399,141 US5061648A (en) | 1985-10-04 | 1989-08-28 | Method of fabricating a thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60221666A JPH0622244B2 (en) | 1985-10-04 | 1985-10-04 | Thin film transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6281064A true JPS6281064A (en) | 1987-04-14 |
| JPH0622244B2 JPH0622244B2 (en) | 1994-03-23 |
Family
ID=16770359
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60221666A Expired - Fee Related JPH0622244B2 (en) | 1985-10-04 | 1985-10-04 | Thin film transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0622244B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069370A (en) * | 1997-03-26 | 2000-05-30 | Nec Corporation | Field-effect transistor and fabrication method thereof and image display apparatus |
| JP2006148114A (en) * | 2004-11-16 | 2006-06-08 | Samsung Electronics Co Ltd | Thin film transistor array panel using semiconductor and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5769778A (en) * | 1980-10-17 | 1982-04-28 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPS59172774A (en) * | 1983-03-22 | 1984-09-29 | Nec Corp | Amorphous silicon thin film transistor |
| JPS59181064A (en) * | 1983-03-31 | 1984-10-15 | Toshiba Corp | Semiconductor device |
| JPS59232385A (en) * | 1983-06-15 | 1984-12-27 | 株式会社東芝 | Active matrix type display unit |
-
1985
- 1985-10-04 JP JP60221666A patent/JPH0622244B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5769778A (en) * | 1980-10-17 | 1982-04-28 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPS59172774A (en) * | 1983-03-22 | 1984-09-29 | Nec Corp | Amorphous silicon thin film transistor |
| JPS59181064A (en) * | 1983-03-31 | 1984-10-15 | Toshiba Corp | Semiconductor device |
| JPS59232385A (en) * | 1983-06-15 | 1984-12-27 | 株式会社東芝 | Active matrix type display unit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6248634B1 (en) | 1995-09-26 | 2001-06-19 | Nec Corporation | Field-effect transistor and fabrication method thereof and image display apparatus |
| US6362493B1 (en) | 1995-09-26 | 2002-03-26 | Nec Corporation | Field-effect transistor and fabrication method thereof and image display apparatus |
| US6069370A (en) * | 1997-03-26 | 2000-05-30 | Nec Corporation | Field-effect transistor and fabrication method thereof and image display apparatus |
| JP2006148114A (en) * | 2004-11-16 | 2006-06-08 | Samsung Electronics Co Ltd | Thin film transistor array panel using semiconductor and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0622244B2 (en) | 1994-03-23 |
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