JPS6243747A - dual port memory controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a device for switching the memory space of one data processing device in a system in which two data processing devices are connected via a plurality of dual port memories. It is something.

[Prior Art] Conventionally, this type of device has been configured to include only one memory system of dual port memory, as shown in FIG.

[Problems to be Solved by the Invention] Therefore, when a data processing device accesses a dual port memory, there is always competition with the other data processing device, resulting in a disadvantage that the access time becomes extremely long.

Another disadvantage is that processing becomes complicated when memory capacity is insufficient, such as when dual-port memory is used to temporarily store data from one data processing device to another. .

[Means for Solving the Problems] The present invention eliminates the drawbacks of the conventional example described above, and at the same time, it is possible to transfer data between dual port memories by converting the real memory corresponding to the logical address block. , the purpose is to enable faster processing, and for this purpose, we have developed a means for individually converting dual-port memory, which is an access circuit from two data processing devices, into a single port, and a logical attribution of the dual-port portion of memory. means for arbitrarily allocating a space to the physical address space of the dual port portion in the middle of the block of capacity of the dual port memory.

[Function] In other words, the present invention converts each dual-port memory into a single port, and also converts the logical address space of the dual-port portion of the memory into the physical address space of the dual-port portion with the capacity of the dual-port memory. By arbitrarily allocating it in units of two blows, the data processing device can perform high-speed processing.

[Example] The present invention will be described in detail below with reference to the F1 drawing. FIG. 2 is a block diagram of one embodiment of the present invention.

In FIG. 2, A and B are data processing devices each having a microprocessor/system 1, 2 and a memory 3.4.

9.10 and 11 are dual port memories,
Each is an independent block of dual-port memory.

5 is a decoder, and 6 is an address conversion device that converts the logical address of the data processing device δA into a physical L address (
7 is a multiplexer for branching the control signal 17 from data processing device B to the dual port memory; 8 is a decode/latch circuit;
It is controlled by a control signal 13 from the data processing device A, decodes the data signal 14 from the same 5t21A, and controls the multiplexer 7 by checking the result.

12 is a logical high-order address of the data processing device A, 15 is the logical high-order address 12 or a physical high-order address translated by the address translation device M6, 16 is a control signal to the multiplexer 7 latched by the circuit 8, and 17 is a Memory select signals to dual port memories 9, 10 and 11 are decoded by decoder 5, and 18 is a control signal branched by multiplexer 7.

The address conversion device M (register file) 6 is shown in FIG.
As shown in a), the logical upper address is used as the address of the register file, and the physical upper address corresponding to the logical upper address is stored.

When a register address of the address translation device 6 is accessed by the logical upper address 12, the corresponding physical upper address stored therein is sent to the decoder 5 as an address 15.

In this way, a logically higher address is converted into a physically higher address. Since the contents of this address translation device 6 can be freely rewritten by the data processing device HA, logical high-order addresses can be freely assigned to physical high-order addresses.

When rewriting the contents of the address conversion device 216, the data of the physical upper address is placed on the data signal 14.
For this data, a dual port switching signal is placed on one of the data signal lines as shown in FIG. 3(b). This dual port switching signal causes the dual port memory (dual port memories 9, 10, 11, etc. in Figure 2) corresponding to the data of the physical upper address placed on other data signal lines to be switched to dual port or data processing. Make it a single port from the installed NA.

For example, if the signal line carrying this dual port switching signal is set to 1'', the corresponding memory becomes a dual port, and if it is set to 0'', the corresponding memory becomes a single port.

The decode/latch circuit 8 decodes the physical upper address on the data signal line 14 and the dual port control signal, and outputs a signal to the multiplexer 7 indicating which dual port memory is set as dual port.
And the signal is turned until it is changed.

According to the signal from the circuit 8, the multiplexer 7 branches the control signal 17 only to the memory set to be dual-ported.

Therefore, the memory to which the control signal 17 is not branched automatically becomes the single port memory of the data processing 11F device A.

The 4th IA (a') and (b) have a logical address block (hereinafter referred to as LAB) and a physical address lock (hereinafter referred to as PA).
(abbreviated as B) is an example of correspondence. However, the number of blocks is 3
Let us describe the case.

PABO supports dual port memory 9, and PAB
1 corresponds to the dual port memory 10, and PAB2 corresponds to the dual port memory 11.

In (a), LABO corresponds to PABO, LAB1 corresponds to PAB 1, and LAB2 corresponds to PAB2.

Although PABO is a dual port, this means that 9 is a dual port in the actual memory; the other PABI and PAB2 are single ports.

By changing the contents of the register of the address translation device 6 from this state and controlling the dual baud 1 switching signal at the same time, a setting state such as that shown in (b) can be achieved, for example. In this case, LABO is set to PAB 1, LABI is set to PAB 1, and LABI is set to PAB 1.
2, rewrite LAB2 to correspond to PABO and at the same time change the dual port switching signal from LABO to PAB.
Change the address to correspond to 1! ! ! ! When rewriting the module 2i6, set it to "O", when making LABI correspond to PAB2, set it to "1", and when making LAB2 correspond to PABO, set it to "O".

With this, only the PAB2, that is, the dual port memory 11 can be made into a dual port.

1) In the above embodiment, the logical address block,
Although the case has been described in which the number of physical address blocks is 3 and 2, the number of blocks may be more than one.

2) In the above embodiment, a register file is used as the address translation device, but the present invention is not limited to this as long as it operates in a similar manner.

3) The present invention is not limited to the configuration example of the above-described embodiment, and various configuration modifications are possible within the technical scope thereof.

[Effects of the Invention] l) As explained above, in the present invention, the logical address and physical address of the dual port section can be freely associated in block units, so logical On the address, the same result as the data transfer is selected, so processing becomes extremely fast.

2) Memory can be freely switched between dual port and single port↑ By making memory a single port, access time can be much reduced compared to dual port, and processing can be faster.

3) Since dual-port memory can be freely converted into dual-port or single-port memory, a virtually large dual-port memory space can be taken up by converting real memory that becomes dual-port one after another.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional system having a dual port memory, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3(a) is a diagram showing the contents of an address translation device. Fig. 3(b) is a diagram showing the contents of the data signal, Fig. 4(a)
), (&) are diagrams showing the correspondence between a logical address space, a physical address space, and a dual port memory. 1.2...Microprocessor, 3.4...Memory, 5...Decoder, 6...Address translation device (register file), 7...Multiplexer, 8...Decoder and chip 2,000 Circuit, 9.10.11... Dual port memory, 12...
- Logical upper address of the data processing device, 13... Control signal of the data processing device, 14... Data signal of the data processing device, 15... Physical -F address of the data processing device, 16... Multiplexer Control signal 17...
Control signal for data processing device, 18... Memory select signal, 19... Control signal for data processing device. Figure 1 r -==--11-co- The address of the person who was pregnant and died at the same time Figure 3

Claims (1)

[Claims] Means for individually converting a dual port memory accessible from two data processing devices into a single port; 1. A memory space switching device comprising means for arbitrarily allocating port memory capacity in block units.