JPS62268225A - Data transmission system - Google Patents

Abstract

PURPOSE:To prevent the transmission mistake by providing an address coincidence control means comparing a reception address and an internal generation address and applying synchronizing control so that the internal generation address is coincident with the reception address when they differ. CONSTITUTION:An address reception means 43 receiving an address sent from an address transmission means 33, a reception side address rotation means generating an address changed sequentially the same as the reception address at the inside and an address coincidence control means applying synchronizing control so as to make the internal generation address is coincident with the reception address when they are different from each other are provided to a transmission station 40. Further, the transmission station 40 sent with the address is provided with a reception side address rotation means 44 to generated the address internally. As a result, the reception address is compared with the internal generation address to detect the mistake of the address transmisstion and the transmission mistake of data is prevented in advance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission system, and is applicable to, for example, a heat pump system.

[Conventional technology]

An internal combustion engine-driven heat pump is equipped with an outdoor unit and an indoor unit, and conventionally, for example, a microcomputer-configured controller is installed in each of the outdoor unit and the indoor unit to share control functions. There is something like this. Even when the functions are divided in this way, the data held by the (m) controller may be necessary to execute the control operation, so in the conventional two-way pump system, one controller controls the indoor unit, and the other controller controls the indoor unit. Data could be serially transmitted between the outdoor unit controller and the outdoor unit controller.

As a method for serially transmitting data, three conventional methods have been used as shown below.

The first method is to transmit all data in one transmission cycle, and the second method is to transmit all data in one transmission cycle.
This is a method in which a unit of data and address is transmitted, and the receiving side determines and selects the type of data based on the received address.The third method is to always transmit only one data in one transmission cycle. In this method, a top address is transmitted in a predetermined transmission cycle, and data is received on the receiving side in synchronization based on the top address.

[Problem that the invention seeks to solve]

However, according to the first method described above, since the number of data in one transmission cycle is large, the signal width of 1 bit is short during a certain cycle. In this case, a bit shift occurred and a transmission error occurred. On the other hand, if a sufficient signal width is secured in an attempt to prevent transmission errors, (1) the transmission cycle becomes longer, which adversely affects other control cycles.

Furthermore, according to the second method, if the address itself is changed due to noise or the like and is received, the receiving side cannot determine whether or not the address has changed.
There was a risk of making a big mistake such as putting data into the RAM of the receiver.

The third method also has the same drawbacks as the second method. According to this method, data is simply identified in order based on the top address, so if the top address is received incorrectly, all the data will be messed up, resulting in a bigger mistake than in the second method. Also, even if you try to prevent the above inconvenience by providing a judgment function and not using the address when noise is mixed in, in this case, there is no need to wait for the next top address (while waiting) data transmission will not take place.

Moreover, both methods have the problem that once a transmission error occurs, it takes a long time for the system to recover.

The present invention has been made in consideration of the above points, and can effectively prevent transmission errors due to data transmission delays and transmission errors due to noise contamination. The aim is to provide a data transmission system that can quickly recover.

[Means for solving problems]

In order to solve this problem, in the present invention, as shown in the functional block diagram of FIG. 1, data transmitting means 3t, il, which transmit one data in one transmission cycle,
Data receiving means 32.42 for receiving transmitted data
In a data transmission system comprising a plurality of transmission stations 30, 40, an address transmitting means 33 for transmitting an address indicating the number of data to be transmitted in the transmission cycle, and an address for sequentially changing the address. Rotation means 34 and at least one transmission station 3
address receiving means 43 for receiving the address transmitted by the address transmitting means 33; a receiving side address rotation means 44 for internally generating addresses that are sequentially changed in the same way as the receiving address; and the internally generated address, and if they are different, the internally generated address is synchronously controlled so that it matches the received address.
It was established in

[For production]

■In a transmission cycle, the data transmitted between transmission stations 30 and 40 is set as one data to widen the signal width and reduce transmission errors.

Also, the receiving side address is also sent to the transmission station 40 to which the address is being transmitted.・Reslotition means 44 is provided to generate an address internally.

As a result, by comparing the received address and the internally generated address, it is possible to detect a transmission error in the address, thereby making it possible to prevent data transmission errors.

Furthermore, an address matching control means 45 is provided to perform synchronization control so that the received address and internally generated address match, so that even if the synchronization is lost, the synchronization can be quickly restored.

〔Example〕

An embodiment in which the present invention is applied to a heat pump system will be described in detail below with reference to the drawings.

In FIG. 2, 1 is an outdoor unit controller configured with a microcomputer, and 2 and 3 are indoor unit controllers configured with a microcomputer.
3 are interconnected via cables 4°5.6.

Each controller 1 to 3 is a central processing unit.
(CPtJ)7~9, program ROM10~12, R
Equipped with AM13-15, CPU7-9 and ROM10-1
The program stored in RA 2 is loaded via buses 16 to 18, and the RA is loaded as necessary based on the program.
Data is stored and updated in M13 to M15 to execute control operations of the heat pump system.

In the control operation, when it becomes necessary to transmit data to another controller, data transmission is performed based on the transmission program shown in FIG. 3 or 4 shown below. Each controller 1 to 3 has an interface circuit 1.
9 to 21, and the signals sent through the interface circuits 19 to 21 are shaped in the corresponding signal shaping circuits 22 to 24 and sent to predetermined cables 4 and 6.4 and 5 and 5.
and 6, or the signals arriving through the cables 4 and 6.4 and 5, 5 and 6 are sent to the signal shaping circuit 22
After shaping in ~24, the interface circuit 19~
21 to the controllers 11-1 to 3.

In this embodiment, the outdoor unit controller I is the mask controller, each of the indoor unit controllers 1 to 2 and 3 are slave controls, and the ROM1 of the mask controller I is
The main transmission program shown in FIG. 3 is stored in the slave controller 2.0, and the transmission program shown in FIG. 4 is stored in the slave controller 2.3.

When the CPU of the controller is given a data transmission command, it starts the program in step S1, and then
Proceeding to step S2, the number of times flag is inverted. after that,
In step S3, the state of the count flag is determined. As a result, if the flag has risen to logic "L", the process directly proceeds to step S5, and if the flag has fallen to logic "0", the address is set in step S4. Rotate to the next address and proceed to the next step S5.

In this embodiment, the same data is transmitted twice in a row, and the number flag falling to logic "0" indicates that it is the first transmission cycle, so in step S4 The data to be communicated is determined by rotating the address, and on the other hand, if the number of times flag is rising to logic "1" indicating the second transmission cycle, step S4 is skipped and the address is changed. I try not to.

Step S5 is a step of outputting an interrupt signal to notify the controllers 2 and 3 of the start of transmission. When the process of step S5 is finished, the CPU 7 performs the next step S6.
address (e.g. including the count flag l by 1
-) is sent. Thereafter, in step S7, the CPU 7 determines which controller is the controller that performs the sending operation based on the address.

As a result of the determination, if it is determined that the mask controller 1 is the transmitting controller, the process advances to step S8 to transmit the data, and then in step S9 the processing in the transmission cycle is ended.

On the other hand, if it is determined that the controller 2 or 3 is the transmitting controller as a result of the determination in step S7, the process advances to step SIO or Sll to receive data. Next, the CPU 7 proceeds to step S12 and determines the state of the number of times flag, and determines whether it is the first transmission or the second transmission of the same data. As a result, if it is determined that this is the first transmission, the process proceeds to step S13 and the received data is stored in the RAM.
The data is stored in the previous data register No. 13, and the processing of the transmission cycle is ended in step S9.

On the other hand, if it is determined in step 312 that this is the second transmission, the process proceeds to step S14, where it is determined whether the received data this time matches the received data stored in the previous data register. If a positive result is obtained by matching, the received data is determined to be valid in step S15, and the process ends in step S9.

In step S14, for example, if the previous received data and the current received data do not match due to noise etc. being mixed in the previous transmission or the current transmission, the process proceeds to step S16, where the received data is invalidated and the second transmission is performed. The transmission performed in the cycle is meaningless and is treated as not being received, and the process ends in step S9.

Each CPU 8.9 of the controllers 2 and 3 starts the transmission program shown in FIG. 4 in step S20 when the interrupt signal (step S5 in FIG. 3) is received from the mask controller 1 and the controller 1, and then executes the next step. In S21, the address transmitted from the mask controller l (step S6 in FIG. 3) is received. Then CI) U
8.

9, it is determined in step 322 whether the received address and the internally generated address match (7).

As a result, if a positive result is obtained due to a match, the transmission operations of steps 323 to S31 are substantially performed. Therefore, since the transmission operations in steps 323 to S31 are substantially the same as the transmission operations in steps 87 to S16 in FIG. 3, the explanation thereof will be omitted.

When the transmission operation is finished in this way, the CPUs 8 and 9
Proceeds to step S32, after inverting the number of times flag,
In step S33, the state of the number flag is determined, and as a result, if the number flag indicates the second time (logical r l j '), the process advances to step S34, where the internally generated address is updated to the address of the next transmission cycle. The process advances to step 335, and on the other hand, the number of times flag is set to the first time (logical "0").
''), the process directly advances to step S35 and the main routine without updating the internally generated address. That is, steps 332 to S34 are steps for incrementing the internally generated address in accordance with the incrementing operation of the received address (steps 82 to S4 in FIG. 3).

If a negative result is obtained in step 322 above, CP
U8.9 proceeds to step 336 and subsequent steps for synchronizing the controllers 1 to 3 without performing data transmission processing.

That is, in step S36, it is determined whether or not the number of times flag indicates the first time, and if it is determined that it is the first time, the process advances to step 337 and the reception address is stored in the RAM 14.15.
is stored in the previous address register, and the process returns to the main routine in step S35. On the other hand, if it is determined in step S36 that it is the second time, the process proceeds to step 338, where it is determined whether or not the first address and the current address match. As a result, if a positive result is obtained, system j, S
The process proceeds to step S39, where the received address is stored in the internally generated address register, and the process proceeds to step S32, so that an affirmative result is obtained in step S22 of the next transmission cycle.

On the other hand, if a negative result is obtained in step 338, the process immediately returns to the main routine in step S35.

These processes from step 336 onwards determine whether the cause of the mismatch between the received address and the internally generated address is due to destruction of the address due to noise, etc., or due to loss of synchronization due to a reset timing shift, etc. , only if the address is received correctly but not synchronized, change the internally generated address to synchronize,
In other cases (due to noise, etc., and the probability that the first and second addresses will be the same is considered to be extremely low), the reception address is assumed to have been transformed and the system waits until the reception address can be received correctly.

Therefore, according to the above embodiment, only one pulse and one data are transmitted in one transmission cycle, so that the signal width of one bit for the transmission cycle can be widened, and the signal width can be increased. Transmission errors due to distortion, delay, etc. can be significantly reduced compared to the conventional method.

In addition, the controller 2-3 that receives addresses has an internally generated address that is checked against the received address, so it is possible to detect errors in address reception due to noise, which in turn can prevent errors in data transmission. This can be effectively prevented.

Furthermore, even if the sending and receiving controllers are out of synchronization due to different reset timings, for example, the internally generated address is changed based on the past received address (step 539), so synchronization is quick. can be in a state. Further, even if synchronization is lost due to noise or the like, the synchronization recovery operation is performed without performing a data transmission operation (step S22?: negative result), so that recovery can be quickly achieved in this case as well.

In addition, in the embodiment described in 1-1, the communication station applied the present invention to three heat bomb systems, but
The present invention is applicable not only to transmission systems but also to transmission systems having two or more communication stations.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to significantly reduce transmission errors compared to conventional systems, and data that can be quickly restored even when synchronization is lost between stations. The transmission system can be easily modified.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIGS. 3 and 4 are flowcharts showing the transmission processing operation thereof. 30.40... Transmission station, 3141... Data transmitting means, 32.42... Data receiving means, 33... Address transmitting means, 34... Address rotation means, 43... Address receiving means , 44... Receiving side address rotation means, 45... 7 "Response matching control means."

Claims (1)

[Claims] 1. In a data transmission system comprising a plurality of transmission stations each having a data transmitting means for transmitting one data in a transmission cycle and a data receiving means for receiving the transmitted data, how many times is the data transmitted in the transmission cycle? At least one or more of the transmission stations is provided with an address transmission means for transmitting an address indicating whether the address is 1, and an address rotation means for sequentially changing the address, and an address for receiving the address transmitted by the address transmission means. a receiving means, a receiving side address rotation means that internally generates an address that is sequentially changed in the same way as the receiving address, and compares the receiving address and the internally generated address, and if they are different, the internally generated address is changed to the receiving address. A data transmission system characterized in that the other transmission station is provided with address matching control means for synchronously controlling the addresses so that they match.