JPS62253242A - Line concentrating and distributing system - Google Patents

Abstract

PURPOSE:To simplify the constitution of a line concentrating and distributing system and, at the same time, to efficiently utilize a transmission line, by providing means which multiplex data of the quantity of plural frames at the line concentrating and distributing terminal and central device of the system. CONSTITUTION:A central device 1 changes signals from each terminal 5 to the data form in its exchange section 15 at its line concentrating and distributing circuit 14 through a buffer memory 23, etc. The changed sound signal and control signal are supplied to a buffer 24 through the circuit 14 and an assignment signal AGNi and preamble are combined in a series. The combined signal AGNi and preamble are modulated and amplified after data are added to them and sent to a transmission line 4 through a BPF 19. On the other hand, a line concentrating and distributing device 2 stores the signals from each terminal 5 in a buffer 43 through an interface 36 and sends them to a transmission line 3 through a BPF 41. The signal on the transmission line 4 is demodulated through a BPF 31 and the AGNi is decoded. After the AGNi is decoded, the output of a demodulator 33 is stored in the buffer 42.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a line concentration distribution system VC in which at least one remote terminal device is connected to a central unit via a line concentration distribution terminal.

[Technical background of the invention and its problems]

When configuring a network by connecting a plurality of terminal devices to a private branch exchange (PBX), it is generally very difficult to directly connect each of the terminal devices to the PBX by wire. There are also problems such as high equipment costs.

In particular, since terminal devices are often distributed in a plurality of buildings, or even in the same wire scrap, a predetermined number of terminal devices are distributed and arranged on different floors, so the above-mentioned friend problem is serious.

Conventionally, line concentration and distribution terminals are provided for each line waste and each layer, and these line concentration and distribution terminals are connected to a PBX, which is a central device, through wiring, for example, through uplinks and downlinks, and time sharing is performed between these terminals. It has been considered to transmit signals and to connect terminal equipment such as telephones to each of the above-mentioned line concentration and distribution terminals.

If the system is configured in this way, it will be easy to install the system consisting of the central equipment and the line distribution terminals, which will be the backbone of the system, and it will be possible to connect the terminal equipment to the line concentration and distribution terminal installed at the nearest location, so the network can be constructed flexibly.

However, as mentioned above, this system is a four-component system that transmits signals between the a number of concentration distribution terminals and the central equipment via one signal transmission path (up line and down line), and each concentration distribution Terminals are connected to the signal transmission path at different positions.

For this reason, the transmission path length between each concentration distribution terminal and the central device differs for each valley distribution terminal, and the difference in transmission delay time due to the difference in transmission path length causes signal transmission 7-J.
There will be a difference in time. Therefore, in order to time-division multiplex the transmission signals from each concentrator and distribution terminal without causing collisions, the transmission signal must be sent out in consideration of the transmission time (transmission delay time) for each concentrator and distribution terminal. It is necessary to control the timing. However, if the signal transmission timing from each concentrator/distributor terminal is controlled by simply taking into account the signal transmission delay time and allowing time margin, a problem arises in that the above-mentioned transmission path utilization efficiency 4 is significantly reduced. .

Therefore, the inventors of the present invention first send a test signal from the central device to each concentration distribution terminal in sequence, and on the other hand, the concentration distribution terminal that received this test signal sends the test signal back to the central device. Determine the transmission delay time for each of the above-mentioned line concentration distribution terminals from the return time of the test signal,
A line concentration distribution system was proposed in which this information (transmission delay time) is given to each of the east line distribution terminals to control the signal transmission timing described above.

Furthermore, as an improvement on this method, a patent application filed in 1983-2
As shown in No. 68824, signals are transmitted from a plurality of concentrating distribution terminals to a central device in a time-division manner via a first transmission line (up line), and signals are transmitted via a second transmission line (down line). In the line concentration and distribution system, the first and second transmission lines are configured to time-divisionally transmit signals from the central unit to each of the line concentration and distribution terminals, and to transmit and receive signals between the central unit and the east line distribution terminals. No. 46 τ, which is transmitted via means for transmitting a test signal in synchronization with a clock signal synchronized with the pilot signal on the second transmission path when the distribution terminal receives a test signal transmission request from the central device; The signal to be sent to the first signal transmission path is based on the transmission delay time from the first transmission path through the central device, through the second transmission path, and back to the concentrator distribution terminal. The device is characterized in that it is provided with a means for controlling the transmission timing.

Thus, according to the present invention, each concentrator/distributor terminal sends out a test signal, and the transmission delay time is measured from the return time to appropriately control the signal sending timing, so signal transmission is possible without placing a burden on the central equipment. It becomes possible to set the timing appropriately. Moreover, each concentrator and distribution terminal measures transmission delay time according to its own clock.

The above transmission delay time can be measured with a sufficiently high Muramaru.

Therefore, it is possible to prevent signal collisions without wasting the transmission path, and to transmit signals by effectively utilizing the transmission path. The transmission delay time of each concentrator/distributor terminal that can be connected to the transmission line is measured with high precision, and the signal sending timing is controlled, so there is no increase in the burden on the central equipment, and there is no change in the state of the transmission line. This has great practical effects, such as making it possible to always ensure an optimal signal transmission state regardless of the situation, and to ensure sufficient flexibility of the system.

However, in the above configuration, a window frame is provided to control the signal sending timing,
A device is required to perform highly accurate delay measurement, but
These devices are undesirable because they are complex and expensive.

[Object of the Invention] It is an object of the present invention to provide a line concentration distribution system that eliminates one or more drawbacks, has a W8-free configuration, and can efficiently utilize transmission lines.

[Summary of redundancy]

This invention relates to a line concentration and distribution system in which data is transmitted in a system in which a plurality of line concentration and distribution terminals are connected to one central unit via a pair of transmission paths. The present invention is characterized in that it is equipped with means for multiplexing data for frames, and that the data transmission is performed using the data multiplexed by this means.

〔Effect of the invention〕

According to the present invention, there is no need to provide a complicated timing sending means, and an inexpensive system can be realized.

[Embodiments of the invention]

An embodiment of this invention will be described.

FIG. 1 shows an outline of the information transmission system according to this embodiment. In the figure, 1 is a central device such as a PBX, and 2 is a line concentrator and distributor. Here, n line concentrators and distributors 2a to 2n are used.

One central device 1 is provided for a specific area, and a plurality of line concentration/distribution devices [2a to 2n are distributed and provided within this area. Moreover, the central device 1 and the line concentration/distribution devices 2a to 2n are
They are connected via a pair of transmission lines 3.4, and furthermore, a terminal 5 of a stuffing machine etc.
The connection is loose. Transmission lines 3.4 are unidirectional;
), transmission path 4 is downlink (down-/l'1n
k). The transmission path 3.4V'i and the physical V'C may be different media, or the same medium may be frequency-multiplexed.

In the system configured as described above, the central device 1 sets n frames for n line concentrators and distributors 2az2n, as shown in FIG. 22(a), for example. In other words, the second frame
The frames are assigned to the pseudoray distribution device 2b in this manner. This is a type of polling, and no signal collision occurs on the transmission line 4. Also, 1 frame is 125
With u sec, the central device l receives communication data Dote for n frames.

Dot2, --, DOin-1, and DOin are multiplexed and sent to the transmission path 4.

Here, the frame i sent out from the central unit i11 has a configuration as shown in FIG. 2(b).

Its structure includes, from the beginning, an assignment signal AGNi, a preamble, and transmission data Doff, . . . DOln. The assignment signal AGNi is the central unit 1
This is a signal indicating that data is to be transmitted and received between the line concentrator and distribution device ei. The green ampule is for each concentration distribution terminal 2a~
This is a signal that facilitates clock recovery in 2n.
For example, "1010...10".

Note that the subscript S identifies the line concentrator and distribution device, and the subscript 1- of i
n identifies terminal 5, and subscript 1-n of l identifies terminal 5.
I am separated from my family.

As is clear from the above, the central equipment 1dl sends and receives data to each of the line distribution terminals 2a to 2n.
The AGNi, preamble, and data to each terminal 5 are multiplexed to form a frame, and n frames to the connected line concentrators 2a to 2n are multiplexed and sent to the transmission line 4.

On the other hand, when the east line distribution device 21 receives the assignment signal AGN i applied to itself, the east line distribution device 21 transmits the transmission data Dr il, DIi2 . ..., DIin is multiplexed and sent onto the transmission path 3. This operation is performed by all line distribution terminals 2a to 2a which receive ANG i from the central device 1.
It will be held at 2n. However, each concentrator/distributor 28~2n
There is a no-signal period Tp on the transmission line 3 between frames from
is provided. This no-signal period Tp is provided to prevent collisions between signals from adjacent line concentration distribution terminals.

This zero (H period Tp) depends on the lowest propagation delay time Tdmax of this system. In other words, even if adjacent concentrator and distribution terminals are separated by a distance corresponding to the maximum propagation delay time, This ensures that there is no conflict between the parties.

This maximum propagation delay time Tdmaz means that when the line concentration distribution terminal 21 is connected to the farthest point from the central unit 1 on the transmission path, the data is transmitted through the line concentration distribution terminal 21 from the time when data is sent from the central unit 1. Center F: is the time until data is received at position I.

At this time, +hj also includes the signal processing time at the central device 1 and the line concentration distribution terminal 21.

For such a line distribution terminal 21, a fruit line distribution terminal 2i
+1 in the vicinity of the transmission path median value [1, 1, and send data I) Oi, DOi+1 from the central device 1, in order for the data DIi from the concentrator distribution terminal 21 to be received by the central device l again, Tdmax is required. This will cause a delay. On the other hand, there is almost no delay in the data DI 1+x from the line concentration distribution terminal 21+1. Therefore, data DIi.

Concerning DIi+, a collision may occur upon reception by the central device 1.

The above-mentioned no-signal period Tp is set to ensure that no collision will occur in one piece of data J even in such a worst case.

In addition, in the above description, the preamble signals in FIGS. 2(b) and 2(c) may be modified by means such as supplying a clock signal from the central unit 1 to each concentrating and distributing terminal 2 via another channel. If you do, it's not necessarily necessary.

Further, if the arrangement of each line concentration distribution terminal 2 is fixed, or if the central device 1 already knows the assignment signal AGNI 4, the assignment signal AGNI 4 becomes unnecessary.

Next, the configuration of the central device 1 and each line concentration/distribution terminal 2 will be explained according to the drawings.

In this embodiment, the central device 1 and the line concentration distribution terminal are characterized in that they have a buffer memory, and further,
The median value 1 has a function of generating the assignment signal AGN i, and the line concentration distribution terminal 2 has the function of generating the assignment signal AGN i.
It has the ability to decipher r.

The median value 111 is v, as shown in Figure 3, for example,
It includes an exchange section 15 consisting of a digital PBX capable of exchanging data and voice. The signal from each terminal 5 is
The data format is changed into the data format within the exchange section 15 in the line concentrator and distribution device 14 via the buffer memory 23 and the like. For example, audio signals.

The control number 1M is converted into the input format to the PCM highway and the input format to the data highway, respectively.

The signal is supplied to the converter 15.

After being exchanged by the converter 15, the audio signal and control signal are supplied to the buffer memory 24 via the line concentrator and distributor 14. At the same time, a frame synchronization signal is sent to the AGN generation circuit 25 a). The AGN generation circuit 25ri receives the frame synchronization signal and sequentially generates AGN signals, and also generates data to be sent (AGN (corresponding to number u) from among the data stored in the buffer memory 24). data).

A combining circuit 26 serially combines the AGN signal and the preamble. Following the preamble, the synthesis circuit 26 adds data DOI t , DO12, -, DOin in series and sends them to the modulator 16 . A modulator 16 modulates this signal. Amplifier 18. Band pass filter (BPF) 1
A signal is sent out to the transmission line 4 via 9.

When the signal from the transmission line 3 is received by the central device l, it is supplied to the demodulator 13 via the bandpass filter 1+ and m width 512. The demodulated signal is temporarily stored in the buffer memory 23.

In this buffer memory 23, after data for n frames is stored, data is sequentially sent to a line concentrator/distributor circuit 14, and then sent to a switching unit 1.
Supply to 5. The procedure after the data is sent from the buffer memory 23 until the data is supplied to the buffer memory 24 is the same as in the prior art. Of course in this process.

Delay times will occur. However, it is known that in audio transmission, if the delay time is 50 m5ec or more, unnaturalness occurs, but if it is less than that, there is no problem in practical use. Basically, this embodiment also causes a delay of n frames, but even if n=50, the delay is 125×50==6.25 m5ec, so there is no problem.

The data stored in the buffer memory 24 is combined with data for each line concentration distribution terminal 2n, an assignment signal is added by a synthesis circuit 26, and the data is modulated by a modulator 16. The assignment signal AGNi is the AGN generation circuit 25V
c, this is generated while identifying the line concentration distribution terminal of the other party based on the frame synchronization signal from the conversion unit 15.

The signal from modulator 16 is transmitted to amplifier 18 . It is sent out onto the transmission line 4 via the BPF 19.

On the other hand, the line concentrator/distributor 2 includes an interface circuit 36 connected to a plurality (n) of terminals 5, as shown in FIG. Signals from each terminal 5 are sent via an interface circuit 36.

It is stored in the buffer memory 43. The data of all terminals for 5 minutes is summarized here, and it is divided into the form shown in Figure 2 (C) and becomes BPF.
” 41, etc., onto the transmission line 3.

On the other hand, the signal on the transmission path 4 is demodulated by a demodulator 33 via a BPF 31 or the like. AGNi of the data shown in FIG. 2(b) is supplied to the AGN decoding circuit 37.

Then, if the AGNi signal corresponds to the relevant Kaigan distribution terminal 2, the output of the demodulator 33 is stored in the buffer memory 42.

In this process, the preamble is supplied to the clock generation circuit 34, and a clock signal CP purple is output. Also, the input to the buffer memory 42 is as follows.

Naturally, only the data DO1 is controlled, and these controls are performed under the control of a kakunta (not shown) or the like.

The data in the buffer memory 42 is sent to the frame decomposition circuit 35.
．． The signal is supplied to the terminal 5 via the interface circuit 36.

Further, the output system buffer memory 43 is also controlled based on the detection of the AGN signal.

In the above description, the data length of each frame may be variable. At this time, the assignment signal AGNt may contain this information.

Although the assignment signal is sent from the central device for each frame, it may be sent only once every n frames, and each concentrator terminal may send out frames in order based on its own address.

[Other embodiments of the invention]

Next, other embodiments of the invention will be described. In this embodiment, although the delay measurement technique is used, the longest transmission path is made longer by performing multiplexing as in the previous embodiment.

First, we will explain the delay measurement technique.

PBX as the central equipment and terminal equipment (% line distribution k
W (Concentrator/distributor
An example of a communication network system will be described using the following. b"tg,i, as shown in the central device 1, there are a plurality of terminal devices 2a, 2b, . . . 2 located away from the central device 1.
n is distributed. In this example, a bus-type signal transmission path having an Arab link 3 and a downlink 4 is wired from the central device 1, and the terminal equipment (it2a, 2b, . . .
- 2n is coupled to the signal transmission line with any devotion. A plurality of terminal equipment 5, such as a data processing device to a telephone, is coupled to each terminal device. A number (address) is assigned to each terminal device.

As shown in Fig. 2A, the central device l transmits transmission data (subframe data) DOl, DO2, ... Don to the terminal devices 2a, 2b, ... 2n, and inserts dummy data between them according to the order of addresses. The time and minute side lines 5<p are interpolated and sent on the downlink 4. Transmission data D11 . DI2.・-・DIn, Fig. 5 (
As shown in b).

Receive time division VC. Immediately after the last subframe data Don, the central unit sends an ADR'J'' frame containing address data specifying one of the terminal devices. It is configured as follows: a data section including the DON and ADR subframes, and a window section having a predetermined time length provided for measuring the transmission delay time of each terminal device.

One frame of data transmitted from the terminal devices 2a to 2n to the central device 1 consists of a data section having subframe data DII to DIn from the terminal devices and a window section following Din, as shown in FIG. 5(b). Consisted of. The terminal device specified by the address data M ice from the central device [1 sends a test signal in the window section in the data frame from the terminal device 8, and the central device sends a test signal in the window section in the data frame to the terminal device sends a test signal back to Upon receiving the test signal sent by itself, the terminal equipment measures the transmission delay time between it and the central equipment. By measuring this transmission delay time, each terminal device adjusts the signal sending timing, and as a result, collision of transmission signals from the terminal devices is prevented.

As an example, let us assume that the network shown in Fig. 1 can be connected to a maximum of 31 terminal devices, and that a maximum of 4 terminal devices 5 can be connected to each terminal device. In this case, the subframe data addressed to each terminal device 2 is
As shown in FIG. 3, it consists of a total of 40 bits: 2-bit synchronization code; 4-bit control data; 8-bit x 4-channel audio PCM data and 2-bit data. The synchronization signal is lO''. The ADH subframe is lO
pit.

Assuming that the window section is 284 bits + 2 bits (corresponding to the rising and falling edges of the window), the %l frame has a length of 1536 bits. The time length of l frame is 1
If it is 24μsec, the signal clock rate is 1536/
l 25 #5ec=12.288MHz. The structure of the subframe and l frame of the data transmitted from the terminal devices 2a to 2n to the central device #l is the same as the structure of the data from the central device to the terminal device.

FIG. 6 shows the format of the test signal subframe. As shown in the figure, the test signal consists of a total of lθ bits, including 2-bit timmy data, 2-bit synchronization signal (10), and 6-bit address data (terminal device number).

The ADH subframes sent from the central unit l have a similar format.

V for measuring the transmission delay time of each terminal device with pot accuracy rc
The pilot signal is sent out from the center i4[l, and the modified data signal is superimposed on the Piketsu H8 and transmitted on the signal transmission path. The frequency of the pilot signal is an integral multiple of the clock rate, for example 12.288 x 20 = 245.
Set it to 76MHz. In this case, it is possible to measure the transmission delay time with an accuracy of 1/10 to 1/20 of 1 bit time.

Below, Section 8. The configuration of the central device 1 and the terminal device 2 will be described with reference to FIG. 9.10r. The central mounting [1] shown in Figure 8
In the signal (g) transmitted from the terminal device 2 via the uplink 3, the unnecessary frequency band a is removed by the bandpass filter 1IVc, and the signal is amplified to a predetermined level l/mini by the amplifier 12. This received signal is sent to the demodulator 13 and is completely tuned.

The signal is applied to a distributor (frame disassembler) 14. The distributor 14 decomposes the signals transmitted from the terminal equipment [2a to 2n and divides all the audio PCM data into
4a couples control data to PBX 15 via data highway 14b.

At the PBX 15, signals from the terminal equipment undergo exchange processing. The sound P signal from the circle 2 is supplied to the PCM highway 16a, and the control data signal is supplied to the multi-grec f-C frame assembler) 16 via the data frame 11 way 16bk. The frame assembler 16 responds to the frame synchronization signal and assembles the input signal into the format shown in Section 51). The output signal of the frame assembler 16 is sent to the selector 1.
7 to the modulator 18V (applied, where FSK
It is modulated using a predetermined modulation method such as (frequency 5hift) (eying).

``Z its! The modulated data signal from amplifier 18 is applied to switch circuit 19V along with the received data signal from amplifier 12. Switch circuit 19 provides the output signal of modulator 18 or the output signal of amplifier 12 to amplifier 20 in response to the window signal. amplifier 20
The output signal of is coupled to the downlink 4 via a bandpass filter 21 and an OR gate 22. The switch circuit 19 receives the output signal of the amplifier 12, that is, the uplink signal from the terminal device during the window period of one frame.
The received test signal is sent to the downlink 4.

A pilot signal generation circuit 23 is provided, which constantly generates a 245°76MH sine wave through an OR gate 22.
A pilot signal of z is sent on the downlink 4. The modulated data signal is multiplied by the pilot signal VcM and transmitted on the downlink 4. Pilot signal generation circuit 2
3 is a pilot signal with a phase interval E (phase 1
(ocked) L/ta1 2.2881VfF (Generates the transmission clock signal Tx of z.

The aforementioned selector 17 selects the terminal device' from the frame assembler 16 during the data signal transmission period within one frame period.
The subframe data signals 1) Ol to Don addressed to 12a to 2n are sent to the window Jυ (quantitatively, the ADR subframe signal is selected and supplied to the ftA unit 181/.PB
Figure 9 (a) with a period of %l frame period from X15
) of the frame In(g) is applied to the reset terminal of the 1(-S flip-flop circuit 24 in addition to the frame assembler 16, and as a result, its Q output is as shown in FIG. 9(C).
goes low as shown.

The Q output of the free-lag frog 24 is coupled to the switch circuit 19 as a window signal. When the window signal is low, the switch circuit 19 selects the output of the modulator 18 and thus selects the data signal (DO17X7 to Don and M) from the Vc1 central unit as shown in FIG. 6D.
R) is sent on the downlink 4.

When the flip-flop circuit 24 is reset, a subframe counter 25 is enabled via an inverter 26, which counts the transmitted subframes. At the same time, the frame assembler 16 is enabled and starts transmitting subframe data DOI to Don.

The subframe power sonter 25 counts the transmission clock Tx.

A 40-decimal counter corresponding to the number of bits of one data subframe, 40, and the output of this 40-decimal counter are counted.
An n-ary counter corresponding to the number n of subframes sent out from the frame assembler 16? Be equipped. When n subframes have been counted by this n-ary counter, the ADH subframe generator 28 is activated and sends the subframe B to the selector I7, and at the same time the selector 17 selects the ADR subframe. Send the frame to modulator 18.

A that generates ADR data (terminal device address number)
A DH data generator 27 is provided to AD the ADR data.
The R subframe generator 28 is supplied. The generator 28 is
An ADH subframe is formed using a formant as shown in FIG. The ADR data generator 27 is a counter that counts frame synchronization signals, and is incremented every frame period.

As a result, the addresses of the terminal devices requested to transmit test signals are sequentially updated at intervals of one frame period.

The sub-7 frame counter 25 is configured to supply the FRAME TRNSMIT hM) signal shown in FIG. 9(b) to the reset terminal of the flip-flop circuit 24 at the time when the ADR subframe has finished being transmitted to the selector 17. As a result, the flip-flop circuit 24 is reset and the window 1
No. 8 goes low. The switch circuit 19 is placed in a standby state for returning a test signal from a terminal device that has received a test signal transmission request to that terminal device.

The configuration of the terminal device will be described with reference to FIGS. 10 and 11.

FIG. 10 shows the configuration of the terminal device, and FIG. 11 shows the configuration of the transmission timing adjustment (transmission delay time measurement) circuit. 11th
In the figure, it has been transmitted on the downlink 4. Fall 5
A frame signal having the configuration shown in FIG. 3(a) is applied to a demodulator 31, where it is demodulated. Pilot signal extraction circuit 3
2 is provided, which extracts the pilot signal from the signal transmitted on the downlink 4. The extraction circuit 32 can be formed by a bandpass filter. A reception clock recovery circuit 33 is connected to the output of the demodulator 31,
This restores the receive clock Rxk '6 to be phase-locked to the pilot signal extracted from the output signal of regulator 31. In response to the recovered reception clock δ, the frame disassembler 34 disassembles the subframe data addressed to itself and supplies the data to the terminal device 5 via the interface 35. The interface 35 transmits information from the terminal device 5 to the frame assembler 36vci. The frame assembler 36 assembles the data from the terminal device 5 in accordance with the format shown in FIG. 6 in response to a transmission clock phase-synchronized with the pilot signal from the transmission clock generation circuit 37. The output signal of the frame assembler 36 is supplied to the modulator 3BVC through an OR gate 37 and is modulated using the FSK method. The modulated subframe data is sent on the uplink 3. Frame assembler 36 includes one TRANSMIT ENA from transmit timing adjustment circuit 39 according to the present invention.
Enabled by the BLE signal to transmit subframe data. Subframe data transmission timing i
.

Adjusted according to the time between sending and receiving the test signal.

Next, the configuration of a mechanism for adjusting the transmission timing of subframe data according to the present invention will be described.

The carrier sense circuit 40 monitors the downlink 4, and when it detects an incoming modulated data signal, it sends the carrier sense signal to the subframe counter 41 VC1ssu.
e. The subframe counter 41 is enabled by the carrier sense signal and counts the received clock Rx from the received clock recovery circuit 33. The subframe counter 41 can be configured similarly to the subframe counter 25 in the central unit v, IVc. The subframe count number output of the subframe counter 41 is sent to the comparator 4.
2. The subframe counter 41 is also coupled to an address detector 44, which outputs an address detection signal at the timing of receiving an ADH subframe. The output of address register 45 is coupled to comparator 46, which in response to the address/rendering signal takes address data in the ADH subframe being received.

An address generator 43 is provided, which provides an address number assigned to the terminal.

Address generator 43 is coupled to comparators 42 and 46.

The comparator 42 compares the count value of the subframe counter 41 with the address number set in the address generator 43, and determines which of the subframe data DOI to Don sent to the terminal devices 2a to 2n is addressed to itself. A self-subframe detection signal is output at the timing of receiving subframe data. The self-subframe detection signal enables frame disassembler 34 to disassemble the data of the self-subframe. The decomposed data is supplied to the terminal device 5 via the interface 35. The output of comparator 42 also enables self-subframe synchronization detection circuit 47 to detect the synchronization signal contained in the self-destined subframe. The detection output signal of the detection circuit 47 is supplied to a transmission timing adjustment circuit 39, which will be described later.

Comparator 46 compares the ADH loaded in the address register.
The address data in the subframe is sent to the address generator 43.
When a match is detected, a test signal transmission request signal is output. This is coupled to a transmission timing adjustment circuit 39 and a test signal generation circuit 49. The output of comparator 46 also enables self test signal synchronization detector 48 to detect all synchronization signals in the test signals transmitted by itself and returned from central unit I. The self-test signal synchronization detection signal from the detector 48 is applied to the transmission timing adjustment circuit 39. Synchronous detection 5
47.48 is t from 1" to "0" of synchronization signal @10"
The transition is configured to detect transition.

The test signal generation circuit 49 is enabled by the test signal transmission request signal and starts transmitting the test signal subframe in the format shown in FIG. Test signal subframes are clearly transmitted during the window period.

The transmission timing Nu (transmission delay time measurement) circuit 39 will be described with reference to FIG. An initial setting register 50 is provided, in which one frame time length T is preset. When a test signal transmission request is detected by comparator 46, flip-flop 55 is set so that its Q output enables AND gate 53 to apply the extracted pilot signal to the clock terminal of down counter 51. . The rise of the test signal request signal is detected by the detector 57, and the rise detection signal is applied to the preset terminal of the down counter 51. As a result, the l-frame time length T is preset in the down counter 51, and the down counter 51 is counted down by the pilot signal. When a test signal transmission request is detected, transmission of a test signal subframe is started as described above. This test signal is sent via the uplink 3 to the central unit [1] and returned from the central unit via the downlink 4.

When the detector 48 detects the returned test signal, the self-test signal synchronization detection signal resets the 7rip 70ug 55. As a result, the H0 gate 53 is disabled and the counting operation of the down counter 51 is stopped. The count value of the down counter 51 at this time indicates the length of time from transmission to reception of the test signal. In this way, the transmission delay time between each terminal device and the central device is measured.

When the detector 47 detects subframe data addressed to itself from among the subframe data DOI to Don transmitted from the central device 1, the self frame synchronization detection signal sets the 7-lip 70-tub 56. As a result, AND gate 54 is enabled and supplies pilot a to down counter 52. When the rising edge of the self-subframe synchronization detection signal is detected by the detector 58, the detection signal is applied to the preset terminal of the down counter 52.

As a result, the transmission delay time data held in the down counter 51 is preset in the down counter 52. In other words, when subframe data addressed to itself is detected,
The down counter 52 counts down. When counting down to zero, the counter 52 is T1 SMIT
An ENABLE signal is output, which is applied to the reset terminals of the frame assembler 36 and the free lag frog 56. The pre-lag frog 56 setting disables the arm gate 54 and stops the counting operation of the counter 52. When the TRANSMIT ENABLE signal is asserted once, transmission of subframe data from the frame assembler 36 is started.

Next, measurement of transmission delay time in a network VC according to the present invention and adjustment of signal sending timing based on the measured transmission delay time will be described.

The window period tw necessary for measuring the transmission delay time shown in Figure 12 must satisfy the following conditions. The maximum transmission delay time on the downlink 4 from the central device l to the terminal equipment connected at the farthest position &2 is t dmax
*The maximum delay time on the AG link 3 is tumax, and the minimum delay time from the central device VC to the nearest terminal device is t dmin (=0).

Furthermore, it is assumed that a test signal of time duration tp is transmitted at the start of the window period tw in each terminal device.

As shown in FIG. 12(a), when a frame signal is transmitted from the central device l onto the downlink 4, the farthest terminal device is the terminal device 12119 (as shown in b7, h t dma
x and receive a frame signal. When the farthest terminal is requested to transmit a test signal, this terminal transmits a test signal of time length tp at the beginning of the window, as shown in FIG. 12(c). This test issue is received by the central unit lit, 1 after tumax. In order to return the test signal received by the central unit 1i1i to the terminal device kVC without causing a collision with the data signal, the central unit rj! Window period t in Ll
w'f: It is necessary to set it to be greater than the sum of tdmax, tdmin, and tpd. As shown in Figure 8112(e), since the test signal is received at the terminal device farthest from the central device with tdmax, the window period at the terminal device must also be set as described above. Ru. That is, the window period tw is set to tw≧t max + t dmin + tp r
In particular, it is possible for each terminal device to accurately measure the transmission delay time within the window period ttvVc regardless of its distance from the central device 1. As shown by the dotted line in FIG. 12, even in the case of a terminal device with zero delay time, the transmission delay time can be redundantly measured within the window period.

Delay time measurement in the terminal device 21 to which address number 1 has been assigned will be described with reference to FIG. 13. When the central unit 1 starts transmitting a 1-frame signal when 1=0, the terminal device 21 receives the 1-frame signal with a delay of di. If the time length of each subframe is Δ, the terminal device 2
1 receives the subframe addressed to itself after td1+(1-1)6.

On the other hand, from 1=0 to 1 frame time length T, the central device l
receives the signals from the terminal devices 2a to 2n, and transmits the subframe data from the terminal device [2i to T+(1-1
) In order to receive at the timing of Δ, the terminal device 2 i
It is necessary to start transmitting the signal at a timing of ri T+(i-1)Δ-tut.

This means that when the terminal device fl 2 i receives a signal addressed to itself from the central device 1 at tdi+(i-1)Δ, T+
This means that it is sufficient to start transmitting the signal at (i-1)Δ·tut. Therefore, as shown in FIG. 13, after the terminal device 21 receives a signal addressed to itself, Twait=('I
'+(i-1)Δ-tui)-(tdi+(i-
If signal transmission is started when the waiting time of J)Δ]=T-(tui+tdi)=T-tpd has elapsed, signal collision on the downlink 4 can be reliably avoided.

Referring to Flg, 8,! In the transmission timing adjustment circuit of the M terminal device 21, data corresponding to one frame time length T is loaded into the register 50. The down counter 51 counts down to T - (tut + tdi) after T from the register 50 is reset. Down counter 52Vc is Tw from counter 51
ait=T-(tui+tdi) is preset. The counter 52 counts down from T-(tui + tdi) to O, and then TRANSMIT EN
Take 1 ssue of ABLE M.

The above is the basis of this embodiment. On the other hand, in this embodiment, data is sent from half of the concentrator and distribution terminals 2 at a certain point, and at other times, data is sent from the remaining concentration and distribution terminals 2.
This is to exit data from the . That is, by using multiplexing, by halving the number of subframes assigned to the line concentration distribution terminal 2, the number of dummy bits left behind in the frame, etc. can be reduced, and thereby the window frame length can be set longer.

Before going into detailed explanation, I will briefly explain all the effects.

In the basic flJ+' mentioned above, as a specific example,
Transmission bit rate: 4.096Mbps Frame length:
125. /1 sec = 512 bit time Subframe length = 38 bits (internal M bit 2 bits) Dummy bit: 2 bits Subframe length: 12 If test signal request signal length = 5 bits, window frame length is 25 bits time:
61μsec In the above system, the window frame length is the maximum transmission M
Since the delay time must be set to be greater than or equal to the delay time Tdmax, the maximum transmission path length can be limited to approximately 820 m or less.

In contrast, with multiplexing, as described above.

Buffer memory capacity i: 36 x 2 bits Subframe length per frame 26 (number of multiplexing 2) If subframe length near 4 bits, window frame length: 49 pit time ≧ 12μSee, and the maximum transmission path length is approximately 1610 m. This is twice as many as in the previous example.

In addition, in conjunction with, the data transmission between each concentration distribution terminal 2 and the central unit 1 is 2 frames VC once, but the delay associated with this is 125 μaec x 2 = 250 μsec,
Delay time that generally feels unnatural in audio transmission 5
Compared to 0m5ecK, the delay time is one light minute shorter, which poses a practical problem! I don't.

(, the window frame length (bit time) and maximum transmission path length for buffer memory capacities of 36X4 and 36X6 are respectively 61 bit time 72010m and (j5
5 bits/2140m. The delay times associated with this are 500 Asec and 750 μSec, respectively, which pose no practical problem.

To specifically realize the above effect, 1, for example, classify the line concentration distribution terminals 2a to 2n into groups 2n.

This can be done by classifying into nine categories depending on whether the addresses given to the line concentration distribution terminals 2a to 2n are even or odd.

Then, at time t1, the central device 1 connects the line distribution terminals 2 with odd-numbered addresses as shown in FIG.
Transmission data DOI for a to 2n.

Dummy data (indicated by diagonal lines in the figure) for DO3, . In response to this, the dye distribution devices 2a to 2n having odd numbered addresses transmit data DII, DI3. . . . DIn is being transmitted, and the central unit l111t/'i receives this in a time-division manner.

Then, at the primary time point t2, data transmission is performed between the central device 1 and the line concentration distribution terminals 2a to 2n having even-numbered addresses.

In this embodiment, the odd number or even number of the address of the line concentration distribution terminal may be specified by using the address of the line concentration distribution terminal specified by the test signal transmission request signal sent from the central unit 1 every frame.

Similarly, when data is transmitted once every K frame, mod(x, nin, and own address mV) are sent to the concentrator/distributor terminal address All the line concentration and distribution terminals that have the same mod (m, k) will perform data transmission with the central device l.

Central device 1. The configuration of each line concentrator/distributor 5 is shown in FIGS. 14 and 15. These are schematic diagrams, but basically, buffer memories 23, 24, 42, and 43 are added to the configuration shown in FIGS. 8 and 11. window control circuit 22,
The delay measurement circuit 37 in the line concentration distribution terminal is the above-mentioned mod.
(m, k) is calculated, the target line concentration distribution terminal 2n is identified, and transmission or reception is controlled. In addition, the buffer memory capacity of each line concentration distribution terminal 2 is as follows.
The number of bits is MXK (μ is the number of subframe bits when multiplexing is not performed), and the buffer memory capacity of the central unit I is MXKXM bits.

Central device 1. Each (1) configuration of the gland collection distribution device Fi5 is
It is shown in FIGS. 14 and 15. Although these are schematic diagrams, they are basically shown in Figures 8 and 11.
In addition, buffer memories 23, 24, 42.43 are added to the window control circuit 22.43 in the central unit IVC. a delay measurement circuit at the line concentration distribution end 7;
17 calculates the mod (m, k) described above, identifies the target line concentration distribution terminal 2n, and sends %(,...
controls reception. The buffer memory capacity of each prefecture/image distribution terminal 2 is MXK bits (M is the subframe bit ii!J when multiplexing cannot be performed), and the buffer memory capacity of the central device 1 is MXKXM bits. It is.

[Brief explanation of drawings]

FIG. vJ1 to FIG. 15 are diagrams for explaining the present invention in detail. Agent Patent Attorney Yudo Nori Chika Kikuo Takehana: No changes to the contents of the engraving of the drawings) aD0 5 ゛-'' Figure 6 Figure 7 I Figure 11 Figure 12 Figure t=Q Figure 13 Figure f4 1':'>FAI

Claims (1)

[Claims] (1) A concentrator that transmits signals in a time-division manner from a plurality of concentrator and distribution terminals via a first transmission path, and transmits signals in a time-division manner from the central device to the concentrator and distribution terminals via a second transmission path. In the distribution method, the line concentration distribution terminal and the central device are equipped with means for multiplexing data for a plurality of frames, and the data multiplexed by the means is used to transmit a signal on the first and second transmission paths. A line concentration distribution method characterized by transmission.