JPS62232147A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62232147A JPS62232147A JP61075783A JP7578386A JPS62232147A JP S62232147 A JPS62232147 A JP S62232147A JP 61075783 A JP61075783 A JP 61075783A JP 7578386 A JP7578386 A JP 7578386A JP S62232147 A JPS62232147 A JP S62232147A
- Authority
- JP
- Japan
- Prior art keywords
- film
- chip
- bump
- semiconductor device
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229920001721 polyimide Polymers 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 6
- 230000001681 protective effect Effects 0.000 claims description 8
- 239000000843 powder Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000004806 packaging method and process Methods 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置構造に関し、特にTAB方式を実装
法とする半導体装置の表面保護膜構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device structure, and particularly to a surface protection film structure of a semiconductor device using the TAB method as a mounting method.
従来、この種の表面保護膜構造としては、半導体チップ
表面の全面にポリイミド膜を2〜5μmと薄く形成した
ものがある。また、他の例として。Conventionally, as this type of surface protection film structure, there is one in which a polyimide film is formed as thin as 2 to 5 μm over the entire surface of a semiconductor chip. Also, as another example.
TABIJ−ドと半導体チップ端部との接触防止の為に
、TABIJ−ドとの接続の為のバンプとチップ端部の
間に補助バンプを形成したものがある。In order to prevent contact between the TABIJ-dead and the edge of the semiconductor chip, there is one in which an auxiliary bump is formed between the bump for connection with the TABIJ-dead and the chip end.
上述した従来技術の第1の例の場合、表面保護膜が薄く
、TAB !J−ドとチップ端部が接触し、ショート不
良となるという欠点と、表面保論膜がポリイミドの為、
耐湿性に欠けるという欠点がある0
従来技術の第2の例の場合、補助バンプを、チッ7°端
部から、ダイシング時に発生するチッピング、欠けに対
し元号に余裕ある位置まで遠ざける必要性と%’1’
A Bリードとの接続バンプとチップ端部との間に形成
する必要性から、チップ面積の増加を余aなくされると
いう欠点がある。In the case of the first example of the prior art described above, the surface protective film is thin and TAB! The disadvantage is that the J-board and the chip end come into contact, resulting in a short circuit, and the surface protection film is made of polyimide.
In the case of the second example of the prior art, it is necessary to move the auxiliary bump away from the 7° edge of the chip to a position where there is enough room for chipping and chipping that occur during dicing. %'1'
Since it is necessary to form a connection bump with the A and B leads and the end of the chip, there is a drawback that the chip area is inevitably increased.
本発明の半導体装置の表面保膿膜構造は、i’AB方式
全実装法として用いる半導体装置において、チップ端部
からTABIJ−ド接続用のパップ周辺部ヲ櫟う領域の
第1の表面保護膜をバンプの高さに対し+Oμm〜−1
0μm厚で形成し、その他のチップ表面領域の第2の表
面保護膜t−0,5〜5μm厚で形成する事を特徴とす
る。The surface impregnating film structure of a semiconductor device of the present invention is a first surface protective film in a region extending from a chip end to a peripheral part of a pad for connecting a TABIJ in a semiconductor device used in an i'AB type full mounting method. +0 μm to -1 to the height of the bump
It is characterized in that it is formed with a thickness of 0 μm, and the second surface protective film t-0 on the other chip surface area is formed with a thickness of 5 to 5 μm.
次に本発明について図面全参照して説明する。 Next, the present invention will be explained with reference to all the drawings.
第1図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
実施例は、絶縁膜3.配線2,20μm厚の’l” A
Hリード接続用バンプ4全有するSi チップ1上の
表面保護膜として、チップ端部からパン14周辺にかか
る領域に形成された18μm厚の5i(J2粉末入りポ
リイミド膜5と、その他のチップ表面領域上に形成され
た窒化シリコン膜6を有する。In the embodiment, insulating film 3. Wiring 2, 20μm thick 'l'A
As a surface protection film on the Si chip 1, which has all the bumps 4 for H lead connection, 18 μm thick 5i (polyimide film 5 containing J2 powder and other chip surface areas) is formed in the area from the chip end to the area around the pan 14. It has a silicon nitride film 6 formed thereon.
第2図は第1図のバンプ4上に1’ A B リード7
を接続した状態を示す。Figure 2 shows 1' A B lead 7 on bump 4 in Figure 1.
Shows the state in which it is connected.
以上説明したように本発明は、TAB方式を実装法とし
て用いる半導体装置の表面保護膜を、バンブ厚に対し2
μm薄い厚さで271周辺に形成した、5i02粉末入
りポリイミド膜とその他のチップ表面に形成した窒化シ
リコン膜によって構成する事により、パン1周辺5i(
J2 入りポリイミド膜により、TABリードとチッ
プ端部のシ■−ト金防ぐ事が出来、その他のチップ表面
の窒化シリコン膜により、チップ内部回路を耐湿性良く
保護出来る効果がある。As explained above, the present invention provides a surface protective film for a semiconductor device that uses the TAB method as a mounting method, with a thickness of 2.
By forming a polyimide film containing 5i02 powder with a thickness of μm thin around 271 and a silicon nitride film formed on the other chip surfaces, 5i (
The J2-containing polyimide film can protect the TAB leads and the sheet metal at the end of the chip, and the silicon nitride film on the other chip surfaces has the effect of protecting the internal circuitry of the chip with good moisture resistance.
第1図は本発明の一実施例の縦断面図であり、第2図は
’1’ A B IJ−ドを接続した断面図である。
1・・・・・・Siチップ、2・・・・・・配線、3・
・・・・・IP!縁膜、4・・・・・・TAB接げ用バ
ンプ、5・・・・・・5i02粉末人りポリイミド膜、
6・・・・・・窒化クリコン膜、7・・・・・・TAB
IJ−ド。FIG. 1 is a longitudinal cross-sectional view of one embodiment of the present invention, and FIG. 2 is a cross-sectional view in which '1' ABIJ-do is connected. 1...Si chip, 2...wiring, 3.
...IP! Edge film, 4... TAB bonding bump, 5...5i02 powdered polyimide film,
6...Clicon nitride film, 7...TAB
IJ-do.
Claims (3)
いて、チップ端部からTABリード接続用のバンプ周辺
部を覆う領域の第1の表面保護膜をバンプの高さに対し
+0μm〜−10μm厚で形成し、その他のチップ表面
領域の第2の表面保護膜を0.5〜5μm厚で形成する
事を特徴とする半導体装置。(1) In a semiconductor device using the TAB method as a mounting method, the first surface protection film is formed in a region covering the periphery of the bump for TAB lead connection from the chip end to a thickness of +0 μm to −10 μm relative to the height of the bump. A semiconductor device characterized in that a second surface protection film is formed on other chip surface regions to have a thickness of 0.5 to 5 μm.
膜又はポリイミド膜、前記第2の表面保護膜が窒化シリ
コン膜又はSiO_2膜である特許請求の範囲第(1)
項記載の半導体装置。(2) Claim No. 1, wherein the first surface protective film is a polyimide film containing inorganic powder or a polyimide film, and the second surface protective film is a silicon nitride film or a SiO_2 film.
1. Semiconductor device described in Section 1.
膜、前記第2の表面保護膜がポリイミド膜である特許請
求の範囲第(1)項記載の半導体装置。(3) The semiconductor device according to claim (1), wherein the first surface protective film is a polyimide film containing inorganic powder, and the second surface protective film is a polyimide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61075783A JPH079907B2 (en) | 1986-04-01 | 1986-04-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61075783A JPH079907B2 (en) | 1986-04-01 | 1986-04-01 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62232147A true JPS62232147A (en) | 1987-10-12 |
| JPH079907B2 JPH079907B2 (en) | 1995-02-01 |
Family
ID=13586157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61075783A Expired - Lifetime JPH079907B2 (en) | 1986-04-01 | 1986-04-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH079907B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5518957A (en) * | 1991-10-10 | 1996-05-21 | Samsung Electronics Co., Ltd. | Method for making a thin profile semiconductor package |
| US6002164A (en) * | 1992-09-09 | 1999-12-14 | International Business Machines Corporation | Semiconductor lead frame |
| US6404051B1 (en) * | 1992-08-27 | 2002-06-11 | Kabushiki Kaisha Toshiba | Semiconductor device having a protruding bump electrode |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5333057A (en) * | 1976-09-09 | 1978-03-28 | Nec Corp | Bump type semiconductor device |
| JPS56114358A (en) * | 1980-02-15 | 1981-09-08 | Hitachi Ltd | Semiconductor device and manufacture |
-
1986
- 1986-04-01 JP JP61075783A patent/JPH079907B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5333057A (en) * | 1976-09-09 | 1978-03-28 | Nec Corp | Bump type semiconductor device |
| JPS56114358A (en) * | 1980-02-15 | 1981-09-08 | Hitachi Ltd | Semiconductor device and manufacture |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5518957A (en) * | 1991-10-10 | 1996-05-21 | Samsung Electronics Co., Ltd. | Method for making a thin profile semiconductor package |
| US6404051B1 (en) * | 1992-08-27 | 2002-06-11 | Kabushiki Kaisha Toshiba | Semiconductor device having a protruding bump electrode |
| US6605522B1 (en) | 1992-08-27 | 2003-08-12 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device having a protruding bump electrode |
| US6002164A (en) * | 1992-09-09 | 1999-12-14 | International Business Machines Corporation | Semiconductor lead frame |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH079907B2 (en) | 1995-02-01 |
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