JPS62130038A - Ciphering equipment - Google Patents

Abstract

PURPOSE:To increase number of ciphering keys and to intensify very much the degree of privacy call without increasing an error of a restored digital signal by changing a memory output irregularly not only in the unit of bits but also in the unit of frames. CONSTITUTION:A digital signal S and an irregular signal Y are added at an exclusive OR circuit 10 at the transmission side to obtain a ciphering signal Z. the signal.Z is inputted to a register 12 and stored in the unit of bits. Parallel outputs r1-rm are fed to a memory 22 as address information. Random number information outputs x1-xn in the memory 22 are inputted to a random selection circuit 11. The circuit 11 selects any among the information x1-xn in the unit of frames. The signal Z formed in this way is synthesized with a frame synchronizing signal FS and a start signal START, and the result is fed to a transmitter 20. Then a transmission switch 21 is turned on to raise the transmitter 20 and to set a counter 15 in the circuit 11 to an initial value. Since each counter is operated from the initial set value at the transmission and reception side in this way, when each memory content is coincident, the same selection is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application in Industry-1-] The present invention relates to an encryption device for encrypting and transmitting digital signals.

[Conventional technology]

An example of a conventional encryption device is shown in FIGS. 4 and 5.

Figure 4 shows the transmitting side, where the digital signal S and the irregular signal Y
are added using an exclusive OR circuit 2 to obtain an encrypted signal Z. The encrypted signal Z is sent to M-stage register 3.
Enter it and record it in bits! do. Its parallel output R,,
Using R, . . . , RM as address information, an irregular signal Y is obtained from a memory 1 that stores random numbers.

Irregular 1 random number Y: The random number written in memory 1 as 1.0 is output, and the encrypted signal Z is sent to the transmission switch 5.
The signal is transmitted from the transmitter 4 when the signal is turned on.

On the receiving side, as shown in FIG.
By using R2' + . , a reproduced digital signal S' is obtained.

In order to reproduce the digital signal S on the transmitting side on the receiving side, the contents of the memory 7 on the receiving side are matched with the contents of the memory 1 on the receiving side.

On the transmitting side, it is Z-8■Y (here, ■ means addition of m0d2). Therefore, if there is no error in the transmission path, z'-z and each register 3.6 is R,'
=R,,R2'=R2,...+Rjl'-R8 holds, so if the contents of memory 7 and memory 1 match, Y'-Y, and S'=z'■Y '-Z■Y-(
It can be seen that S■Y)■Y=S.

[Problem that the invention seeks to solve]

Conventional encryption devices have a simple configuration and employ a non-linear encryption method, so they have the advantage of providing extremely strong privacy strength.

However, increasing the number of random numbers, that is, the number of encryption keys, has the disadvantage of becoming more susceptible to transmission errors. For example, in order to increase the variety of random numbers, it is necessary to increase the number of addresses in memories 1 and 7, and for this purpose, the number of stages M of registers 3.about.6 must be increased. On the other hand, an error in the received signal Z' causes an error in the output Y' until it passes through the M stages of registers 6. At this time, normal reproduction information cannot be obtained from the output S', but this state continues for an M-bit period.

However, when the number of encryption keys is increased, there is a problem that the digital signal S' cannot be reproduced normally for a long time due to a transmission error.

An object of the present invention is to provide an encryption device that can increase the number of encryption keys without increasing errors in the reproduced digital signal and has strong privacy strength.

[Means for solving problems]

The present invention encrypts and outputs a digital signal on the transmitting side,
In an encryption device that reproduces a digital signal on the receiving side, the sending side includes an encrypted signal forming means that adds the digital signal and the irregular signal to form an encrypted signal, and an encrypted signal from the encrypted signal forming means. Store the signal in bits rp−,
first register means for outputting a plurality of bits in parallel;
The parallel output from this first register means is input as address information, and corresponding to each address, n bits (n is 2
First random number information record 1 that outputs random number information (an integer greater than or equal to)
．． α means, this first random number information record 1, and a first selection means that randomly selects one of the n-bit random number information of the α means in frame units and outputs it as an irregular signal [1fj]. The receiving side includes a second register means having the same number of stages as the first register means, which records the received encrypted signal bit by bit and outputs a plurality of bits in parallel; a second random number information storage means having the same memory content as the first random number information storage means, which inputs parallel outputs from the register means as address information and outputs n-bit random number information corresponding to each address; n of this second random number information storage means
a second selection means for obtaining an irregular signal by selecting one of the bit random number information in a frame unit synchronized with the transmitting side in the same operation as the first selection means; It is characterized by comprising a digital signal reproducing means for reproducing a digital signal by adding encrypted signals.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows the configuration of a transmitting system to which the encryption device of the present invention is applied. In the figure, 10 is an exclusive OR circuit;
12 is an m-stage register, 22 is a memory for storing random numbers of 1.0, 11 is a random selection circuit, 16 is a frame l, a synchronization pulse generator, and 17 is a frame synchronization signal generation circuit 17.1
8 is a start signal generation circuit, 19 is a frame synthesis circuit,
20 is a transmitter, and 21 is a transmission switch. The random selection circuit 11 includes a selection circuit 13, a memory 14 for storing random numbers, and a counter 15.

In the transmitting system described above, the digital signal S and the irregular signal Y are added by the exclusive OR circuit IO to obtain the encrypted signal Z. This encrypted signal Z is input to the register 12 and stored bit by bit. The parallel output 'I+r2+..., r' is supplied to the memory 22 as address information. Random number information output xIt of n bits (n is an integer greater than or equal to 2) of memory 22 X2+...1x1
1 is input to the selection circuit 13 of the random selection circuit 11. The random selection circuit 11 selects one of the random number information xl+, X2+, . . . , xo on a frame-by-frame basis.

The frame synchronization pulse output from the frame synchronization pulse generator 16 is input to the counter 15, and the parallel outputs of the counter 15, b2. . . , b specifies the address of the memory 14, and the random number output a1 . a2. ....

The selection contents of the selection circuit 13 are changed by a. That is, the counter 15 and the memory 14 constitute a random number generator, which generates random numbers on a frame-by-frame basis.

Note that as the random number generator, it is also possible to use a PN (pseudo-noise) signal generation circuit or the like. The selection circuit 13 selects the random number information output from the memory 22 based on the random number output from Memo January 4, inputs it as an irregular signal Y to the exclusive OR circuit 10, and adds it to the digital signal S to generate the code. Converting signal 2 is obtained.

The encrypted signal Z formed as described above is transmitted in the following manner. First, the encrypted signal Z is input to the frame synthesis circuit 19. In the frame synthesis circuit 19, a frame synchronization signal FS generated in the frame synchronization signal generation circuit 17 in response to the output of the frame synchronization pulse generator 16, that is, a frame synchronization pulse, and a frame synchronization signal FS generated in the start signal generation circuit 18 in response to the transmission switch 21. Start signal 5TA
RT and the encrypted signal Z to generate the transmission data T.
DATA is obtained and sent to the transmitter 20. Then, by turning on the transmission switch 21, the transmitter 20 is started up and the counter 15 in the random selection circuit 11 is set to an initial value.

FIG. 3 shows the frame structure of the output TOAT of the frame synthesis circuit 19 and the relationship between the frame synchronization pulse output from the frame synchronization pulse generator 16 and TDATA. In the figure, 5TART is a start signal, FS is a frame synchronization signal, and Z is an encryption signal.

FIG. 2 shows the configuration of a receiving side system for reproducing a digital signal from the encrypted signal sent from the transmitting side shown in FIG. In the figure, 23 is a receiver, 24 is a division circuit, 2
5 is a frame synchronization signal detection circuit, 26 is a start signal detection circuit, 27 is an m-stage register, 32 is a memory for storing random numbers, 28 is a random selection circuit, and 33 is an exclusive OR circuit. The random selection circuit 28 includes a selection circuit 29;
Write down the random number 1. ! It consists of a memory 30 and a counter 31.

In the above receiving system, the received data RDATA, which is the output of the receiver 23, is the transmitted data T shown in FIG.
DATA is received, and is input to the separation circuit 24, the frame synchronization signal detection circuit 25, and the start signal detection circuit 26, respectively. In the separation circuit 24, RDA
Separate the encrypted signal Z' from TA. The separated encrypted signal Z' is equal to the encrypted signal Z on the transmitting side if there is no error in the transmission path.

Furthermore, from RDATA, a start detection circuit 26 detects a start signal 5TART, and a frame synchronization signal detection circuit 25 detects a frame synchronization signal FS. The output FS of the frame synchronization signal detection circuit 25 is the third
Like the frame synchronization pulse in the figure, the received data RDATA
The encrypted signal Z' is synchronized with
used to separate only. The frame synchronization signal FS is also supplied to the counter 31 of the random selection circuit 28.

Encrypted signal Z' is input to register 27 and exclusive OR circuit 33. The register 27 stores the encrypted signal Z' in bit units, and its parallel output r1'.

r2', . . . , r1' are used as address information of the memory 32. The memory 32 generates an n-bit signal x1' as random number information corresponding to the designated address.

x2',...,x,,' is output. One of these signals is selected by the selection circuit 29 of the random selection circuit 28 and inputted to the (-1F) OR circuit 33 as the irregular signal Y'.

The random selection circuit 28 operates in exactly the same way as the random selection circuit 11 on the transmitting side. That is, the counter 31 counts the output FS of the frame synchronization signal detection circuit 25, and also counts the output FS of the start signal detection circuit 26.
Initialized by TART. The memory 30 is operated using the parallel outputs S, /, b2/, ..., b9' of the counter 31 as address information, and its random number output aI' +
The selection contents of the selection circuit 29 are controlled by a2', . . . , a,'. The selection circuit 29 selects one of the n-bit input signals Xl'+X2'+...+Xl'1' to obtain an irregular signal Y'.

The exclusive OR circuit 33 adds the irregular signal Y' from the random selection circuit 28 and the encrypted signal Z' from the separation circuit 24 to reproduce the digital signal S'.

As explained above, since the counter 15 on the sending side and the counter 31 on the receiving side operate from the same initial setting value,
If the contents of the memo 1J14 on the sending side and the memo 1J14 on the receiving side match, the random selection circuit 11 on the sending side and the random selection circuit 28 on the receiving side make the same selection. Therefore, the sending side memory 22 and the receiving side memory 3
If the contents of 2 match, s'-s can be read as a reproduced signal when there is no transmission error, as in the conventional case.

This can be explained logically as follows.

First, when there is no error in the transmission path, z'-z.

Next, for the case where the contents of memories 22 and 32 match, x,' ``x, l X2' ``X2+ '''+x
,,' = x, holds true. Therefore, memories 14 and 3
For the case where the contents of 0 match, the random selection circuit 1
1 and 28 have the same operation, Y'=Y, therefore, s'-z'■Y'=Z■Y=(S■Y)■Y
=S.

As explained below, in this embodiment, not only the memories 22 and 32 but also the memo stations 4 and 30 are used as parameters variable depending on the key information, so the random numbers stored in the memos 1J and 22 and 32 are used. The number of types can be reduced. That is, since the number of addresses in memory 22゜32 can be reduced, the number of addresses in registers I2 and 27 can be reduced.
The number of stages m can be selected to be small.

If the number of stages m of registers 12 and 27 is selected to be small, an error will occur in the transmission path, and therefore the output of register 27 'l' * '2' +...+ r
Even if there is an error in %+ and as a result an error occurs in the output Y', since the output &m of the register 27 is small, the time during which the digital signal is not normally reproduced due to the transmission path error is shortened. In other words, as long as frame synchronization is established, the error in Y' will not increase even if the number of random numbers in the memory 30 is very large. Therefore, in this embodiment, the reproduced digital signal Z'
The number of confidential keys (the types of random numbers that can be used) can be significantly increased without increasing the number of errors.

Furthermore, the encryption device of this embodiment does not randomize only in bit units as in the conventional device, but also changes the output of the memory 22 irregularly in frame units. It will be done.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain an encryption device that is resistant to transmission path errors even when the number of keys is significantly increased. Further, according to the present invention, since the encryption is performed by making irregular changes not only in bit units but also in frame units, it is possible to obtain an encrypted signal with extremely strong confidential communication strength.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a transmitting system to which the present invention is applied, Fig. 2 is a block diagram of a receiving system to which the present invention is applied, and Fig. 3 shows the operation of the systems in Figs. 1 and 2. A time chart for explanation; FIG. 4 is a configuration diagram of a transmission system related to a conventional cryptographic device; FIG. 5 is a configuration diagram of a reception system related to a conventional cryptographic device. 10.33 ・・・・・・・・・・・・・・・・・・
Exclusive OR circuit 12.27 ・・・・・・・・・・・・
・・・・・・・・・ Register 14, 22.30.32
・・・・・・ Memory 13.29 ・・・・・・・・・
・・・・・・・・・・・・ Selection circuit 15.31 ・・
・・・・・・・・・・・・・・・ Counter agent
Patent Attorney Yoshiyuki Iwasa Figure 4

Claims (2)

[Claims] (1) In an encryption device that encrypts and outputs a digital signal on the sending side and reproduces the digital signal on the receiving side, the sending side adds the digital signal and the irregular signal to form an encrypted signal. a signal forming means, a first register means for storing the encrypted signal from the encrypted signal forming means bit by bit and outputting a plurality of bits in parallel; and an address for the parallel output from the first register means. a first random number information storage means that inputs as information and outputs n-bit (n is an integer of 2 or more) random number information corresponding to each address; and n-bit random number information of the first random number information storage means. a first selection means for irregularly selecting one of the following on a frame-by-frame basis and outputting the irregular signal as the irregular signal; the receiving side stores the received encrypted signal in bits and stores a plurality of bits in parallel; A second register means having the same number of stages as the first register means to be output, and parallel outputs from the second register means are input as address information, and n-bit random number information is output corresponding to each address. A second random number information storage means having the same storage content as the first random number information storage means, and a frame unit in which any of the n-bit random number information in the second random number information storage means is synchronized with the transmitting side. a second selection means that selects and obtains an irregular signal in the same manner as the first selection means; and a digital signal reproduction means that adds the irregular signal and the encrypted signal to reproduce a digital signal. An encryption device comprising: (2) In the encryption device according to claim 1, the first selection means includes a first random number generator that generates random numbers in units of frames, and a random number generator that generates random numbers from the first random number generator. a first selection circuit that is controlled by a random number output and selects one of the n-bit random number information from the first random number information generation means, and the second selection means is synchronized with the transmitting side. A second random number generator that generates random numbers in units of frames and a random number output from the second random number generator to select one of n-bit random number information from the second random number information generation means. An encryption device comprising a second selection circuit.