JPS6127681A - Field effect transistor with superlattice structure channel part - Google Patents
Field effect transistor with superlattice structure channel partInfo
- Publication number
- JPS6127681A JPS6127681A JP14795784A JP14795784A JPS6127681A JP S6127681 A JPS6127681 A JP S6127681A JP 14795784 A JP14795784 A JP 14795784A JP 14795784 A JP14795784 A JP 14795784A JP S6127681 A JPS6127681 A JP S6127681A
- Authority
- JP
- Japan
- Prior art keywords
- superlattice structure
- field effect
- effect transistor
- layer
- channel part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure
Landscapes
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、超格子構造を用いた電界効果トランジスタに
関し、特に超格子構造内に形成されるポテンシャル井戸
を主にチャネル部として使用した高速動作可能な電界効
果トランジスタに関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a field effect transistor using a superlattice structure, and in particular to a field effect transistor using a potential well formed in the superlattice structure as a channel portion. Regarding possible field effect transistors.
〔従来の技術と発明が解決しようとする問題点〕従来の
電界効果トランジスタにおいては、キャリアの蓄積され
るチャネル部がゲート絶縁膜と半導体の界面近傍に集中
するため、チャネル内を走行するキャリアは、界面単位
あるいはゲート絶縁膜内のキャリア捕獲準位によって捕
獲される。キャリアを捕獲した準位は、チャネル内を走
行するキャリアを散乱させて移動度の低下を招いたり、
制御不可能な再放出によるキャリア生成を行って、ヒス
テリシス特性や特性変動を生じる原因となる。[Problems to be solved by the conventional technology and the invention] In conventional field effect transistors, the channel region where carriers are accumulated is concentrated near the interface between the gate insulating film and the semiconductor. , captured by a carrier trap level in an interface unit or a gate insulating film. The level that captures the carriers scatters the carriers traveling in the channel, causing a decrease in mobility.
Carrier generation occurs due to uncontrollable re-emission, which causes hysteresis characteristics and characteristic fluctuations.
このためキャリア捕獲準位は、誤動作の原因となったり
、高速動作の大きな障害となっている。For this reason, the carrier trapping level causes malfunctions and is a major obstacle to high-speed operation.
本発明は、超格子構造をチャネル部に使用することによ
り、安定で且つ高速動作可能な電界効果トランジスタを
提供する。The present invention provides a field effect transistor that is stable and capable of high-speed operation by using a superlattice structure in a channel portion.
超格子構造は、禁制帯幅の異なる２種類の半導体の各極
めて薄い膜、すなわちそれぞれ数百Å以下の薄膜を交互
に積層して形成したものであり、結晶あるいは非晶質の
いずれの材料の場合も可能である。A superlattice structure is formed by alternately stacking extremely thin films of two types of semiconductors with different forbidden band widths, each thin film having a thickness of several hundred Å or less, and can be made of either crystalline or amorphous materials. It is also possible.
以下に、本発明の詳細を実施例にしたがって説明する。 The details of the present invention will be explained below based on examples.
第１図は、本発明の１実施例である薄膜電界効果トラン
ジスタの断面図である。図において、１は半導体のバル
ク層、２は動作時にチャネルが形成されるヘテロ接合超
格子構造の活性層、３はソース、４はドレイン、５はゲ
ート電極、６はＳ８０□あるいは８□３Ｎ４などのゲー
ト絶縁膜を表している。FIG. 1 is a cross-sectional view of a thin film field effect transistor that is an embodiment of the present invention. In the figure, 1 is a semiconductor bulk layer, 2 is an active layer of a heterojunction superlattice structure in which a channel is formed during operation, 3 is a source, 4 is a drain, 5 is a gate electrode, 6 is S80□ or 8□3N4, etc. represents the gate insulating film.
本実施例では、ヘテロ接合超格子構造の活性層２の厚さ
は約２００人であるが、２００乃至２０００人の範囲に
製作することができる。キャリアは、ソースおよびドレ
イン間で、活性層２の超格子構造内に形成されるポテン
シャル井戸層に拘束された状態で、２次元的に高速度で
伝播する。図中の実線の矢線は電子流を表している。In this embodiment, the thickness of the active layer 2 having a heterojunction superlattice structure is about 200 layers, but it can be manufactured to a thickness in the range of 200 to 2000 layers. Carriers propagate two-dimensionally at high speed between the source and drain while being restrained by the potential well layer formed within the superlattice structure of the active layer 2. The solid arrow in the figure represents the electron flow.
ヘテロ接合超格子構造は、結晶のＳ□と５ｉｔ−ｘＧ、
Ｘ、あるいは非晶質Ｓ、とＳ １．−、ＮＸまたはＳ、
とＳ□Ｉ−ＸＣＸなどの超薄層を交互に積層して形成さ
れる。第２図はその１例を示したもので、７は水素を含
有する非晶質のａ ＳｉトｘＮｘ：Ｈ層、８は非晶質の
ａ−３ｚ：Ｈ層であり、層７と層８は交互に積層されて
いる。各層の厚さＷは、３０〜２００人の範囲が適当で
ある。The heterojunction superlattice structure consists of crystal S□ and 5it-xG,
X, or amorphous S, and S 1. -, NX or S,
It is formed by alternately stacking ultra-thin layers such as SI-XCX and S□I-XCX. Figure 2 shows one example, where 7 is an amorphous aSiTxNx:H layer containing hydrogen, 8 is an amorphous a-3z:H layer, and layer 7 and layer 8 are alternately stacked. The appropriate thickness W of each layer is in the range of 30 to 200 people.
第３図は、第２図に示した超格子構造のエネルギーバン
ド図である。図示のように、ａ Ｓ＝＋−８Ｎｘ ：
Ｈ（ｘ−０，２４）層の禁制帯幅は１ 、９６ｅ Ｖ
であり、ａ−３１：Ｈ層のそれは１ 、７２ｅ Ｖであ
って、後者の層は前者の層に対してポテンシャル井戸と
なりでいる。FIG. 3 is an energy band diagram of the superlattice structure shown in FIG. 2. As shown, a S=+-8Nx:
The forbidden band width of the H(x-0,24) layer is 1,96e V
That of the a-31:H layer is 1.72e V, and the latter layer serves as a potential well with respect to the former layer.
第４図は、第１図に示した薄膜電界効果トランジスタに
おける、フラットバンド状態（ゲート電圧無印加時又は
小さいゲート電圧で実現される）でのエネルギーバンド
図を示したもので、第５図は、これに比較的大きい正の
ゲート電圧Ｖ６を印加し、チャネルを形成した状態での
エネルギーバンド図を示したものである。また第６図は
、比較のため、超格子構造をもたない従来の薄膜電界効
果トランジスタに比較的大きい正のゲート電圧印加時に
おけるエネルギーバンド図を示したものである。Figure 4 shows the energy band diagram of the thin film field effect transistor shown in Figure 1 in a flat band state (achieved when no gate voltage is applied or with a small gate voltage). , an energy band diagram is shown in a state where a relatively large positive gate voltage V6 is applied to this to form a channel. For comparison, FIG. 6 shows an energy band diagram when a relatively large positive gate voltage is applied to a conventional thin film field effect transistor that does not have a superlattice structure.
電界効果トランジスタのチャネル部に超格子構造を導入
することにより、安定で且つ高速の動作が得られるのは
次の３つの理由による。Stable and high-speed operation can be achieved by introducing a superlattice structure into the channel portion of a field effect transistor for the following three reasons.
第１には、超格子構造内に形成されるポテンシャル井戸
層に閉じ込められたキャリアは、井戸幅がキャリアのド
・ブロイ波長程度（数十人）に狭い場合には、量子サイ
ズ効果により、キャリアが２次元的にのみ分布する２次
元キャリアガス状態となることである。この２次元キャ
リアガス状態において、井戸層内のキャリア輸送時の散
乱は、２次元等エネルギー面内での散乱のみが支配的と
なってキャリア散乱確率が減少するため、キャリア移動
度が増大する。First, carriers confined in a potential well layer formed in a superlattice structure are This results in a two-dimensional carrier gas state in which the carrier gas is distributed only two-dimensionally. In this two-dimensional carrier gas state, scattering during carrier transport within the well layer is dominated by scattering only within the two-dimensional iso-energy plane, reducing carrier scattering probability and increasing carrier mobility.
第２には、第５図中にキャリアが電子の場合についてｅ
で示されているように、キャリアの電子θは、超格子構
造内の各ポテンシャル井戸層に閉じ込められ、ゲート絶
縁膜から離れて形成されたチャネルを走行するようにな
ることである。そのため、第６図に示す従来例の場合ｐ
ように、ゲート絶縁膜界面に存在する界面準位により電
子ｅが捕獲されたり、界面付近の固定電荷により散乱を
うけて、キャリア移動度が低下するというような不具合
点が大幅に改善される。Second, regarding the case where the carrier is an electron in Figure 5, e
As shown in , carrier electrons θ are confined in each potential well layer in the superlattice structure and travel through a channel formed away from the gate insulating film. Therefore, in the conventional example shown in FIG.
Thus, problems such as electrons e being captured by the interface states existing at the gate insulating film interface or scattered by fixed charges near the interface, resulting in a decrease in carrier mobility, can be greatly improved.
第３には、第５図のエネルギーバンド図に示されるよう
に、超格子構造を用いた場合、キャリア（電子）の分布
が各ポテンシャル井戸層に空間的に分離されて分布する
ため、ゲート電圧■。の印加によって生ずるバンドの曲
がりが均一化され、第６図の従来例のものでは、強（バ
ンドの曲がる領域が表面から１００人乃至２００人程度
の深さしかなかったのにくらべて、表面層よりさらに深
い位置（たとえば数百人）にまで及ぶことである。Thirdly, as shown in the energy band diagram in Figure 5, when a superlattice structure is used, the distribution of carriers (electrons) is spatially separated in each potential well layer, so the gate voltage ■. The bending of the band caused by the application of It extends to even deeper positions (for example, hundreds of people).
これにより、平均電界強度を表面層で低下させることが
でき、強電界下での界面準位やゲート絶縁膜内の捕獲準
位へのキャリア捕獲を抑制することが可能となる。Thereby, the average electric field strength can be reduced in the surface layer, and it becomes possible to suppress carrier trapping in the interface level or the trap level in the gate insulating film under a strong electric field.
なお、本発明は、薄膜電界効果トランジスタを実施例と
して説明されたが、一般のＭＯ３型電界効果トランジス
タにも適用できることは容易に理解できるところである
。Although the present invention has been described using a thin film field effect transistor as an example, it is easy to understand that it can also be applied to a general MO3 type field effect transistor.
また、本実施例で使用された非晶質半導体Ｓ８、Ｓｉｌ
□ＮＸは本発明に適用可能な１例にすぎず、広い範囲の
材料の組み合わせが可能である。結晶半導体についても
同様である。In addition, the amorphous semiconductor S8 used in this example, Sil
□NX is only one example applicable to the present invention, and a wide range of combinations of materials are possible. The same applies to crystalline semiconductors.
以上のように、本発明によれば、超格子構造を電界効果
、トランジスタのチャネル部に使用することで、キャリ
ア移動度の増大とともに、捕獲準位によるキャリア捕獲
の抑制とが図られ、誤動作が極めて少なくて高速動作が
可能な電界効果トランジスタを提供することができる。As described above, according to the present invention, by using a superlattice structure in the field effect and channel portion of a transistor, carrier mobility is increased and carrier trapping by trapping levels is suppressed, thereby preventing malfunction. It is possible to provide a field-effect transistor that can be operated at high speed with extremely small quantities.
第１図は本発明の１実施例の薄膜電界効果トランジスタ
の断面図、第２図はへテロ接合超格子構造の１実施例を
示す図、第３図は第２図に示すヘテロ接合超格子構造の
エネルギーバンド図、第４図は第１図に示す実施例のフ
ラントバンド状態の時のエネルギーバンド図、第５図ば
同じ実施例のゲート電圧印加時のエネルギーバンド図、
第６図は従来の薄膜電界効果トランジスタのゲート電圧
印加時のエネルギーバンド図である。
図中、１はバルク層、２はヘテロ接合超格子構造の活性
層、３はソース、４はドレイン、５はゲート電極、６は
ゲート絶縁膜を示す。FIG. 1 is a cross-sectional view of a thin film field effect transistor according to an embodiment of the present invention, FIG. 2 is a diagram showing an embodiment of a heterojunction superlattice structure, and FIG. 3 is a heterojunction superlattice shown in FIG. The energy band diagram of the structure, FIG. 4 is the energy band diagram of the embodiment shown in FIG. 1 in the flant band state, and FIG. 5 is the energy band diagram of the same embodiment when gate voltage is applied.
FIG. 6 is an energy band diagram of a conventional thin film field effect transistor when a gate voltage is applied. In the figure, 1 is a bulk layer, 2 is an active layer with a heterojunction superlattice structure, 3 is a source, 4 is a drain, 5 is a gate electrode, and 6 is a gate insulating film.
Claims (1)
交互に積層して製作されるヘテロ接合超格子構造のチャ
ネル部をもつ電界効果トランジスタ。A field effect transistor has a channel portion with a heterojunction superlattice structure, which is manufactured by alternately stacking extremely thin films of two types of semiconductors with different forbidden band widths.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14795784A JPS6127681A (en) | 1984-07-17 | 1984-07-17 | Field effect transistor with superlattice structure channel part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14795784A JPS6127681A (en) | 1984-07-17 | 1984-07-17 | Field effect transistor with superlattice structure channel part |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6127681A true JPS6127681A (en) | 1986-02-07 |
| JPH0224025B2 JPH0224025B2 (en) | 1990-05-28 |
Family
ID=15441903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14795784A Granted JPS6127681A (en) | 1984-07-17 | 1984-07-17 | Field effect transistor with superlattice structure channel part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6127681A (en) |
Cited By (46)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61230374A (en) * | 1985-04-05 | 1986-10-14 | Seiko Epson Corp | Field-effect type transistor and manufacture thereof |
| JPS62279672A (en) * | 1986-05-28 | 1987-12-04 | Kanegafuchi Chem Ind Co Ltd | semiconductor equipment |
| JPS6394681A (en) * | 1986-10-08 | 1988-04-25 | Semiconductor Energy Lab Co Ltd | Manufacture of insulated-gate field-effect semiconductor device |
| JPS6394682A (en) * | 1986-10-08 | 1988-04-25 | Semiconductor Energy Lab Co Ltd | Manufacture of insulated-gate field-effect semiconductor device |
| JPS6394680A (en) * | 1986-10-08 | 1988-04-25 | Semiconductor Energy Lab Co Ltd | Insulated-gate field-effect semiconductor device |
| US4806998A (en) * | 1986-06-30 | 1989-02-21 | Thomson-Csf | Heterojunction and dual channel semiconductor field effect transistor or negative transconductive device |
| US4908678A (en) * | 1986-10-08 | 1990-03-13 | Semiconductor Energy Laboratory Co., Ltd. | FET with a super lattice channel |
| US5051786A (en) * | 1989-10-24 | 1991-09-24 | Mcnc | Passivated polycrystalline semiconductors quantum well/superlattice structures fabricated thereof |
| EP0694756A2 (en) | 1994-07-27 | 1996-01-31 | Shimadzu Corporation | Elongation measurement using a laser non-contact extensometer |
| WO2002001641A1 (en) * | 2000-06-27 | 2002-01-03 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
| WO2002043157A1 (en) * | 2000-11-21 | 2002-05-30 | Matsushita Electric Industrial Co.,Ltd. | Semiconductor device and its manufacturing method |
| US6460418B1 (en) | 2000-01-19 | 2002-10-08 | Kishimoto Sangyo Co., Ltd. | Method of and apparatus for measuring elongation of a test specimen |
| WO2005018005A1 (en) * | 2003-06-26 | 2005-02-24 | Rj Mears, Llc | Semiconductor device including mosfet having band-engineered superlattice |
| WO2005018004A1 (en) * | 2003-06-26 | 2005-02-24 | Rj Mears, Llc | Method for making semiconductor device including band-engineered superlattice |
| WO2005034245A1 (en) * | 2003-06-26 | 2005-04-14 | Rj Mears, Llc | Semiconductor device including band-engineered superlattice |
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| US7700447B2 (en) | 2006-02-21 | 2010-04-20 | Mears Technologies, Inc. | Method for making a semiconductor device comprising a lattice matching layer |
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| JPS55117281A (en) * | 1979-03-05 | 1980-09-09 | Nippon Telegr & Teleph Corp <Ntt> | 3[5 group compound semiconductor hetero structure mosfet |
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|---|---|
| JPH0224025B2 (en) | 1990-05-28 |
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