JPS61241672A - IC test equipment - Google Patents

Abstract

PURPOSE:To make it possible to analyze trouble by comparing output value obtained by inputting a test pattern to an IC to be tested and the expected value of an output, and referring to fault simulation data when the output is discordant. CONSTITUTION:In an IC testing device 100, the output value sent out from the IC 6 to be tested through a test head 5 is compared with the expected value of the output sent out from a simulating device by a judging device 2. When the output value and expected value of the output are judged as discordant by the device 2, the output value of the IC 6 is fed back to a trouble analyzing device 10, and the place of the trouble is judged by referring to the fault simulation data, and the trouble is displayed. Then, an IC logical circuit of the place of the trouble is rewritten to conform with the output value from the IC 6, and logical simulation and the fault simulation are repeated. Thereby, test is executed to the last, and accordingly, it becomes possible to analyze troubles of plural places in a short period in IC test at the time of development.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC testing device belonging to a category called a real-chip test workstation.

[Conventional technology]

FIG. 4 is a schematic diagram of the configuration of a conventional IC testing device. In FIG. The expected output value of the designed IC obtained by the input test pattern during simulation or the input test pattern automatically generated after execution of the fault simulation is compared with the output value of the IC under test 6 obtained by the same human test pattern. 3 is a GO/NOGO display means for displaying the result of the judgment means 2; A pattern generator 4 converts the input test pattern sent from the simulation means 1 into an electrical signal. Reference numeral 5 denotes a test head that applies electrical signals sent from the pattern generator 4 to the IC under test 6 and
The output value is taken in and sent to the judgment means 2. Reference numeral 7 denotes a design support computer, which is composed of a simulation means 1, a judgment means 2, and a GO/NOGO display means 3. 8 is a test terminal device, and pattern generator 4
and a test head 5. The design support computer 7 and the test terminal device 8 constitute an IC testing device 200.

FIG. 5 is a diagram of an IC logic circuit 300 constituting the IC under test 6, which includes a two-man powered NOR gate 13°12 and a two-man powered NOR gate 13°12.
Consists of a gate 13, an inverter 14, '15,
■1 to 4 are input terminals (also represent input), 01,0
2 is an output terminal (also represents an output). For explanation, the output of NAND gate 11 is designated as NET+, and the output of NAND gate 12 is designated as NET2. The output of the NOR gate 13 is assumed to be NET3, but these are internal NETs in the IC chip.
Therefore, these electrical signals cannot be directly detected from the outside.

FIG. 6 is a timing chart showing the results of logic simulation in the IC logic circuit 300. The upper part of the solid line is the output "'l", the lower two parts of the solid line are the output "I Q I+, and the broken line is the undefined state II X 11, and Time indicates the elapsed time.

The IC testing apparatus 200 shown in FIG. 4 performs logic simulation on the IC logic circuit 300 shown in FIG. The input test pattern used at this time may be one created manually or one automatically created by a computer, but it is desirable that the input test pattern be programmed so that the entire IC 6 under test can be checked. Here, an input test pattern as shown in the timing chart of FIG. 6 is applied to input terminals I, I2. I 3.
The case where input is made to I4 will be explained. However, it is assumed that the delay time of each logic gate 11 to 15 is one unit of elapsed time for both rising and falling edges.

In the logic simulation, calculations are performed in the gate function according to each input state, and the outputs N E T+ , 'N E T2 , N'E are obtained as shown in Figure 6□.
FIG. 7 is a list of printer images showing the results of this logic simulation.

Although the logic simulation for the IC logic circuit 300 shown in FIG. 5 has been described above, an actual IC test will be explained below.

In FIG. 4, the input test pattern is sent one unit at a time from the simulation means 1 to the pattern generator 4.
will be sent to. The input test pattern of this logic simulation is converted into an electrical signal by the □ chisel turn generator 4, and is sent to the test device C6 via the test head 5.
is applied to

The IC under test 6 to which the input pulse of the first unit (T'i m'''e'=1') is applied operates according to this applied pulse, and the output signal from this IC under test 6 is sent to the test head 5. The output value is sent to the judgment means 2, but the test terminal device 8 performs static operation, time information from the simulation means 1 is taken in and time correction is performed, and the judgment means 2 determines whether the output value from the test head 5 and the output expected value sent from the simulation means 1 are temporally correct. A comparison reference is made so that it matches the test head 5.
If the output value from the simulator 1 matches the expected output value sent from the simulation means 1, it is assumed that there is no failure, and the input pulse of the second unit (Time=2) is sent from the simulation means 1. Then, if there is no mismatch until the end (that is, until T i m'e = 'l'8 in this example), the I'C6 to be tested is Go/N'
The IC 6 to be tested is displayed as a 'C food' by the O'00 table prefecture means 3 and is passed, but if a discrepancy is detected, the IC 6 to be tested is displayed as a defective product by the Go'/No co display means 3. be done.

[Problem that the invention seeks to solve]

The conventional IC testing apparatus as described above has a problem in that the test result is only a pass/fail result for the IC under test, and it is not possible to detect a failure location that causes a failure.

The present invention was made in order to solve such problems, and an object of the present invention is to provide an IC testing device that can also analyze the location of the failure when there is a failure in the IC under test.

[Means for solving problems]

The IC testing device according to the present invention includes a simulation means, a judgment means for comparing an output value obtained by inputting a test pattern to an IC under test and an expected output value, and outputting a signal indicating a match or a mismatch. A failure analysis means that determines the failure location by referring to the fault simulation data at that time when the outputs from the determination means do not match, and a failure display means that displays the failure analysis result by the failure analysis means. It is.

[Effect]

In this invention, when the outputs from the determining means do not match, the failure analysis means refers to the fault simulation data at this point in time to determine the location of the failure, and the failure display means displays the result.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the IC testing device of the present invention, in which the same reference numerals as in FIG. It shows. In this embodiment, the output of the determination means 2 is fed back to the failure analysis means 10.

FIG. 2 is a fault list showing fault simulation data for detecting a failure location when the timing chart of FIG. 6 and the input test pattern shown in the list of FIG. 7 are used.

The operation of the IC testing apparatus 100 of the present invention will be described below using the logic simulation outputs shown in FIGS. 6 and 7 and the fault simulation data shown in FIG. 2.

Also in the IC testing apparatus 100 of the present invention, the test object C
6, it is the same as the conventional IC testing apparatus 200 shown in FIG. It is. However, in the IC test pass device 100 of the present invention, at a certain point, for example, the sixth
When the output value and the expected output value are determined to be inconsistent by the determination means 2 at T i m e = 9 in FIG. 7 and FIG.

02=1) is fed back from the determination means 2 to the failure analysis means 10, and the failure location is determined by referring to the fault simulation data shown in FIG.

That is, referring to the fault simulation data, when Time = 9, the expected output value (0+ = 1.02
= 1), if the output value is (0+ = 0.02 = 1), it can be seen that NET2, which is the output of the NAND gate 12, is forced to the stuck-at fault 1, that is, the level "1pa". Therefore, If the IC6 under test has a single failure (a failure in which only a single net is at the ``0'' level or the ``11'' level), only one test cycle can detect the failed gate (also a gate output NET failure). analysis (that is, which gate is malfunctioning), which can be displayed on the failure display means 9.

However, this is only effective when there is a single fault; for example, if a fault is discovered at Time = 9, the analysis result that the output NET2 of the NAND gate 12 is at level "1" is displayed. The test has ended, and the following input test patterns reveal, for example, Time
It becomes unclear whether or not the NAND gate 11 has a failure at =12.

In the above explanation, since the IC logic circuit under test C6 is simple, there is no problem, but in actual IC testing, the number of gates ranges from several thousand gates to tens of thousands, and if the input test pattern is fast T i If a failure occurs in the IC, all it takes is a failure analysis of a few percent of the entire IC.
If the test is completed, other failures may still exist unless the failed part of the IC under test is corrected according to the failure analysis results, remanufactured using the corrected photomask, and tested again. Further advanced T
Failure analysis using IME is impossible. This has been a serious obstacle in shortening the IC development period.

Therefore, another embodiment will be described below in which the IC testing apparatus of the present invention can also analyze multiple failures.

In this embodiment, as in the previous embodiment, the judgment means 2 determines the output value (0+
=0.02=1) and the expected output value (O1=1.02=1) sent from the simulation means], the output value of the IC6 under test (0+=
0.02 = 1) is fed back to the failure analysis means 10, and the fault simulation data shown in FIG. 2 is referred to. Then, it is analyzed that NET2, which is the output of the NAND gate 12, is a short-sided fault l, and the fault display means 9 displays it.

Next, based on this failure analysis result, the simulation means 1 determines that the IC under test 6 is the IC logic circuit 30 shown in FIG.
0 as shown in the IC logic circuit 400 of FIG. 3, and the logic simulation and fault simulation after T i me=10 are performed again. Then, each time a failure is detected, the IC logic circuit is rewritten in the same way, and the logic simulation and fault simulation are performed until the end.

This logical simulation is executed again.
For example, when a failure is detected at Time = 9 and the IC logic circuit is newly rewritten, there is a method to perform simulation from Time = 1, and a time when the cause of the event of output 01 at Time = 9 is traced back. Time=8
There is a method of performing logic simulation from the beginning, and using the latter method can reduce the test time.

It goes without saying that if the test head means is capable of measuring DC parameters, the data can also be taken into the design support computer and displayed at the same time by the failure display means.

〔Effect of the invention〕

As explained above, when the output value of the IC under test does not match the expected output value when the IC under test is simulated, the fault location is determined and displayed by referring to the fault simulation data. Part I
The C logic circuit is rewritten to match the output value from the IC under test, and the logic simulation and fault simulation are executed again. By repeating this, the test is executed to the end, so the IC at the time of development
An advantage of this method is that it is possible to automatically analyze failures that occur in multiple locations in a single hour during a test.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram showing an embodiment of the IC testing device of the present invention, Fig. 2 is a fault list showing fault simulation data, Fig. 3 is a diagram showing an IC logic circuit, and Fig. 4 is a conventional IC test. A schematic diagram of the device, Fig. 5 is a diagram showing the IC logic circuit, Fig. 6 is a timing chart showing the results of logic simulation in the IC logic circuit, and Fig. 7 is a diagram showing the IC logic circuit.
This is a list showing the results of logic simulation in a logic circuit as a printer image. In the figure, 1 is a simulation means, 2 is a judgment means, 4 is a pattern generator, 5 is a test head, 6 is a test target IC 17 is a design support computer, 8 is a test terminal device, 9 is a failure display means, 1o is a failure analysis means , 10o is I
C test device. INPUT Time I+ 12 13 1431
1.00 OUTPLJT NETI NET2 NET30+ 02xxxx B 1111 1200'11 4ooooi 1ooi ioo+i

Claims (2)

[Claims] (1) A simulation means that performs simulations necessary for IC design, a pattern generator that converts an input test pattern sent from this simulation means into an electrical signal, and an electrical signal sent from this pattern generator that is applied to the IC under test. and the IC under test that is input via this test head.
determining means for comparing the output value of the output value with the expected output value sent from the simulation means and outputting a signal indicating whether the output matches or does not match, and referring to the fault simulation data at that time when the output from the determining means does not match. 1. An IC testing device comprising: a failure analysis means for determining a failure location by determining a failure location; and a failure display means for displaying a failure analysis result by the failure analysis means. (2) The simulation means rewrites the IC logic circuit used in the simulation to match the output value of the test head based on the failure analysis result output by the failure analysis means and continues the logic simulation. The IC according to claim (1)
Test equipment.