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JPS61220339A - Control of characteristics of semiconductor material - Google Patents

Control of characteristics of semiconductor material

Info

Publication number
JPS61220339A
JPS61220339A JP6169385A JP6169385A JPS61220339A JP S61220339 A JPS61220339 A JP S61220339A JP 6169385 A JP6169385 A JP 6169385A JP 6169385 A JP6169385 A JP 6169385A JP S61220339 A JPS61220339 A JP S61220339A
Authority
JP
Japan
Prior art keywords
donor
defect
substrate
oxygen
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6169385A
Other languages
Japanese (ja)
Other versions
JPH0511415B2 (en
Inventor
Yoichi Mada
間田 洋一
Kazumi Wada
一実 和田
Naohisa Inoue
直久 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP6169385A priority Critical patent/JPS61220339A/en
Publication of JPS61220339A publication Critical patent/JPS61220339A/en
Publication of JPH0511415B2 publication Critical patent/JPH0511415B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To control space distribution of specific resistivity and conductive types by introducing an energy level created by a defect into a substrate crystal by local heat treatment. CONSTITUTION:A semiconductor substrate 2 is partially heated by a local heating source 1 such as a laser beam to create a defect in the heated region and the energy level created by the defect is introduced into the substrate crys tal. The silicon substrate is locally melted by the laser beam to create an oxy gen donor. The oxygen donor is one of the defects which form a donor potential in a band gap of silicon. A change of a specific resistivity is created by the defect. The specific resistivity is in inverse proportion to the donor concentra tion. As the concentration increases linearly in accordance with the increase of the laser power and the change of the oxygen donor concentration against the laser power is monotonous, it is easily controlled.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体の比抵抗・伝導型を制御する半導体材料
特性の制御方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for controlling semiconductor material properties by controlling resistivity and conductivity type of a semiconductor.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

半導体の基本特性である比抵抗・伝導型は、バンドギャ
ップ内のエネルギ準位によシ決定される0通常は、ドナ
不純物(シリコンを例にとればV族元素)あるいはアク
セデタ不純物(同じく■族元素)の添加によシ発生する
エネルギ準位を利用して、比抵抗・伝導型の制御が行な
われる。LSIに代表される半導体素子では、比抵抗・
伝導型を空間的に、精密に、制御できることが必要であ
り、素子作製技術には上記の不純物を基板に精度よく、
局所的に添加できることが要求される。従来、基板に不
純物を局所的熱処理することによシエネルギ準位を導入
する方法として、拡散あるいはイオン打込が用いられて
いる。これらの方法は制御性は良いが、ウェハ全体を高
温で熱処理する工程を含むため材料特性の劣化が生じる
、局所的な不純物添加を行なうための表面被覆fQ5の
形成にホトリソを含む複雑な工程を要する、大掛シな装
置を必要とするため処理コストが高くなる等の欠点があ
る。
The resistivity and conductivity type, which are the basic properties of semiconductors, are determined by the energy level within the band gap.Normally, donor impurities (for example, in silicon, group V elements) or accelerator impurities (also group The specific resistance and conduction type are controlled by using the energy level generated by the addition of (elements). In semiconductor devices such as LSI, resistivity and
It is necessary to be able to spatially and precisely control the conduction type, and element fabrication technology involves precisely applying the above impurities to the substrate.
It is required that it can be added locally. Conventionally, diffusion or ion implantation has been used as a method for introducing a cyene energy level into a substrate by locally heat-treating impurities. Although these methods have good controllability, they include a step of heat-treating the entire wafer at high temperature, which causes deterioration of material properties, and a complicated process including photolithography to form the surface coating fQ5 for localized impurity addition. However, since this method requires large-scale equipment, it has drawbacks such as high processing costs.

上記の方法の欠点を除くため、エネルギ準位の導入にド
ナあるいはアクセグタ不純物金用いずに、シリコン中の
欠陥によるエネルギ準位を活用する次の二つの方法が提
案されている。これらの方法では、シリコン中の酸素は
単独ではエネルギ準位を形成しないが、450℃付近の
熱処理によシ複数個集合し結晶欠陥を形成するとドナ(
酸素ドナ)となる性質を利用している。
In order to eliminate the drawbacks of the above-mentioned methods, the following two methods have been proposed that utilize energy levels due to defects in silicon without using gold as a donor or acceptor impurity to introduce energy levels. In these methods, oxygen in silicon does not form an energy level by itself, but when multiple oxygen in silicon aggregates and forms crystal defects by heat treatment at around 450°C, it becomes a donor (
It takes advantage of the property of being an oxygen donor).

第一の方法は、p型側上げ結晶中の酸素濃度を成長条件
によシ周期的に変化させ、然る後に酸素ドナを発生させ
る熱処理を施し、酸素濃度の高い領域t−n型、低い領
域irp型に制御するものである。この方法では、酸素
濃度分布が結晶成長時の融体内での現象により支配され
るため。
The first method is to periodically change the oxygen concentration in the p-type side-raised crystal depending on the growth conditions, and then perform heat treatment to generate oxygen donors. This is a region IRP type control. In this method, the oxygen concentration distribution is dominated by phenomena within the melt during crystal growth.

酸素ドナ濃度の空間的分布の制御性が悪く、微細な半導
体素子の形成は出来ない。別の方法として、シリコン基
板へ酸素をイオン打込したのち熱処理を行ない、イオン
打込領域に酸素ドナを発生させる方法が提案されてbる
。この方法では酸素ドナ濃度の空間的分布の制御性は良
いが、大掛シなイオン打込装置を使用する点で従来の手
法と相違がなくまた酸素のイオン打込量を増加すると熱
処理により欠陥が発生するため、得られる最大ドナ濃度
は1015/cm”で低抵抗は得られない。
The controllability of the spatial distribution of oxygen donor concentration is poor, making it impossible to form fine semiconductor devices. Another proposed method is to implant oxygen ions into a silicon substrate and then perform heat treatment to generate oxygen donors in the ion implantation region. Although this method has good controllability over the spatial distribution of the oxygen donor concentration, it is no different from the conventional method in that it uses a large-scale ion implantation device, and when the amount of oxygen ion implantation is increased, defects may occur due to heat treatment. occurs, so the maximum donor concentration that can be obtained is 1015/cm'' and low resistance cannot be obtained.

〔発明の目的〕[Purpose of the invention]

本発明は上記の事情に鑑みてなされたもので、所謂ドナ
やアクセデタ不純物を用いることなく半導体の比抵抗・
伝導型を局所的に制御できる半導体材料特性の制御方法
を提供することを目的とする。
The present invention has been made in view of the above circumstances, and it is possible to improve the resistivity and specific resistance of semiconductors without using so-called donor or accelerator impurities.
The purpose of the present invention is to provide a method for controlling semiconductor material properties that can locally control conductivity type.

〔発明の実施例〕[Embodiments of the invention]

本発明では、正規の格子位置Kl>ってはエネルギ準位
を形成しないかあるいは形成しK〈いが欠陥位置でエネ
ルギ準位を形成する不純物、もしくは単独ではエネルギ
準位を形成しないかあるいは形成しにくいが複合化し欠
陥となることによって初めてエネルギ準位を形成する不
純物や点欠陥を、エネルギ準位の導入に利用する。
In the present invention, the normal lattice position Kl> does not form an energy level or does form an energy level K<or does an impurity form an energy level at a defect position, or does not form an energy level by itself or does it form an energy level. Impurities and point defects, which are difficult to form but only form energy levels when they become complex and become defects, are used to introduce energy levels.

すなわち、欠陥位置を占める不純物、または不純物、点
欠陥の複合した欠陥(以下では両者を合わせて単に欠陥
と呼ぶ)に起因するエネルギ準位を、局所的な熱処理(
融解を伴なう場合を含む)で基板結晶に導入することK
よシ、その比抵抗・伝導型の空間的分布を制御する。
In other words, the energy level caused by impurities occupying defect positions, or defects that are a combination of impurities and point defects (hereinafter referred to simply as defects), is reduced by local heat treatment (
(including cases involving melting) into the substrate crystal.
Therefore, the spatial distribution of resistivity and conduction type can be controlled.

第1図は本発明による局所加熱源を用いた半導体基板へ
のエネルギ準位の導入を示す図である。レーデ光等の局
所加熱源1で半導体基板2を部分的に加熱することKよ
シ、加熱領域に欠陥を発生させ、そのエネルギ準位を導
入する。
FIG. 1 is a diagram illustrating the introduction of energy levels into a semiconductor substrate using a local heating source according to the present invention. By partially heating the semiconductor substrate 2 with a local heating source 1 such as Raded light, a defect is generated in the heated region and its energy level is introduced.

以下、実施例に基づいて本発明を説明する。Hereinafter, the present invention will be explained based on Examples.

第2図はレーデ光でシリコン基板を局所的に融解させる
ことによシ、シリコンのバンドギャップ中にドナ準位を
形成する欠陥の一つである酸素ドナを発生させ、これに
よる比抵抗の変化を広が)抵抗法で測定した例である。
Figure 2 shows that by locally melting the silicon substrate with Rade light, oxygen donors, which are one of the defects that form donor levels in the band gap of silicon, are generated, and the resistivity changes due to this. This is an example of measurement using the resistance method.

基板は比抵抗0.830・個のn型Czウェハである。The substrate is an n-type Cz wafer with a specific resistance of 0.830.

レーザ光源は波長0.53μmのNd:YAGレーデ逓
倍光で、照射条件は・母ルス周波数4 kHz m走査
速度10 vm/ S 、  レーザ・−ワー0.3W
である0図よ)レーデ光照射領域3では、比抵抗が0.
090・αに減少している。比抵抗とドナ濃度とは反比
例関係にあるため、レーデ光照射によシドナ濃度が増加
しているのがわかる。レーデ光照射にょ)発生したドナ
が酸素ドナであることは、ドナが650℃の短時間熱処
理によシ消滅し450℃の長時間熱処理によシ発生する
という酸素ドナ固有の熱的挙動を示すことから容易に確
認できる。
The laser light source is Nd:YAG radar multiplied light with a wavelength of 0.53 μm, and the irradiation conditions are: base frequency: 4 kHz, scanning speed: 10 vm/S, laser power: 0.3 W.
(Fig. 0)) In the Raded light irradiation area 3, the specific resistance is 0.
It has decreased to 090·α. Since resistivity and Donna concentration are in an inversely proportional relationship, it can be seen that Cydona concentration increases due to Raded light irradiation. The fact that the generated donor is an oxygen donor indicates the unique thermal behavior of oxygen donors, in which the donor disappears after short-time heat treatment at 650°C and is generated after long-time heat treatment at 450°C. This can be easily confirmed.

第3図は、上記の照射条件でレーザ・やワーを変えた場
合の酸素ドナ濃度とレーデパーワーとの関係である。図
よ)、酸素ドナはシリコンが融解しはじめるo、 i 
J W付近から発生し、レーデパワーの増加につれて濃
度が直線的に増加する。
FIG. 3 shows the relationship between the oxygen donor concentration and the laser power when the laser power and power are changed under the above irradiation conditions. ), oxygen donor silicon begins to melt o, i
It occurs near JW, and its concentration increases linearly as the lede power increases.

このように酸素ドナ濃度のレーデ14ワーにたいする変
化は単調であるため、その制御は容易である。レーデパ
ワー〇、 30 Wでは酸素ドナ濃度/I′i1.15
 X 10 10n”で、先述した酸素のイオン打込に
よシえられるドナ濃度の最大値1.OX 10 ”7c
m”よシも2桁以上高く、本発明によれば低抵抗領域を
形成することができる。以上はn型シリコン基板を用い
た場合であるが、p型シリコン基板でも、また表面に窒
化シリコン膜、酸化シリコン膜等の薄膜が有る場合でも
同様のことができることが確かめられている。レーデ光
の波長を変えてもまた電子ビーム加熱の場合にも同様の
効果が得られる。
As described above, since the oxygen donor concentration changes monotonically with respect to radar power, it is easy to control it. At Rede power〇, 30 W, oxygen donor concentration/I'i1.15
X 10 10n", the maximum donor concentration obtained by the oxygen ion implantation described above is 1.OX 10"7c
m'' is also higher by more than two orders of magnitude, and a low resistance region can be formed according to the present invention.The above is a case where an n-type silicon substrate is used, but a p-type silicon substrate can also be used with silicon nitride on the surface. It has been confirmed that the same effect can be achieved even when there is a thin film such as a silicon oxide film or a silicon oxide film.A similar effect can be obtained by changing the wavelength of the Raded light or by electron beam heating.

上記実施例は欠陥がシリコン中の酸素ドナの場合である
が、冒頭に述べたようにシリコン中のその他の例えばア
クセプタ等の欠陥でもまた他の半導体材料の欠陥であっ
ても、バンドギャップ中にエネルギ準位を形成する欠陥
であれば、当然釆手法が有効なことは言うまでもない、
また実施例は融解を伴なう局所的熱処理の場合であるが
、融解を伴なわない場合でも本方法を同様に適用しうる
In the above example, the defect is an oxygen donor in silicon, but as mentioned at the beginning, other defects in silicon, such as acceptors, or defects in other semiconductor materials can also occur in the band gap. It goes without saying that the pottery method is effective for defects that form energy levels.
Further, although the embodiment deals with a case of local heat treatment accompanied by melting, the present method can be similarly applied to cases where melting is not involved.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、半導体基板に局所的
熱処理を行なうだけで、欠陥のエネルギ準位に起因する
ドナあるいはアクセプタ濃度の空間的分布を制御できる
ため、ドナやアクセデタ不純物の添加は不要であり、ま
た添加のために基板を高温に保持することがないので基
板特性の劣化が起こら彦い等大きな利点が生じる。さら
に、本発明によル得られる酸素ドナの最大濃度は、冒頭
にて述べた酸素のイオン打込によ)得られる最大濃度よ
シも二桁以上高く、本発明では欠陥によるドナあるいは
アクセプタの濃度の制御範囲を広くできるという特徴が
ある0本発明によれば、オーミック接触のための低抵抗
層あるいは素子分離のための高抵抗層のほかpn接合の
形成も可能である。
As described above, according to the present invention, the spatial distribution of the donor or acceptor concentration caused by the energy level of defects can be controlled by simply performing local heat treatment on the semiconductor substrate. This is unnecessary, and since the substrate is not held at a high temperature for addition, there are great advantages such as no deterioration of the substrate properties. Furthermore, the maximum concentration of oxygen donors obtained by the present invention is more than two orders of magnitude higher than the maximum concentration obtained by the oxygen ion implantation described at the beginning. According to the present invention, which has the characteristic of widening the concentration control range, it is possible to form a pn junction as well as a low resistance layer for ohmic contact or a high resistance layer for element isolation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による局所加熱源を用いた半導体基板へ
のエネルギ準位の導入を説明するための構成図、第2図
は本発明の実施例によるレーザ光照射で発生した酸素ド
ナによる比抵抗変化の広がシ抵抗法による測足例を示す
図、第3図は本発明の実施例による酸素ドナ濃度のレー
デパワー依存性を示す図である。 1・・・局所加熱源、2・・・半導体基板、3・・・レ
ーデ光照射領域。 出願人代理人  弁理士 鈴 江 武 彦第2図
FIG. 1 is a block diagram for explaining the introduction of energy levels into a semiconductor substrate using a local heating source according to the present invention, and FIG. 2 is a diagram showing the ratio due to oxygen donors generated by laser beam irradiation according to an embodiment of the present invention. FIG. 3 is a diagram illustrating an example of foot measurement using the resistance method in which the spread of resistance change is measured, and FIG. DESCRIPTION OF SYMBOLS 1...Local heat source, 2...Semiconductor substrate, 3...Raed light irradiation area. Applicant's agent Patent attorney Takehiko Suzue Figure 2

Claims (3)

【特許請求の範囲】[Claims] (1)半導体のバンドギャップ中にエネルギ準位を形成
する欠陥を、半導体基板の局所的熱処理で発生させ、そ
の欠陥のエネルギ準位に対応するドナあるいはアクセプ
タの濃度の空間的分布を制御することを特徴とする半導
体材料特性の制御方法。
(1) Generating defects that form energy levels in the band gap of the semiconductor by local heat treatment of the semiconductor substrate, and controlling the spatial distribution of donor or acceptor concentrations corresponding to the energy levels of the defects. A method for controlling semiconductor material properties characterized by:
(2)局所的熱処理を半導体基板の融解の起る条件で行
なう特許請求の範囲第1項記載の半導体材料特性の制御
方法。
(2) A method for controlling semiconductor material properties according to claim 1, wherein the local heat treatment is performed under conditions that cause melting of the semiconductor substrate.
(3)欠陥がシリコン結晶中の酸素ドナであり、かつ局
所的熱処理をレーザ光により行なう特許請求の範囲第2
項記載の半導体材料特性の制御方法。
(3) Claim 2 in which the defect is an oxygen donor in a silicon crystal, and the local heat treatment is performed using a laser beam.
Method for controlling semiconductor material properties as described in .
JP6169385A 1985-03-26 1985-03-26 Control of characteristics of semiconductor material Granted JPS61220339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6169385A JPS61220339A (en) 1985-03-26 1985-03-26 Control of characteristics of semiconductor material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6169385A JPS61220339A (en) 1985-03-26 1985-03-26 Control of characteristics of semiconductor material

Publications (2)

Publication Number Publication Date
JPS61220339A true JPS61220339A (en) 1986-09-30
JPH0511415B2 JPH0511415B2 (en) 1993-02-15

Family

ID=13178584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6169385A Granted JPS61220339A (en) 1985-03-26 1985-03-26 Control of characteristics of semiconductor material

Country Status (1)

Country Link
JP (1) JPS61220339A (en)

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US6830964B1 (en) 2003-06-26 2004-12-14 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US6833294B1 (en) 2003-06-26 2004-12-21 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US6993222B2 (en) 1999-03-03 2006-01-31 Rj Mears, Llc Optical filter device with aperiodically arranged grating elements
US7018900B2 (en) 2003-06-26 2006-03-28 Rj Mears, Llc Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regions
US7045377B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7045813B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US7123792B1 (en) 1999-03-05 2006-10-17 Rj Mears, Llc Configurable aperiodic grating device
US7202494B2 (en) 2003-06-26 2007-04-10 Rj Mears, Llc FINFET including a superlattice
US7227174B2 (en) 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7229902B2 (en) 2003-06-26 2007-06-12 Rj Mears, Llc Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US7396742B2 (en) 2000-09-13 2008-07-08 Hamamatsu Photonics K.K. Laser processing method for cutting a wafer-like object by using a laser to form modified regions within the object
US7446002B2 (en) 2003-06-26 2008-11-04 Mears Technologies, Inc. Method for making a semiconductor device comprising a superlattice dielectric interface layer
US7491587B2 (en) 2003-06-26 2009-02-17 Mears Technologies, Inc. Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
US7514328B2 (en) 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US7517702B2 (en) 2005-12-22 2009-04-14 Mears Technologies, Inc. Method for making an electronic device including a poled superlattice having a net electrical dipole moment
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