JPS61206254A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To avoid a malfunction due to a crosstalk by a simple means by disposing a power supply line supplying each cell with electricity between bit lines in adjacent column along bit lines. CONSTITUTION:A power supply line VDD is divided into two, and positioned outside bit lines B, -B. Consequently, the power supply lines VDD are positioned between the bit lines -B and B in each column between adjacent columns C1, C2. These bit lines -B, B are shielded electrostatically by the power supply lines VDD, and a crosstalk between the bit lines is reduced. A simple means such as the change of the arrangement of the power supply lines may be used as a means required in order to position the power supply lines outside the bit lines, and said method has an advantage that the trouble concerning the device is not generated by said means.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a static memory device in which a memory cell having a flip-flop structure is arranged at each intersection of a large number of word lines and bit line pairs. Regarding.

[Conventional technology]

A memory cell of a static memory generally has a flip-flop structure, and its pair of input and output terminals are connected to a pair of pin I lines via a transfer gate, and the transfer gate is opened and closed by a word line. Become. The flip-flops and transfer gates are composed of bipolar transistors or MOS transistors, but in semiconductor devices using gallium arsenide (GaAs) for the semiconductor substrate, MOS (Metal Oxide SEM) is used.
Since it is difficult to make a 1-conductor type FET (field effect transistor), junction type or Schottky barrier type MES (metal semi-cond
uctor) type FET is used.

Furthermore, there are two types of mating types: PN junction type and heterozygous type, and some of the latter are HEMT (High Electron M
abilityTransistor) and have different operating principles, but here they are simply referred to as MES FE
It's called T.

SRAM (Statistical) using MES FET
cRa-mdom Access Memory
) has the configuration shown in FIG.

Q1 to Q4 are MESFETs that constitute a flip-flop.
, C5, Qs are MES forming the transfer gate.
These six transistors constitute one memory cell MC. B and B are a pair of bit lines that control input and output of memory cell data. W is the word line,
Transfer gate transistors Qs and Qa are opened and closed. A memory has a large number of such bit line pairs and word lines, and a memory cell MC is connected to each of their intersections. The word line W is set to H by a word driver (not shown).
level, transistor Q5. Q6 turns on. Therefore, in memory cell MC, transistor Q1 is on,
When C2 is turned off, the potential of bit line B, which is pulled up by a circuit not shown, flows through gate Q5 and transistor Q+, so the potential decreases, and the current passing through C6 and C2 is Since there is no potential, the potential does not drop, and thus a potential difference is created between B and 100, and the cell storage data is read.

In this way, SRAM using MES FET also has MO
It operates similarly to an SRAM using S FETs.

Of course, there are some differences between MEs FE and T because the gate is a diode and is not insulating like a MOS FET, and the semiconductor substrate used is insulating.

Figure 6 (al~(C1) shows various examples of planar patterns of memory cells. In (a), a ground line GND runs vertically in the center of the cell, and on both sides of the ground line GND there are bit line pairs B, B. A power supply line VDD and a word line W run perpendicularly to the line, and the transistor QI-Qa is configured as shown in the figure. B, B, word line W and power supply line VDD run orthogonally to these, but (a
), the upper and lower relationships between word lines and power lines are reversed. Transistors Q1-Q6 are constructed as shown. (
In C1, a ground line GND runs horizontally through the cell, a power supply line VDD and a word line W are on both sides thereof, and a bit line pair B runs on both sides of the cell orthogonally to these. Transistors Q1-Q6 are constructed as shown.

The fact that word lines and bit lines are orthogonal is essential since memory has a matrix configuration, and the sixth
(al to (C1) in the figure are all like that. It is not essential whether the power line VDD and ground line GND are run vertically or horizontally, but (al, (b)
), the ground line runs vertically, and (C), the ground line runs horizontally. However, in all of (a) to (C1), the power supply line VDD runs in the horizontal direction (word line direction).

[Problem that the invention seeks to solve]

By the way, in a memory, there are a large number of word lines W and bit line pairs B, B, and the bit lines are on both sides of the cell, so in adjacent columns, each bit line faces each other with a small gap, reducing the electrostatic capacitance between them. I will have it. In a normal bipolar or MOS memory that uses silicon as the semiconductor substrate, the wiring capacitance is mainly formed between the silicon substrate and the capacitance between the wirings is not much of a problem, but in an FET type memory that uses GaAs as the semiconductor substrate, Since the substrate is insulative, there is almost no capacitance with the substrate, and instead the capacitance between the wirings occupies a large proportion.

If the bit lines in adjacent columns have a large capacitance between each other, when the potential of one bit line pair changes during reading or writing, that potential change may change the potential of the other bit line pair, resulting in malfunction. be. The present invention attempts to avoid malfunctions due to crosstalk by simple means.

[Means for solving problems]

In the present invention, a memory cell having a flip-flop structure is arranged at each intersection of a large number of word lines and a large number of pairs of bit lines perpendicular to these, and a pair of input and output terminals of the flip-flop are connected via a transfer gate transistor. A semiconductor memory device in which cells are connected to bit lines on both sides is characterized in that a power supply line for supplying power to each cell is arranged along the bit lines and between bit lines of adjacent columns.

[Function and Examples]

As shown in FIG. 1, in the present invention, the power supply line VDD is divided into two parts and placed outside the bit lines B and B. In this way, between adjacent columns (cell arrays in the bit line direction) CI and C2, there will be a power line VDD between the bit lines B and B of each column, and these bit lines B and B will be connected to the power line VDD. Electrostatic shielding is provided by the wires, and crosstalk between the Bi and Node wires is reduced. To give a numerical example, if the width of the bit lines is 2 μm, the distance between the bit lines is 4 μm, and the substrate is made of GaAs, the capacitance between the bit lines is 0.07 pF/mm. When placed and shielded, the capacity is 0.
01 pF/fl.

Figure 2 (al and (bl are lines A-A' and B-B in Figure 1)
FIG. In this memory cell as well, a ground line GND runs vertically (in the bit line direction) at the center of the cell, and transistors (MES FET) Q are placed on both sides of the ground line GND.
1, C2 are formed, and transistors (MEI FETs) C3 and C5, Ql and G6 are formed using the drain regions D+ and D2 of these 1 transistors as source regions, and these transistors Q3 . The drain region of Q4 is connected to the outermost power supply line VDD, VDD, and the drain region of transistor Qa, Q6 is connected to the inner bit line B, B.
connected to. CW indicates contact window, Gl, G2
indicates the gate electrode wiring of transistors Ql and Q2. Since the substrate used is gallium arsenide (GaAs), silicon is used as an impurity and ions are implanted to form diffusion regions (source, drain, and channel regions).AuGe is used as the electrode material that makes ohmic contact with the diffusion region. WSi is used for the gate electrode, and TiAu is used for the upper wiring material.

The power supply lines VDD between the columns may be integrated into one line instead of arranging two lines in parallel as shown in the figure. Also, the outer power line VDD for the outermost column of the cell array (if 01 in the figure is the leftmost column, the leftmost power supply line VDD is omitted because there is no opposite bit line to be electrostatically shielded, and the right side Power may be supplied from the power line VDD. Figure 4 shows an example in which the power line is shared by the columns on both sides,
Di-1 is a power line provided between the i-1th column and the i-th column, and VDDI is a power line provided between the i-th column and the i+l-th column. The same applies to other power supply lines. FIG. 3 shows the memory cell MCi shown in FIG.
b) A corresponding cross-sectional view.

Memory cell driver transistors Ql, Q2 and transfer gate transistor Q5. C5 is an enhancement (E) type, and load transistors Ql and Q4 are depletion (D) types. Now, if transistor Q1 of memory cell MCi is on and C2 is off, the current is
Flows through the path of DDi-1, Q 3 +Q, and GND, and also "pDI+ Q a.

The currents flowing through the paths Ql and GND are so equal that they flow through these paths. Transistor Q1 is off, C2
When is on, the path of VDDI + C4, C21GND and VDD, -1, Q 3, Q 2, G
Currents flow through the paths of ND, and these currents are also equal.

The same thing can be said about all the cells in the column, so all the cells in the column have power supply lines VDDi-1°VD on both sides of the column.
The currents drawn from DI are equal, so the currents in these power lines are balanced. On the other hand, in MOS memory, if Q+ is on and C2 is off, the current is VDDl-1, Q
3, Q + , flows only to the GND path, V
There is no current in the paths of DDI, Q a, and Q I (
Ql is an insulated gate) If C2 is on and Q1 is off, then VDDI, Q 4 , Q 2 , Cr N D
VDDI-1, C3, C2, GND with only the current in the path
There is no current. For this reason, in a MOS memory, when power lines are run on both sides of a column in the column direction, a current flows in the power line in a biased manner depending on the data stored in the column content cells. There is no problem with memory using MES FETs, and the line width can be determined assuming that 1/2 of the cell current flows through the left and right power supply lines.

〔Effect of the invention〕

As described above, the present invention is extremely effective in reducing crosstalk due to capacitance between bit lines of adjacent columns and preventing malfunctions. Further, the means necessary for this purpose may be as simple as changing the arrangement of the power supply lines, and there is an advantage that there is no problem caused by this.

[Brief explanation of drawings]

1 is a plan view showing an embodiment of the present invention, FIG. 2 is a sectional view taken along lines AA' and BB' in FIG. 1, and FIG. 3 is a sectional view of the memory cell shown in FIG. 4. FIG. 4 is a circuit diagram showing another embodiment of the present invention, FIG. 5 is a circuit diagram of a memory cell using MESFET, and FIG. 6 is a plan view of FIG. 5. In the drawing, W is a word line, B and B are bit line pairs, MC is a memory cell, Q1 to Q4 are transistors forming a flip-flop, Ql and C2 are load transistors, C5 and C
6 is a transfer gate transistor, CI and C2 are columns, and VDD is a power supply line.

Claims (3)

[Claims] (1) A memory cell with a flip-flop structure is arranged at each intersection of a large number of word lines and a large number of bit line pairs perpendicular to these, and a pair of input and output terminals of the flip-flop are connected to the cell through a transfer gate transistor. 1. A semiconductor memory device connected to bit lines on both sides, characterized in that a power supply line for supplying power to each cell is arranged along the bit lines and between the bit lines of adjacent columns. (2) The semiconductor memory device according to claim 1, wherein the transistors constituting the flip-flop and the transfer gate are MESFETs. (3) One load transistor of the flip-flop is connected to a power line on one side of the column, and the other load transistor is connected to a power line on the other side of the column. Or the semiconductor memory device according to item 2.