JPS61177551A - Start-up control system of processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a processing device for an electronic computer.
This invention relates to a start-up control method when performing automatic self-diagnosis (when running from a certain address).

[Background of the invention]

Conventionally, in order to guarantee the reliability of electronic computer systems, an automatic self-diagnosis function has often been added to the processing device F11φ.

For example, ICRO5Y was published in July 1980.
STE! 4S/July 1980 pages 90 to 94, “ASelf-diagnosing min
On icomputerJ, when a hardware reset is applied, the hard core section (including 32 bytes of R
Singleboard compute with AM
r) is stated to be checked.

However, improvements in processor speed have lagged behind the increase in memory capacity due to advances in semiconductor technology.
As a result, there is a problem that automatic self-diagnosis takes a long time at startup (when loading a program into main memory and running it from a certain address when the power is turned on, etc.).For example, when checking the main memory, , 2 MI
It takes several seconds for a PS-sized processor to check a memory of 8 MB (access width: 8 bytes), but when the memory is expanded to 32 MB, it takes about 20 seconds. If the system start-up frequency is about 71 days at a time, 20 seconds or so is not a problem, but when debugging the system, it is necessary to start up the system many times, which becomes a problem.

There is also a method in which the main memory is checked only when necessary by an operator's command. This method is convenient because unnecessary memory check operations are omitted during debugging, but in order to guarantee the reliability of the system, the operator must activate memory checks every time during normal operations other than debugging. It's a hassle.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a startup control method for a processing device that performs automatic self-diagnosis at startup, which reduces startup time and eliminates the need for troublesome operations by an operator to ensure reliability.

[Summary of the invention]

The present invention has means for storing whether the processing device is in a debug state or in a normal state, and means for changing the stored contents, and when the stored contents indicate a debug state, an automatic diagnosis is performed. It is characterized in that it performs some or not all of the automatic diagnosis, and in normal times, it performs all of the automatic diagnosis.

[Embodiments of the invention]

The following is a detailed explanation of the present invention: 0 Examples of the invention: 2
The first embodiment uses a mechanical switch as a means for storing two states, and the second embodiment uses a semiconductor memory.
An example will be described.

FIG. 3 shows an example of the overall configuration of a processing device system, which is the background of the present invention, and shows a processing bag! 1 includes a display device 2 for the operator, such as a character display.

An input device 3 from an operator such as a keyboard is connected. The processing device 1 also has an auxiliary storage device 4 and an operator panel 5. The operator panel 5 has a reset switch 6 (push button type) and an auto switch 7 (on,
(off selection method) is provided.

FIG. 4 shows the internal configuration of the processor 1.
1 reads and executes a program in the ROM 12 or main memory 13 via the system bus 14. Furthermore, the processor 11 can read the contents of a power-on flag 18 and auto switch 7, which will be described later, via the same bus 14 and gate 15. The processor 11 also uses the same bus 14.
and console input/output device attachment 16. The processor 11 communicates with the display device 2 for the operator and the input device 3 from the operator via the interface cable 8, and the processor 11 communicates with the auxiliary storage connection mechanism 1 via the same bus 14.
7 can be activated.

The mechanism 17 that has been activated stores the auxiliary storage device 4 and the main memory 1.
The output of the reset switch 6, which transfers data between When the switch is turned off, it starts from a specific address (for example, address 0). The address corresponds to an address in the ROM 12, and the processor 11 sequentially reads programs from the ROM 12 and executes them. The program started by this reset is hereinafter referred to as a reset program. Further, the output of the reset switch 6 is also input to a power-on flag 18 (a flag indicating that the reset program has been started due to power restoration), and when the reset switch 6 is turned on, the flag becomes "0". The power restoration control unit 19 outputs a pulse for a certain period of time when power is restored to the processing device. This output is input to the processor 11, which performs a hardware reset and starts the reset program in the same way as when the reset switch 6 is turned on.The same output is also input to the power-on flag 18, so that the power is turned on when the power is restored. On flag 1
Make 8 1゛1.

FIG. 5 shows the detailed configuration of the power-on flag 18 and the power recovery control unit 19. At the time of power recovery, while the capacitor 21 is being charged through the resistor 22, the output of the power recovery control unit 19 becomes 1 and the power-on flag 18 is “ In contrast, when the reset switch 6 is turned on, the power-on flag 18 is turned on.

FIG. 1 shows a flowchart of a reset program according to a first embodiment of the present invention. When a reset switch of a processing device is pressed, the hardware in the processing device is reset and then linked to the reset program. This program first determines the power-on flag 18, and if the flag is 1', clears all areas of the main memory to O and releases the parity state, then performs a self-diagnosis around the processor and checks the main memory, and then checks the processing unit. When the auto switch 7 is set to the OFF state, it enters the WAIT state (stops processing and waits for operator input), and when the auto switch 7 is set to the ON state, it enters the IPL (loads the program from the auxiliary storage device). and start.

On the other hand, when the power-on flag is “M”, self-diagnosis is performed around the processor, and when the auto switch of the processing unit is set to “O”, which means debugging, it is WAIT.
state, and when it is set to "1" which means normal time, the main memory is checked and started.

FIG. 6 shows a flowchart of a program in the WAIT state according to the first embodiment of the present invention. This program is also a program stored in the ROM 12 like the reset program. The program waits until input data from the operator is sent to the console input/output connection mechanism 16. When the input data is sent, it judges the data, and if it means IPL, performs IPL and starts. If the same data means start, start.

In normal use, the operator sets the auto switch 7 to "1", and when the reset switch 6 is turned on for startup, the main memory check is performed as shown in the flowchart in Figure 1, and the system starts. do. On the other hand, during debugging, the auto switch 7 is set to "0".

When the reset switch 6 is turned on for startup, an 8-doware reset is performed and self-diagnosis of the processor periphery is performed, but the main memory is not checked and the processing device immediately enters the IIAIT state. After entering the WAIT state, the operator can immediately start the processing device by inputting data specifying start from the input device 3.

FIG. 2 shows a flowchart of the reset program according to the second embodiment of the present invention. When the reset button of the processing device is pressed, the hardware in the processing device is reset and then linked to the reset program. This program first determines the power-on flag 18, and the flag is “1”.
When this flag is set to 0, all areas of the main memory 13 are cleared to 0, and when the flag is "On, the main memory is not cleared to zero. 1st: Processor peripheral self-diagnosis is performed. 6: Checking of specific addresses on the main memory is prohibited. Determine the flag and the flag is “0”
When the flag is 1", the main memory is checked, and when the flag is 1", the main memory is not checked.0 When the auto switch 7 is set to the OFF state, the WAIT state is entered, and when the switch is set to the ON state and When the power-on flag 18 is 1, IPL is performed and started, and when the switch is on and the power-on flag 18 is "0", IPL is performed and starts immediately.

FIG. 6 shows a flowchart of a program in the IIAIT state according to the second embodiment of the present invention. The program waits until input data from the operator is sent to the console input/output connection mechanism 16.

When input data is sent, it is judged and I
If it means PL, perform IPL and state. If the same data means start, start. Also,
If you mean setting the check prohibition flag, set the check prohibition flag at a specific address on the main memory to "1n," and set the WA
Return to the top of the IT time program. If it means clearing the check prohibition flag, the check prohibition flag at a specific address on the main memory 13 is set to "0" and the program returns to the beginning at wAIT.

In normal use, as shown in Figure 2, when the power is turned on, the power-on flag is 1'', so all areas of the main memory are cleared, and the check prohibition flag is also set to 0. ”, when the operator turns on the reset switch 6 for startup, a main memory check is performed as shown in the flowchart in the same figure.On the other hand, during debugging, the reset switch 6 is turned on with the auto switch 7 turned off. The operator turns on and puts the processing device in the %1AIT state.Then, the operator inputs data specifying the recheck prohibition flag set from the input device 3, sets the check prohibition flag in the main memory to 1'1'', and temporarily sets this flag. After setting "1" to "1", when you want to restart, turn on the reset switch 6 to perform a hardware reset and processor peripheral self-diagnosis, but the processing unit immediately enters WAIT without checking the main memory. state.

After entering the WAIT state, the operator can immediately start the processing device by inputting data specifying restart through the input device 3.

〔Effect of the invention〕

According to the present invention, the restart time during debugging is shortened,
Moreover, troublesome operations by an operator for guaranteeing reliability are not required. Reduction of restart time during debugging: 1. For example, what used to take about 20 seconds can be reduced to 2 to 3 seconds.

[Brief explanation of drawings]

FIG. 1 is a flowchart of the first embodiment of the present invention;
The figure is a flowchart of the second embodiment of the present invention, FIG. 3 is a diagram showing an example of the overall configuration of a processing device system that is the background of the present invention, FIG. 4 is an internal configuration diagram of the processing device, and FIG. 5 is a power supply system. Detailed configuration diagram of the on-flag and power recovery control unit, Figure 6 is the first
Flowchart in the WAIT state of the embodiment, No. 7
The figure is a flowchart in the WAIT state of the second embodiment. DESCRIPTION OF SYMBOLS 1... Processing device, 2... Display device, 3... Input device, 4... Auxiliary storage device, 5... Operator panel, 6... Reset switch, 7... Auto switch, 11... Processor, 13... Main memory, 18.
...Power onf/'? t/N Myo2n y4H It/N Kuzu, U It/N

Claims (1)

[Scope of Claims] 1. A processing device including means for issuing an automatic self-diagnosis command and means for performing automatic self-diagnosis of a predetermined item within the processing device in response to the command, which can take two states. comprising a storage means and a means for changing the state of the storage means, and when the storage means receives the above instruction when the storage means is in the first state, performs some or not all of the predetermined items of the diagnosis. ,
A start-up control method for a processing device, characterized in that when the storage means receives the command while the storage means is in the second state, all of the predetermined items of the diagnosis are performed. 2. A start-up control system for a processing device according to claim 1, wherein the means for issuing a diagnosis command is a reset switch operable by an operator. 3. In claim 1, the means for issuing a diagnosis command is a reset switch that can be operated by an operator and a circuit that automatically notifies the processing device that the power has been restored immediately after the power is restored. Equipment start-up control method. 4. A start-up control system for a processing device according to claim 1, wherein the storage means is a mechanical switch. 5. A start-up control system for a processing device according to claim 1, wherein the storage means is a semiconductor memory. 6. In claim 1, the storage means is set to either the first or second state by a command from the operator, and is set to the second state on the condition that it is in the state immediately after power restoration. A start-up control method for processing equipment.