JPS6068635A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable to reduce the area of a contacting electrode by covering a contacting hole with the first layer electrode. CONSTITUTION:A contacting hole 6 is opened by a photoetching method using a resist 3 at an insulating film 2 formed on an Si substrate 1, and a contacting aluminum-2% Si electrode 4 of the first layer is formed by vacuum deposition. Then, the photoresist 3 is removed, thereby removing the electrode 4 thereon, a wiring film 5 of the second layer is formed, and a wiring pattern is etched with a photoresist 3'. In the electrode thus formed, the contact is covered with the electrode 4. Accordingly, even if the mask alignment of the wiring 5 is displaced by a width (alpha), no problem occurs, and it is not particularly necessary to increase the size of the contact.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having an electrode with a reduced area of a contact electrode on the surface of a semiconductor element, or with an electrode that prevents disconnection or reduction in current capacity at the contact portion.

In conventional semiconductor devices, holes are formed in the insulating film on the St substrate by photoetching, the photoresist is removed, and then a thin film for wiring such as A-6-8i is formed by vacuum evaporation or sputtering. The wiring was formed by photo-etching.

Another prior art is Pt5i-Ti-Pt-Au.
This is the electrode structure. In this case, the contact electrode part is made of Pt.
S1-Ti-Pt-Au and the wiring part is Ti-Pt-
It is Au. The method for making this electrode is as follows. After forming a contact hole, PT is formed on the entire surface, heat treated to form PtSi only on the contact portion, and then Pt on the insulating film is removed by etching.

Next, 1'jT i , P t is deposited by sputtering, and P
t is photoetched and Au plated, and Ti other than the wiring portion is removed by etching to form a Ti-Pt-Au wiring.

In both cases, the contact holes are all covered with electrodes, so the dimensions of the contact electrodes are made larger than the contact holes, as shown in the third row.

Further, as shown in FIG. 4 in the cross section of the contact electrode, the electrode film thickness tends to become smaller in the area around the contact hole.

However, as semiconductor devices become smaller, the area occupied by contact electrodes can no longer be ignored. However, in the conventional structure, as shown in FIG. 3 (13), C must be determined so as to reduce the misalignment during mask alignment. When α=2 μm, the area becomes 2α−4 μm, which is a non-negligible area when the number of contacts is large.

Further, as shown in FIG. 4, the electrode wiring film thickness around the contact hole tends to become small, resulting in disconnection or a decrease in current capacity.

For example, regarding a structure that makes contact between a diffusion layer formed on a semiconductor substrate and a wiring layer, Japanese Patent Laid-Open No. 51-3898
It is disclosed in No. 7.

The present invention solves the above-mentioned drawbacks, and aims to provide a novel method for manufacturing a semiconductor device having a small contact electrode area and a highly reliable electrode structure.

In order to achieve such an object, the present invention provides an electrode having the same dimensions as the contact and formed in the contact hole opening without any displacement, covering the contact hole, and masking the wiring pattern. The present invention relates to a method for manufacturing a semiconductor device configured to reduce the margin, that is, the contact area, and further prevent disconnection at the contact portion and decrease in current capacity. a step of forming a first layer of electrodes on the photoresist and the exposed semiconductor substrate; a step of removing the photoresist; The method is characterized by comprising a step of forming an electrode.

The present invention will be specifically explained in detail below using one preferred embodiment of the present invention.

FIGS. 1A-1F show an embodiment of the present invention. A contact hole 6 is formed in an insulating film 2 of about 1 .mu.m thick formed on a semiconductor (Si) substrate 1 by photoetching using a photoresist 3 of 1 .mu.m thick [FIG. 1(B)].

After that, first layer contact A! -2% Si electrode (for example, A1 containing 20% Si) 4 is formed to a thickness of about 0.5 μm by vacuum evaporation or sputtering [first
Figure (C)].

Thereafter, by removing the photoresist 3, the first layer of electrode 4 on the photoresist 3 is also removed using a photoresist stopper (see FIG. 1). Next, a second layer wiring film (for example, A-e containing 20% Si) 5 is formed to a thickness of about 1 μm by vapor deposition or sputtering, and a wiring pattern is etched using a photoresist 3'. Figure 1 (
to))〕.

Examples of electrode wiring formed in this manner are shown in FIGS. Since the contact is covered by the contact electrode 4, there is no problem even if the mask alignment of the wiring 5 deviates by α, so there is no need to particularly increase the dimensions of the contact portion.

FIG. 5 shows another embodiment of the invention.

001 μm of Pt is formed as a contact electrode with Si, W-10% Ti is formed as a barrier layer, and A, . By changing the first layer electrode material and the second layer wiring material in this way, electrodes with various contact characteristics can be easily obtained without increasing the contact electrode area.

Although the present invention has been described above, the present invention is not limited to such cases (application of one material for each).

Possible applications.

In the present invention, since the contact hole opening portion is covered with the first layer electrode, there is no problem even if there is a misalignment of the mask in the second layer wiring, and therefore the area of the contact electrode can be reduced. Furthermore, since the contact hole can be filled with the first layer electrode, disconnection of the wiring and reduction in current capacity around the contact hole can be prevented.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 (5) to [F] are cross-sectional views showing the method for manufacturing a semiconductor device according to the present invention, and Fig. 2 (5) to [F]) show contact holes and wiring according to the present invention. Figure 3-03) is a plan view showing the relationship between the conventional contact hole and wiring, Figure 4 is a cross-sectional view showing the relationship between the conventional contact hole and wiring, and Figure 5 The figure is a sectional view showing an electrode portion of a semiconductor device according to the present invention. l...Semiconductor base, 2...Insulating layer, 3, 3'...
Photoresist film, 4... First layer contact electrode, 5.
...Second layer wiring, 6...Contact hole, 7...Pt
Si layer. Figure 1] Figure 4 Figure 5 Evening

Claims (1)

[Claims] 1. (11) Step of selectively removing an insulating film formed on a semiconductor substrate using a photoresist (2) A first layer of electrodes is formed on the photoresist and the exposed semiconductor substrate. Step (3) of removing the photoresist (
4) A method for manufacturing a semiconductor device, comprising the step of forming a second layer electrode on the first layer electrode.