JPS6050695A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To set a prescribed data pattern to an RAM when a power source is turned on, by setting a circuit constant of a memory cell containing a flip-flop to a prescribed value. CONSTITUTION:A memory cell of a matrix array for forming an RAM contains an FF27 formed by CMOS invertors 23, 24 of a crossing connection, and the impedance of a PMOSFET35 is set so as to be larger than the impedance of a PMOSFET36. Accordingly, when a power source is turned on, the potential of an output terminal 31 of an invertor 26 rises quickly from an output terminal 28 of the invertor 23, and an N type MOSFET22 of the invertor 23 is turned on. As a result, the potential of the output terminal 28 drops quickly by discharging, the output terminal 28 is set to logic ''0'', and the output terminal 31 is set to logic ''1'' by charging. Accordingly, when the power source is turned on, prescribed data is set to the RAM, it is unnecessary to store a necessary program in an ROM only when the power source is turned on, and the ROM can be utilized effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a static type semiconductor memory device capable of reading and writing data.

[Technical background of the invention and its problems]

Semiconductors/memories used in microcomputers, etc. include FROM (programmable k ROM), MROM (7, X I ROM), which store fixed data.
), etc., and SRAM (
There are two types of RAM: static RAM (static RAM) and DRAM (finami RAM). Here, the above R
OM includes data such as a software operating system that requires a constant value only for γ at system startup, and does not necessarily require the entirety when executing a user program, and IPL (Initial Program Loader). In many cases, programs such as those used only at startup are pre-stored.

Storing data or programs in the ROM that are used only at startup and are not used thereafter is extremely inconvenient from the standpoint of effectively utilizing the memory area. Therefore, it is conceivable to store such data or programs in RAM instead of ROM. However, in conventional static RAMs that have flip-flops as data storage means, the internal storage state is not constant when the power is turned on, so predetermined data cannot be set after the power is turned on, unlike in a ROM.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and its purpose is to provide a static RAM type semiconductor memory device in which a predetermined data pattern is set when power is turned on. .

[Summary of the invention]

In the semiconductor memory device according to the present invention, predetermined data is stored in each memory cell when power is turned on by setting circuit constants of the memory cells each having a flip-flop as a data storage means, and thereby a predetermined data pattern is set. It is configured as follows.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a semiconductor memory device according to the present invention. In the figure, No. 1 indicates a memory cell in which static memory cells each having a flip-flop as a data storage means are arranged in a matrix in the X direction (e.g. row direction) and in the Y direction (e.g. column direction). In this memory cell matrix 11, the memory cells in the X direction are selected by the X decoder 12, and similarly, the Y decoder 13Vc selects the memory cells in the
A memory cell in the direction is selected. In the case of data reading: Data is read from the memory cell in the memory cell matrix 11 selected by the X decoder 12, Y decoder 13, and K, and the read data is detected by the sense amplifier 14.

This detection data is supplied to the input/output circuit (Ilo) J5, and the input/output circuit 15 outputs data corresponding to the read data. In the case of data writing, write data is supplied from the input/output circuit 15 to the data writing circuit 16, and based on the output of the data writing circuit 16, the data is selected by the X decoder 12 and the Y decoder 13. Data is written to memory cells within the memory cell matrix 1.

FIG. 2 is a circuit diagram showing the configuration of one memory cell in the memory cell matrix 11 of FIG. 1, and the other memory cells are similarly configured. This memory cell is of the so-called CMO3 type, and is a P-channel MO8FET.
,! A CMOS inverter switch consisting of 22 N-channel MO8FETs and a P-channel MO8F
A flip-flop 27 is provided in which the input and output terminals of CMO inverters each consisting of an ET 24 and an N-channel MOSFET x s are alternately connected. And the above C which is one data storage point of this flinopfronopl
N-channel MO for transfer gate between output terminal 28 of MOS inverter U and one data line 29
SFET, 90 is connected. Similarly, the CMO which is the other data storage point of the flip-flop
Output end 31 of S inverter 11 and other data line 3
2 and N-channel MOS for transfer gate
FET 33 is connected. and an N-channel MOSFET for the two transfer gates, 90;
33 (7) Commonly connected to each tart-Howard line 34. In addition, the flip 70 knob 27'f: P channel M in the CMOS inverter 2.9 that constitutes one side.
A P-channel MO8FET 35 is connected between the O8FET 21 and the point where the high voltage power supply potential vD2 is applied.
7) MOSFET, 15 darts are connected to the above VDI) application point.

In addition, the P-channel MO8FET 24 in the other CMOS inverter configuring the above-mentioned 7 lip-flops and jLi.
and the above vDD application point 1/CdP channel M) SF
ET 36 is connected, and MO8FET 36 is also connected to the vDD application point. The two P channel #MO3FETs 35 and 36 are connected to the CMOS
It acts as an impedance means having a predetermined impedance for the invar p2.9+26K.

Moreover, the two P-channel MO3FETs, 95,
36 are set to have different impedance values by means such as different channel widths. That is, in this memory cell, flip-flop 1
) P-channel MDSFEITs 35, 35 as impedance means having different values are inserted in the middle of the power supply path of the two CMOS inverters 23, 26 constituting the circuit. Note that all the MOSFETs used in this memory cell are of the enhancement type.
6 input terminal.

In such a configuration, the two P channels M
O8FET 35, 36 (one of D) MOSFE
The impedance of T35 is set higher than that of the other MOSFET 36. The power is turned on in this state. At this time, P channel yDSFET J
The impedance of 5 is P channel MO8FliT s
Since it is set larger than e, after the power is turned on, C
The potential of the output terminal 3 of the MOS inverter 26- is CMO.
The potential at the output terminal 28 of the S-inputter 2 also rises quickly. The potential 4 of the (5° output terminal 3) of the CMOS inverter 26 is input to the other CMOS inverter, so when this potential reaches the threshold voltage of the CMOS inverter 11, the CMOS MOSFE
ON channel kMO8FET22 in T3 turns on. When this MOSFET 22 turns on, the potential at the output terminal 28 of the CMOS inverter J is rapidly discharged toward the low power supply potential vss. In addition, the output end 28
is discharged toward V, , the P-channel MO8FFJT 24 in the CMOS inverter 26 is turned on, and the output terminal 3 of the CMOS inverter 26 is thereby turned on.
The potential at is rapidly charged toward the potential at DD. As a result, in this memory cell, when the power is turned on, the output terminal 28 of CMOS inverter 1 is V81! In other words, the output terminal 3 of the CMOS inverter 26 is at the logic "O" level (vI)
Data setting is performed so that the signal becomes f, that is, the logic "1" level. Similarly, in other memory cells, the two P-channel MO8FETs 35 are connected.

By making the impedances of 36 different from each other,
Each predetermined data setting is performed when the power is turned on.

Therefore, by using memory cells having the configuration as shown in FIG. 2 in the memory cell matrix 11 of FIG.
In this memory area) in the IJ box 11, predetermined data can be stored in each memory cell when the power is turned on, and a predetermined data pattern is thereby set.

Therefore, the software operating system, IPL, etc. that were conventionally stored in ROM can now be stored in RAM, allowing the user to use the memory area effectively.In other words, this storage device is a static type RAM. Mask ROM while having the characteristics as
A static RAM that also functions as a mask ROM and coexists with a mask ROM can be realized with one device.

FIG. 3 is a circuit diagram showing the structure of a memory cell according to another embodiment of the invention. This memory cell can be used in the memory cell matrix in FIG. 1 instead of the one in FIG. 2 above. This memory cell differs from that of FIG. 2 in that the P-channel P/DsFETs 35, . Instead of 96, N-channel MO, S, FET with different impedances
4 J, 42 to two CMOS inverters 23.2
It is designed to be inserted in the middle of the power supply path of No. 6.

That is, the N-channel MO8FET 4J is connected between the N-channel MO8FET z 2 in one CMOS inverter 23 and the low power supply potential V□ application point.The dirt of this MOSFET 41 is connected to this MOSFE
It is connected to the series connection point between T 41 and the MO8FET 22.

However, the N-channel MO8FET 42 is connected between the N-channel MO8FET 25 in the other CMOS inverter 26- and the potential v, 8 application point, and this WE
) SFF, T 42 dirt is this MOSFET 42
and the MO8FET 25 are connected in series.

The memory cell according to this embodiment also has two N-channel M
By making the impedance values of O8FET41 and 42 different, two CMOS
Inno Kuta 33,260 Outer Bubba W2 B, , 91
The rising speed of the potential at is made different, and thereby a predetermined data setting is made.

FIG. 4 is a circuit diagram showing the configuration of a memory cell according to still another embodiment of the invention. The difference between the memory cell according to this embodiment and the one shown in FIG. 2 is that the P-channel MO8FET, 9
Instead of providing 5 and 36, two CMOS inputs are provided.
Ta23,! P-channel MO3FET 4 as impedance means with different values between the input and output terminals of -6
3, 44 f, was inserted. That is, the output terminal 28 of one CFL[)S inverter
The P-channel MO8FET 43 is connected between the input terminal 38 of the other CMOS inverter l5, and the M
The output terminal of OSFET 4.41 is connected to the output terminal 31 of the CMOS input terminal 26 and the output terminal 31 of the other CMOS input terminal 26.
The P-channel MO8FET 44 is connected between the input terminal 37 of the OS inverter B, and the MOSFET 4
The date 4 is connected to the output terminal 71 of the CM)S inverter 26.

In the memory cell according to this embodiment, two P-channel M
By changing the impedance values of O8FET4J and 44, two CMOS inverters 23
．． By changing the time constants during input transmission between 26 and 26, when the power is turned on, one of the CMOS input/(
-The evening is always the first to do the reversal motion f[.

For example, by setting the impedance of P-channel MO8FET 4J to be larger than that of P-channel MO3FET 44, CMOS impertus! The potential at the input terminal 38 of CMOS inverter n rises more slowly than the potential at the input terminal 37 of CMOS inverter n. Therefore, in this case, CM
The OS inverter 23 operates inverted first, and as a result, the CM
The output terminal 28 of the OS inverter is at the logic "o" level.
Data setting is performed so that the output terminal 31 of the CMOS input terminal 31 reaches the logic IH level.

FIG. 5 is a circuit diagram showing the configuration of a memory cell according to another embodiment of the present invention. In each of the embodiment circuits shown in FIGS. 2 to 4, there is no parasitic capacitive force between the input terminals 37.38 of the two CMOS inverters 23 and 26 and the v68 application point. The value of this capacitance is usually equal to 11. Therefore, in this embodiment circuit, two α section inverter main), an input terminal of g7
, 3 A capacitance (capacitance means) that exists parasitically between B and the vss application point; The value 45.46 is two CMOS in marks. In this embodiment circuit, the capacitor 45.46 is in a state equivalent to being connected to the output terminal 31.2B of the CMOS inverter 26.23. Therefore, the rate of rise in potential at the output end of the CMOS inverter to which the capacitor with the larger value is connected is slower than the other capacitor, and as a result, predetermined data is set when the power is turned on.

FIG. 6 is a circuit diagram showing the structure of a memory cell according to another embodiment of the present invention, in which a KCMO3 type cell is shown as in the case of FIGS. 2 to 5. In this example circuit, CMOS inverters 2, ? , 26- are made to have different circuit threshold voltages, thereby allowing predetermined data settings to be made when the power is turned on. For example, if the circuit threshold voltage of one CMOS inverter 23 is set to be smaller than that of the other CMOS inverter, when the power is turned on, one CMOS inverter 23
The OS inverter 23 always performs inversion operation first, and as a result,
The output terminal 28 of the CMOS inverter 23- is logic "0#"
Data is set so that the output terminal 3 of the CMOS inverter 26 is at the logic "1#" level.

FIGS. 7 to 11 are circuit diagrams showing the configurations of memory cells according to other embodiments of the present invention. 2nd above
Each of the memory cells according to the embodiments shown in FIGS. 6 to 6 is of the 0MO8 type, but this
It is also possible to implement the NMO8 type using only O3FF and T.

That is, in the memory cell of FIG. 7, MOSFET 51 is a load MO8FET, and MOSFET 52 is a drive MO.
Inverter with 8FET and MO8FFJT 54
Flip-flops are provided in which the input and output terminals of an input/multiplier 66 are connected alternately to each other. In addition, in FIG. 7, the same reference numerals are given to the parts corresponding to those in FIG. 2, and the explanation thereof will be omitted.

In a memory cell having such a configuration, in order to perform predetermined data setting when power is turned on, the MOSFETs 51 and 52 (D impedance values) in the two inverters 53 and 56 are set to be different from each other.

That is, in this memory cell, the flip-flop 57
There are two intensifiers that make up 5J.

MOSFETs 51 and 54 as impedance means having different values are inserted in the middle of the power supply path of MO8FET51 and MOSFET54.
also plays a role as a load MO8FET.

In the memory cell of FIG. 8, MOSFET 51 in FIG.
．． The impedance values of 54 are set equal, and MOSFETs 58 with different impedances are used instead.
, 59 are inserted between the driving MOSFETs 52 and 55 and the application point of the low potential power supply voltage vB8.

In the memory cell shown in FIG. 9, as in the case of the α-shaped memory cell shown in FIG.
, '' are inserted between the input and output terminals of the MOSFETs 60 and 61 as impedance means having different values.

In the memory cell shown in FIG. 10, the 0MO8 shown in FIG.
Similar to the NMO8 type memory cell, the NMO8 type memory cell also has two inverters forming a flip-flop -Ll-, two input terminals or MOSFETs 52,
The values of the capacitances 71 and 72 that exist parasitically between the gate of 55 and the vsB application point are set to be mutually exclusive.

In the memory cell shown in FIG. 11, the 0MO8 shown in FIG.
Similarly to the NMOS type memory cell, by making the circuit threshold voltages of the two inverters 53 and 56 that constitute the flip-flop different from each other, a predetermined data setting can be performed when the power is turned on. It was designed so that the following was carried out. In addition, two inverters Ll
.

The circuit threshold voltage of 56 is the driving MOSFET, 52
It is set by adjusting the threshold voltage of .degree.55.

However, this invention is not limited to the embodiments described above, and various modifications are possible. For example, the memory cell may be modified by combining the memory cell shown in FIG. 2 with that shown in FIG. 4. It is possible to rub.

〔Effect of the invention〕

As explained above, according to the present invention, the circuit constants of the memory cells each having a flip-flop as the two-data storage means are set.

It is possible to provide a static RAM type semiconductor memory device in which predetermined data/turns are set when power is turned on.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a semiconductor memory device according to the present invention, and FIGS.
FIG. 2 is a circuit diagram showing the configuration of one memory cell in the memory cell matrix shown in the figure. 11...Memory cell matrix, 12...X decoder% 13...Y decoder, 14...Sense amplifier, 15...I/O circuit, 16...Data write circuit,
2.9, 26...CMOS inverter, 27.57
...Flip-flop, 53.56- Inverter. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10

Claims (8)

[Claims] (1) A plurality of memory cells each having 70 flip horns as a data storage means and configured to store predetermined data when the power is turned on by setting circuit constants, and storing the predetermined data when the power is turned on. A semiconductor memory device characterized in that it is configured such that a pattern is set. (2) The semiconductor memory device according to claim 1, wherein the flip 70 horn has two inverters whose protruding edges are alternately connected. (3) The semiconductor memory device according to claim 2, wherein the inverter is a complementary MO3 type inverter. (4) The semiconductor memory device according to claim 2, wherein the inverter is composed of a drive transistor (MO8) and a load element. (5) Predetermined data is stored in the memory cells when the power is turned on by inserting impedance means having different values in the middle of the power supply paths of the two inverters. The semiconductor storage device described in . (6) Predetermined data is stored in the memory cell when the power is turned on by inserting an impedance means between the input and output terminals of the two inverters, the values of which are applied externally to each other. The semiconductor memory device according to item 2. (7) Predetermined data is stored in the memory cell when power is turned on by making the circuit threshold voltages of the two inverters different from each other. Body memory device. (8) By inserting capacitance means having different values between each input terminal of the two inverters and a predetermined potential, constant data is stored in the memory cell when the power is turned on. A semiconductor device according to claim 2, wherein the semiconductor device is configured as follows.