JPS60235430A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS60235430A JPS60235430A JP59090914A JP9091484A JPS60235430A JP S60235430 A JPS60235430 A JP S60235430A JP 59090914 A JP59090914 A JP 59090914A JP 9091484 A JP9091484 A JP 9091484A JP S60235430 A JPS60235430 A JP S60235430A
- Authority
- JP
- Japan
- Prior art keywords
- metal plate
- semiconductor substrate
- thermal expansion
- support member
- expansion coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はパワートランジスタに係り、特に半導体基体が
それを支持するための支持部材上に導電的に又は絶縁し
て載置された構造の半導体装置に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a power transistor, and particularly to a semiconductor device having a structure in which a semiconductor substrate is placed conductively or insulated on a support member for supporting the semiconductor substrate. Regarding.
従来の半導体装置を第１図によって説明する。 A conventional semiconductor device will be explained with reference to FIG.
１はシリコーン等で形成された半導体基体、２は鋼板等
で形成された支持部材、３はアルミナ等で形成された絶
縁基板、４は銅板等で形成されたヒートシンクである。Reference numeral 1 denotes a semiconductor substrate made of silicone or the like, 2 a support member made of a steel plate or the like, 3 an insulating substrate made of alumina or the like, and 4 a heat sink made of a copper plate or the like.
上記の各部材間は、鉛−錫系のはんだ５．６．７によっ
てそれぞれの面に対向して接合されており、多層構造を
形成している。The above-mentioned members are joined to each other by lead-tin solder 5, 6, 7 so as to face each other, forming a multilayer structure.
一般的にパワートランジスタと称するＩＯＡ〜２０Ａ級
の半導体基体を内蔵する半導体装置は上記の層構造を有
する。A semiconductor device containing a built-in semiconductor substrate of IOA to 20A class, which is generally called a power transistor, has the above-mentioned layer structure.
上記半導体装置を安全かつ安定に動作させるためには、
半導体装置の動作時に生ずる熱をパッケージの外部に有
効に発散させる必要かある。また繰返し動作によって生
ずる温度差に対して、耐える構造が必要である。さらに
詳説すると、半導体装置は、通電、休止の繰り返しに伴
なって、上記半導体基体は高温状態（約１００〜１５０
℃）と、低温状態（周囲温度）とか繰返し訪ｎることに
なる。このような高温−低温の繰返し毎に、該半導体装
置における各部材は、そわらに固有の熱膨張係数に基づ
く膨張、収縮を繰返すことになり、最も軟かい部材であ
るはんだ層に熱歪として加わることになる。繰返し数（
ヒートサイクル）が多くなると、はんだ層は引張り歪、
圧縮歪の周期的かつ反軍なる印加によって、次第にもろ
くなり、ついには熱疲労現象を生ずるに至り、例えばは
んだ層にクラックか生じ、接着力の低下、熱伝導性の低
下等を引起し、半導体装置の品質低下を来たし、著しい
ものは破壊にまでおよぶ。In order to operate the above semiconductor device safely and stably,
There is a need to effectively dissipate heat generated during the operation of a semiconductor device to the outside of the package. A structure that can withstand temperature differences caused by repeated operations is also required. To explain in more detail, as the semiconductor device is repeatedly energized and stopped, the semiconductor substrate is in a high temperature state (approximately 100 to 150 degrees Fahrenheit).
℃) and low temperature conditions (ambient temperature) will be visited repeatedly. With each repetition of high and low temperatures, each member of the semiconductor device repeats expansion and contraction based on its own coefficient of thermal expansion, which causes thermal strain to be applied to the solder layer, which is the softest member. It turns out. Number of repetitions (
When the number of heat cycles (heat cycles) increases, the solder layer becomes tensile strained,
Periodic and counter-force application of compressive strain gradually causes the semiconductor device to become brittle, eventually leading to thermal fatigue phenomena.For example, cracks occur in the solder layer, causing a decrease in adhesive strength and thermal conductivity, etc. The quality has deteriorated, and in some cases it has even been destroyed.
本発明の目的は、上述した問題点を解決し、動作の繰返
し時に接合部に生じる熱歪を低減し、品質低下あるいは
破壊の恐れかない改善された半導体装置を提供すること
にある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide an improved semiconductor device that reduces thermal strain occurring in the joint during repeated operations and is free from the risk of quality deterioration or destruction.
本発明は上記目的を達成するため、第１図の層構造を有
する半導体装置において、支持部材２に異種の２以上の
金属層が互いに直接接着された積層構造を有する複合金
属板を使用し、かつ上記複合金属板の熱膨張係数が半導
体基体の熱膨張係数に近接するように諷整されているこ
とを特徴とする。In order to achieve the above object, the present invention uses a composite metal plate having a laminated structure in which two or more metal layers of different types are directly bonded to each other as the support member 2 in a semiconductor device having the layered structure shown in FIG. Further, the composite metal plate is characterized in that the coefficient of thermal expansion of the composite metal plate is adjusted to be close to the coefficient of thermal expansion of the semiconductor substrate.
以下本発明を実施例により説明する。 The present invention will be explained below with reference to Examples.
第１図に本発明の４００■、１５Ａ級トランジスタの要
部断面図を示す。１はシリコン半導体基体で、２は複合
金属板で形成さｎた支持部材、３はアルミナ基板、４は
銅板で形成されたヒートシンクである。上記各部材間は
鉛−錫系のはんだ５．６．７によって、それぞれの面に
対向して接合されている。また上記複合金属板は鉄−３
６９６ニツケルの両面に銅板を配し、冷間圧延法により
直接一体化されたもので熱膨張係数は約８ Ｘ １０−
’／℃であり、銅の熱膨張係数１８ ｘ １０−’／ｒ
、の約１／２になり、またシリコーン半導体基体の熱膨
張係数３、５ Ｘ １０″（１７℃に近い値になってい
る。FIG. 1 shows a sectional view of essential parts of a 400cm, 15A class transistor of the present invention. 1 is a silicon semiconductor substrate, 2 is a support member made of a composite metal plate, 3 is an alumina substrate, and 4 is a heat sink made of a copper plate. The above-mentioned members are joined with lead-tin solder 5.6.7 so that their respective surfaces face each other. In addition, the above composite metal plate is iron-3
Copper plates are arranged on both sides of 696 nickel and directly integrated by cold rolling, and the coefficient of thermal expansion is approximately 8 x 10-
'/℃, and the coefficient of thermal expansion of copper is 18 x 10-'/r
, and the thermal expansion coefficient of the silicone semiconductor substrate is 3.5 x 10'' (approximately 17°C).
以上説明した本実施例半導体によれば、支持部材の熱膨
張係数か従来の銅板に比べ小さくなっていることおよび
シリコーン半導体基体との差か縮少されたことによって
、トランジスタの運転時に過大な熱歪が発生するのを抑
制することかでき、その結果はんだ層の熱疲労を避ける
ことができる。According to the semiconductor of the present embodiment described above, the coefficient of thermal expansion of the support member is smaller than that of a conventional copper plate, and the difference with the silicone semiconductor substrate is reduced, so that excessive heat is generated during operation of the transistor. The generation of strain can be suppressed, and as a result, thermal fatigue of the solder layer can be avoided.
第２図は本実施例の半導体装置に断続的に通電して、半
導体基体１が９０℃の温度変化か生ずるようにしながら
、半導体基体からヒートシンク４に至る放熱経路の熱抵
抗を追跡した結果（Ａ）である。同図には支持部材に銅
板を用いた従来構造の結果（Ｂ）を比較して示す。FIG. 2 shows the results of tracing the thermal resistance of the heat dissipation path from the semiconductor substrate to the heat sink 4 while the semiconductor device of this embodiment is intermittently energized so that the temperature of the semiconductor substrate 1 changes by 90°C. A). The same figure shows the result (B) of a conventional structure using a copper plate as a support member for comparison.
同図より次が明確である。すなわち耐ヒートサイクル性
は銅板を用いた構造に比べ格段に向上している。また熱
抵抗は約１０９６高くなっているが、本発明の実施例に
は殆んど影響の無い範囲内である。The following is clear from the figure. In other words, the heat cycle resistance is significantly improved compared to a structure using a copper plate. Further, although the thermal resistance is increased by about 1096, it is within a range that has almost no effect on the embodiments of the present invention.
なお上述した複合金属板の熱膨張係数は素材として用い
る金属層の種類や、各金属層の厚さを変化させることに
よっても調整可能である。Note that the coefficient of thermal expansion of the composite metal plate described above can also be adjusted by changing the type of metal layer used as a material and the thickness of each metal layer.
これらについては使用する半導体装置の特性面および使
用環境等から熱伝導性、熱膨張系数を調整し選択する必
要かあり、またはんだに対するぬれ性を付与するためニ
ッケルメッキ等の金属膜をめっき法等により形成してお
くのが好ましい。For these, it is necessary to adjust and select thermal conductivity and thermal expansion coefficient depending on the characteristics of the semiconductor device to be used and the usage environment.In order to provide wettability to solder, a metal film such as nickel plating is applied using a plating method. It is preferable to form it by.
以上説明したように、本発明によれば熱歪に基づ（金属
ろう接合部の熱疲労劣下が減少され、品質の低下および
破壊の恐れがない改善された半導体装置を提供するのに
効果かある。As described above, the present invention is effective in providing an improved semiconductor device in which deterioration due to thermal strain (thermal fatigue of metal soldered joints) is reduced, and there is no risk of quality deterioration or destruction. There is.
第１図は本発明にかかわる半導体装置の要部断面図、第
２図は半導体装置のヒートサイクル試験と熱抵抗変化を
表わした図である。
１・・・シリコン半導体基体、２・・・支持部材、３・
・・アルミナ基板、４・・・ヒートシンク、５．６．７
・・・はんだ。FIG. 1 is a sectional view of a main part of a semiconductor device according to the present invention, and FIG. 2 is a diagram showing a heat cycle test and a change in thermal resistance of the semiconductor device. DESCRIPTION OF SYMBOLS 1... Silicon semiconductor base, 2... Support member, 3...
...Alumina substrate, 4...Heat sink, 5.6.7
...Solder.
Claims (1)
部材と、半導体基体と支持部材とを接合する金属ろう層
より成り、上記支持部材に異種の２以上の金属層か互い
に直接接着された積層構造を有する複合金属板を使用し
た半導体装置。 ２、特許請求の範囲第１項記載において、上記複合金属
板の熱膨張係数が上記半導体基体の熱膨張係数に近接す
るように調整された半導体装置。[Claims] 1. Consisting of a semiconductor substrate, a metal support member on which the semiconductor substrate is mounted, and a metal solder layer for joining the semiconductor substrate and the support member, the support member includes two or more metal layers of different types. A semiconductor device that uses composite metal plates with a laminated structure that are directly bonded to each other. 2. The semiconductor device according to claim 1, wherein the thermal expansion coefficient of the composite metal plate is adjusted to be close to the thermal expansion coefficient of the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59090914A JPS60235430A (en) | 1984-05-09 | 1984-05-09 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59090914A JPS60235430A (en) | 1984-05-09 | 1984-05-09 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60235430A true JPS60235430A (en) | 1985-11-22 |
Family
ID=14011678
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59090914A Pending JPS60235430A (en) | 1984-05-09 | 1984-05-09 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60235430A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4872047A (en) * | 1986-11-07 | 1989-10-03 | Olin Corporation | Semiconductor die attach system |
| US4929516A (en) * | 1985-03-14 | 1990-05-29 | Olin Corporation | Semiconductor die attach system |
| JPH03136338A (en) * | 1989-10-23 | 1991-06-11 | Mitsubishi Electric Corp | Semiconductor device and brazing method for its manufacture |
| US6693350B2 (en) | 1999-11-24 | 2004-02-17 | Denso Corporation | Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure |
| US6703707B1 (en) | 1999-11-24 | 2004-03-09 | Denso Corporation | Semiconductor device having radiation structure |
| US6946730B2 (en) | 2001-04-25 | 2005-09-20 | Denso Corporation | Semiconductor device having heat conducting plate |
-
1984
- 1984-05-09 JP JP59090914A patent/JPS60235430A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4929516A (en) * | 1985-03-14 | 1990-05-29 | Olin Corporation | Semiconductor die attach system |
| US4872047A (en) * | 1986-11-07 | 1989-10-03 | Olin Corporation | Semiconductor die attach system |
| JPH03136338A (en) * | 1989-10-23 | 1991-06-11 | Mitsubishi Electric Corp | Semiconductor device and brazing method for its manufacture |
| US6891265B2 (en) | 1999-11-24 | 2005-05-10 | Denso Corporation | Semiconductor device having radiation structure |
| US6703707B1 (en) | 1999-11-24 | 2004-03-09 | Denso Corporation | Semiconductor device having radiation structure |
| US6798062B2 (en) | 1999-11-24 | 2004-09-28 | Denso Corporation | Semiconductor device having radiation structure |
| US6693350B2 (en) | 1999-11-24 | 2004-02-17 | Denso Corporation | Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure |
| US6960825B2 (en) | 1999-11-24 | 2005-11-01 | Denso Corporation | Semiconductor device having radiation structure |
| US6967404B2 (en) | 1999-11-24 | 2005-11-22 | Denso Corporation | Semiconductor device having radiation structure |
| US6992383B2 (en) | 1999-11-24 | 2006-01-31 | Denso Corporation | Semiconductor device having radiation structure |
| US6998707B2 (en) | 1999-11-24 | 2006-02-14 | Denso Corporation | Semiconductor device having radiation structure |
| US6946730B2 (en) | 2001-04-25 | 2005-09-20 | Denso Corporation | Semiconductor device having heat conducting plate |
| US6963133B2 (en) | 2001-04-25 | 2005-11-08 | Denso Corporation | Semiconductor device and method for manufacturing semiconductor device |
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