JPS6016996Y2 - Address selection device for input/output interface device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address selection device for selecting an interface device by address in an interface device connected to a data processing device through a data bus.

In conventional address selection devices, one unique address is set for an interface device, and the interface device is configured to operate when the set address is applied to the bus.

Therefore, in so-called program depacking, which checks whether the program of a data processing device is normal and discovers defective parts, an interface that corresponds to all input/output devices that should originally be connected to the data processing device is used. Equipment had to be prepared.

In other words, if even one of the interface devices is missing, the program will be detected as abnormal.In other words, if the interface device does not respond when an address is generated by the program, the program itself will be inspected as defective.

Therefore, when depacking a program for such a data processing device, it is generally necessary to prepare all types of interface devices to be connected to the data processing device, or
Or, if you cannot prepare all the interface devices that correspond to the program, only the address in the program,
It operated by replacing the address of the prepared interface device.

As shown in FIG. 1, an information processing system using this type of interface device has a main memory as an interface device 11 for digital input/output devices, an interface device 12 for digital input/output devices, and an inkface device for analog input/output devices. 13 etc. are provided for each input/output device, and these are connected to the data processing device 15 through a bus 14.

As shown in FIG. 2, various interface devices such as these, for example, those for transmission, when an address strobe is applied to the bus 14 and applied to the address latch circuit 17 through the terminal 16, generate signals on the bus 14 at that time. The current address is taken into latch circuit 17 through line 18.

This address from the data processing device 15 is sent to the comparator 19.
The address is compared with the address unique to the interface device set in the address setting circuit 21.

When the comparator 19 detects a match between the two addresses, a selection signal is generated at the output terminal 22 of the comparator 19.

For example, when writing data, a write strobe from the bus 14 is applied to the AND circuit 24 through the terminal 23, and the AND circuit 24 is logically ANDed with the selection signal at the terminal 22.

When the write enable signal is given to the gate circuit 25 from the AND circuit 24, the gate of the gate circuit 25 opens and the bus 1
Input data is written to the first-in-first-out memory 27 through the four-stranded wire 26 .

The written data is successively outputted under the control of the timing control circuit 28, and in the conversion circuit 29, for example, parallel data is converted into direct data, and the converted data is outputted from the terminal 31.

Further, when a write enable signal is generated from the AND circuit 24, the signal is sent to the line 33 as a response signal via the OR circuit 32.
is provided to bus 14 through.

In the case of data acquisition, when a selection signal is obtained in the comparator 19, its output at the terminal 22 is also applied to the AND circuit 34, so that a read strobe is applied to the bus 14 through the line 35 to the AND circuit 34. When this happens, the AND circuit 34 generates a read enable signal, which opens the gate circuit 36.

The serial data from the terminal 37 is converted into parallel data in the conversion circuit 29 and written into the first-in-first-out memory 38, which is read out and applied to the bus 14 through the gate 36 and through the line 39 as data. It is sent to the processing device 15.

The read enable signal output from the AND circuit 34 is supplied to the OR circuit 32 and sent to the bus 14 as a response signal.

In this way, in the conventional interface device, one address unique to the interface device is stored in the setting circuit 2.
1, and only when an address unique to this interface device is given to the bus, data can be input to or output from that interface device.

As mentioned above, when checking whether there is an error in the program of the data processing device 15, it is necessary to connect and check all the buses 14 of the interface devices included in the program, or If all such interface devices could not be prepared, it would be necessary to rewrite the addresses of the programs for the interface devices that could not be prepared.

In other words, a number of interface devices with the same function are actually connected to the bus 14, but for example, when testing a program in a factory, only one to a few interface devices are prepared. is normal.

For this reason, the program had to be changed and then depacked, which took a long time to complete, and the program could not be inspected correctly due to misreading.

Furthermore, when testing is performed using a program that has already been developed, that is, an existing program, it is necessary to change the address of each interface device to match the address of the program.

The purpose of this invention is to be able to respond to multiple addresses, thus allowing one interface device to function as multiple inkface devices, with fewer interface devices than are actually needed when testing a program. To provide an address selection device that can perform inspection even if several devices are prepared.

According to this invention, two addresses can be set, and a selection signal can be generated for either of the two addresses in response to a call from the data processing device.

Further, depending on the case, it is configured to be able to generate a selection signal for an address that exists between the two addresses.

Because of this configuration, when testing a program, for example, one interface device can operate as multiple interface devices, and from the data processing device's perspective, it is difficult to see whether the multiple interface devices are connected. It can be operated as follows.

Therefore, a program can be tested with a small number of interface devices, there is no need to take the trouble of rewriting program addresses, and correct testing can be performed in a short time.

For example, in FIG. 3, parts corresponding to those in FIG. 2 are shown with the same reference numerals, and in this invention two address setting circuits 41 and 42 are provided.

In this embodiment, the address setting circuit 41 is set to the maximum value of the addresses within the range, and the address setting circuit 42
sets the minimum value for that address range.

The addresses set in these address setting circuits 41 and 42 and the address set in the address latch circuit 17 are compared by comparators 43 and 44, respectively.

In the comparator 43, when the address taken into the address latch circuit 17 is equal to or smaller than the address set in the address setting circuit 41, an output is generated, for example, at a high level.

In the comparator 44, when the address of the address latch circuit 17 is equal to or larger than the address of the address setting circuit 42, an output thereof is generated and becomes high level.

The outputs of these comparators 43 and 44 are supplied to an AND circuit 45.

The output of the AND circuit 45 becomes a selection signal and is supplied to the AND circuits 24 and 34.

The rest is the same as the case shown in FIG.

Therefore, when the address applied to the bus 14 is within the range of the two addresses applied to the address setting circuits 41 and 42, this interface device is selected, and a selection signal is applied to the AND circuit 34. When writing data in the same manner as explained in connection with FIG.
4 is written into the memory 27 through the gate circuit 25, and conversely, when reading data, data from the memory 38 is supplied to the bus 14 through the gate circuit 36.

Therefore, when a plurality of interface devices of the same type are used in an actual system, if consecutive addresses are given to the interface devices of the same type, the addresses at both ends of the consecutive addresses can be assigned to the address setting circuit 41. By setting it to .42, for example, the interface device for the digital input/output device is represented by one interface device, and similarly the interface device for the analog input/output device is represented by another interface device. Thus, it is possible to check a program without having to provide all the interface devices that are actually used.

Therefore, the correct program can be checked in a short time.

If the same address is set in the setting circuits 41 and 42, the interface device can operate as a normal interface device only when a single address unique to that interface device is given.

In other words, it can be used not only for inspection purposes, but also as an actual device.

Furthermore, if the set values of the setting circuits 41 and 42 are set at both ends of all addresses, failures in buses, etc. can be tested by combining them with a read/write test program for all addresses.

In this case, if the data input from the data processing device to the interface device is read out again to the data processing device and the terminals 31 and 37 are connected to compare the input and output, it is possible to check the addresses of the entire read and write operations.

As for data, it is possible to control not only digital data input/output but also analog data input/output. For example, inputting a flow rate signal and outputting a valve control signal, etc. You can also do it.

In that case, the memory 27.3B, the conversion circuit 29, etc. are circuits that convert analog signals and digital signals.

Furthermore, it can also be used as an interface device for main memory.

further internal within one interface device,
For example, it is possible to select a register, and in that case, for example, select the interface device above the decimal point of the setting value of the address setting circuit,
Each part within the interface device can be selected by the address below the decimal point.

Furthermore, in addition to connecting these data processing devices and input/output device interface devices to input/output devices within a relatively short distance, it is also possible to connect stations located relatively far apart by bus, and to This idea can also be applied to input/output interface devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data processing system, FIG. 2 is a block diagram showing a conventional interface device, and FIG. 3 is a block diagram showing an example of an interface device according to this invention. 11.12,13: Interface device, 14: Bus,
15: data processing device, 17: address latch circuit, 2
7: First in first out memory, 41.4
2 Near address setting circuit, 43.44: Comparator.

Claims (1)

[Scope of utility model registration request] An interface device that is connected to a data processing device through a bus and generates a selection signal when an address from the data processing device matches an address set in the address setting circuit, includes two address setting circuits that can change and set the address. . An address selection device for an input/output interface device, comprising means for generating a selection signal for any address between the two set addresses.