JPS601674A - Error detecting method - Google Patents

Abstract

PURPOSE:To detect assuredly an error of a data word by considering an error only with the data word that is decided erroneous by all error check codes of other plural series which are provided to the data block series of a prescribed number of data words. CONSTITUTION:A data block formed with a prescribed number of data words D1, D2- is provided with an error detecting cyclic redundancy check code C of a block series and p- and Q-series parity check codes P and Q of error check codes of different series. This data block is demodulated and an error is detected by the codes P and Q. Then P-series flags F1 and F2 and Q-series flags F3 and F4 of words are all set at ''1'' owing to the detection of an error. Thus the corresponding word is considered as erroneous. Thus it is avoided that forget the preceding word erasing that cannot be detected with the code C is detected as an error and that another word in the block is regarded as an error. Thus a word error can be assuredly detected.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an error detection method suitable for use in a so-called digital recording/reproducing apparatus.

BACKGROUND TECHNOLOGY AND PROBLEMS It has been proposed, for example, to perform AD conversion of audio signals and record and reproduce them as digital signals. In this case, error correction by so-called cross interleaving is performed. That is, forming a data word with predetermined hints of the digital signal,
A predetermined number of consecutive data words are set as a data block, and a CRC check code, for example, according to a sequence in this data block is provided, and a CRC check code, for example, according to a sequence different from the sequence in the above-mentioned data block is provided for the consecutive data blocks. A parity check code is set.

For example, in FIG. 1, the data signal to be recorded (transmitted) in C1 is provided with an address signal A after a synchronization signal S.
followed by data words D11D2 of 16 bits each;
, D3, and D4, each having a 16-bit variation check code 1-'P.

Q, CRC check code C are provided, and it is used as l data clock. This data block is transmitted sequentially. Here, the CRC check code C is formed for the data words D1-N)4 and the parity check codes P, Q in the same data block. Also, normality check node I
), Q is t(s). When the data blocks are arranged sequentially as shown in Figure 2, for example, solid lines and broken lines are formed for a continuous sequence.

In this case, the parity check code FQ is code l)
Since the parity check code is formed for the data including the parity check: J-)"P is formed first, the parity check code Q is formed, and then the CRC check code C is formed.
is formed.

By doing this, the inner η: (fJtttJIJ
) Sometimes, in a series of parity check codes P or Q, C among the data reads included in that series
If the error detected by the RC check code is only one sort, then the parity check code I) or (,
1 allows @J' iE to be repeated, and by alternately repeating the error correction 11- by the two sequences, it is possible to improve ilJ' +IgoiHika.

However, in such an apparatus, when recording is performed by reusing a recording medium that has been used once, the previous data signal may be reproduced due to unerased data. In this case, the data signal due to the erased residue can be detected by simply looking at that part, so the CRc check code cannot detect the error.

Also, depending on the content of the error, detection using the CRC check code may not be performed due to the severity of the error.

For this reason, if such erroneous data signals are overlooked and reproduced, abnormal sounds will occur in the reproduced signal, severely degrading the sound quality.

or the above parity check) lI) or Q
In the series, if an error data word detected by the CRC check and an error data word that was not detected are present at the same time, the detected error data word contains an error 61.
There is a risk that this will affect the next series and cause the error to be stopped.

SUMMARY OF THE INVENTION In view of these points, the present invention is designed to ensure that erroneous data words are detected.

SUMMARY OF THE INVENTION The present invention forms a data word with a predetermined number of digital signals, data blocks a predetermined number of successive nodes of this data, and generates an error check code according to the sequence within the data block. When demodulating a data signal in which a plurality of other error check codes are provided with a plurality of sequences different from the sequences in the data solo lock for the successive data blocks, - This is an error detection method in which the data sorting described above that is detected as an error simultaneously by all of the other plurality of error check codes is treated as an error.
The ability to reliably detect nodes.

Embodiment In FIG. 3, a flag F (1 hint) for an error pointer is set in each word of the random access memory into which ζ and data sort ν1 are loaded, together with 16-bit data. Here, the overall configuration of the random access memory is 11 old φ as shown in FIG.
The number of addresses corresponding to the data blocks related to the error R1' i1 are provided.

First, all flags F are set to "1°" in a row of random access methods as shown in FIG.

Next, divide the data signals 1) 1 to D4, parity check 2-does P, and Q of the data block judged to have no errors with the CRC check code 0 to the address corresponding to the address signal. , set the flag F of each stored sort to 0.

In addition, a parity check is performed in the DoP series.
At this time, if there is no data word with the flag F "1" and the parity check indicates an error, the flag F of the data 1 node of all C included in the series is set to "1".
This is done for all data solos.

Furthermore, if a parity check code (, 1) sequence is checked, and if there is no data word with flag F as "1" as described above, and the parity check is determined to be an error, all The flag F of the data 1 node is set to "1".At the same time, if the flag F is "l" as described above, the data word with the flag F set to "l" is set to 1. Do this for all databubs 1:1.

Thereafter, error correction is performed alternately using the series of parity check codes P1Q, as in the conventional case, to increase the C correction power.

In this way, error detection and correction are performed.

According to this method, the above-mentioned error caused by missing the CRC check mark can be prevented, and ii! '4iiFIl-C
Therefore, there is no risk that the effects of the error will spread.

That is, in FIG.
If the error is not detected and the data glock of medium heat a is incorrect, then barity check 1-1;
When a test is performed on the series P, the data word surrounded by a solid line is completely changed to Fl 1iji, and the flag F is set to "1". Next, a check is performed on the sequence of parity check codes Q, and at this time data word D1 of cheater block a = 0
4. Since the flag of P has already become "'l", the series including this data 1 node is not checked, and the data word surrounded by the broken line containing data sword Q is determined to be an error.
1i, and thereafter ζ correction is performed using this. Note that E in the figure does not indicate one go. In addition, the 13 data words that were found in the Izumi river are the parity Chesolani 1.
- This is an error detected when 11 tests are performed using the Q sequence.

By the method described above, check the parity
111i, even though one data word in the series is incorrect, all the data words in the series are considered to be errors, so even the incorrect data words are considered to be errors. Extremely large number of data sorts
ζ increases. In this case, the sequence of parity FP is AD/DA before cross interleaving.
This directly affects the sound quality, and if there are many erroneous data words in this sequence, the sound 1. iji deteriorates significantly.

Furthermore, if all data words in the parity check code P or Q series are found to be errors, it is extremely difficult to correct them in the other series (and there is a risk that the sound quality will deteriorate due to a lot of interpolation, etc.). will increase.

Therefore, in FIG. 5, in each word of the random access memory stored in the data word IS, 16-bit data and 4-bit flags I, F'' for the J-lar pointer are added. 2, F3, and F4 are set numbers.

Here flag 1-F2 is parity check code 1'
Flags F3 and F4 are for the P series, and flags F3 and F4 are for the Q series, and those that are found to be correct as a result of the parity check are used (()
,Q), there is an error due to CRC check pattern in 1 data line 1-
-A-2°C For those whose parity check was impossible (0, ■), parity check C: 6 gori and 'yen 11
i Salenokomononi (1, ()), a flag of (1, 1) is formed for those determined to be errors by the cRc4i scan code.

According to this, Balitei Chesokko 1. ')), the publication 1υ1 by the Q series is followed by all Dakshi 1').

Zunawaji random access memory flag F1/F4
Set all ζ to "1".

Next, the data block ``Dock signal 4t D 1 to D4,
parity check code 1), Q is "al" reply (i'4
3'J' Input p; into the address corresponding to A, τ! 1
- Set the flags F~F1 of each written lead to (0, ■,
0.1).

Furthermore, a parity check is performed on the sequence of 1"P, and if there is no data word marked as an error in the CRC check mark sequence, and no error is detected in the parity check, the The flags Fl and F2 of all data words in the series are set to (0, O), and when an error is detected, the flags Fl and F2 are set to (l, 0), and the CRC check code is incorrect. If there is 1 or more, leave it as is.This is done for all data blocks to 0.

Furthermore, in the series of parity check coats Q, the same test as described above is performed, and the flags F3 and F4 are replaced as necessary. This is done for all datab 1.

In this result, flags F1 to F4 are (Fj,
F2, F3, F4) = (1,0,1,0)...
・(1) −(1,0,0,1) ・ ・ ・(2) = (0,, ml O) ・ ・ ・(3) The data word is determined to be an error in the series of both swords and is an error. If the ijJ capability is extremely low, or if the - force is erroneous and the other is untestable, an erroneous i+J capability remains, making these data words erroneous.

On the other hand, since anything other than ``double'' is not considered to be an error in the single sequence, it is determined that other data words in the sequence are erroneous in the other sequence, and this is t
It should be treated as 1'' for a complete data sort.

In Figure 6, "ζ", the part (C) determined to be an error in the CRC check code C, and the above equation tl+, (2), (
3) Te Angusu Dokan 11i Sareta (11, (2), (31)
0:) Partial force i"4') is applied, and in the above example (0
), which was considered to be an error, will be reduced.

In addition, in FIG. 7, under the same conditions as in FIG. 4 above, only the erroneous data program a surrounded by a solid line and the part Q that is not determined in the parity check code P series are erroneous. This reduces the number of correct data words that are determined to be errors.

Therefore, the possibility of deterioration of sound quality is reduced.

Furthermore, in FIG. 8, if there are error data blocks b and c that are subjected to 1tli determination by CRC check code C along with error data block a, the states of flags F1 to F4 of each data word are not shown in the figure. become that way. Here, the results based on the series of parity check codes P are shown on the upper side, Q
The results from the series are written above with codes, and in the codes, E is (1, 0), U is (0, 1), and C is (1, 1, 1).
, ■), no mark indicates (0,0). In this case, the data words that are judged to be erroneous are all contained in the data blocks b and c detected in the CRC check frame "rJC" surrounded by a solid line, and only the data sorts D1 and P of the data block a.

In addition, FIG. 9 shows that there is no error due to CRC check code C, and 2
In the case where two data blocks a1 and a2 are consecutively erroneous, the error in this case is the data block I.
is the part surrounded by a solid line.

Furthermore, Fig. 10 shows that when there is an error data block b with CRC check code C in the vicinity of error data block a, it is determined that an error is detected. .

However, in the case of this method, if there are more than one erroneous data word due to the CRC check code C in both the validity check sequences P and Q, it becomes impossible to detect that data word. ζ Put away. However, it becomes impossible to detect the data words I)2 to D4 and Q in the data block a of FIG. 8, and there is a risk that errors may be overlooked.

In addition, as mentioned above, if the parity check is applied to the sequence of 1-doP and the sequence of
There is one erroneous data sorting due to CRC check fiT No. C on the sequence containing de
l- and +l- are performed, and there is a risk that the error 11-1 may spread due to the confusion.

By the way, as mentioned above, a data block that is not detected by the CRC check code C and is erroneous has an extremely high rate of occurrence in which all of the data blocks are erroneous.

Therefore, after performing the above-mentioned detection, each data word of the data block containing at least one erroneous data word is
Set flags F1 to F4 (1, ■, 1..1) with Kuretoshi'.
I end up making it. All data words surrounded by broken lines in FIGS. 1 to 1O are treated as errors.

This makes it possible to extremely reduce the chance of missing an erroneous data word.

However, in this case, if the number of data blocks judged to be errors by the CRC check 1, No. 1C is large, the correct data words will be judged as errors by the parity check.
There is a risk that the data word may be unnecessarily changed. Furthermore, if an erroneous data word that is not detected by the CRC check code C exists in the vicinity, a +E, dark data word will be judged as an error by both the parity check code P and Q series.
This may cause the entire data block containing the data word to become erroneous.

So, in the above detection, the data word that is determined to be correct is detected, and the part that is 71 marked in (4), (5), and (6) in Figure 6 is detected, and the correct data word is detected in the data block. All data words included in the data block are judged to be errors only when there is no at least one data sort.

For example, if at least one data word is correct, all data words of the data block are considered correct. As a result, data blocks a1b, c, al, a2
The erroneous data blocks can be almost completely identified by considering these otherwise unusual data words as being common.

Note that there is a probability that some data words in an erroneous data block happen to be correct and are cut off by TII, so the number of correct data words in the data block is detected and the number is greater than or equal to a predetermined number. It is determined that it is correct when .
It is also possible to determine the correct number of data words by weighting when F4 is (0, 0, 0, 0).

In addition, in the above example C, all the data 1 nodes that were marked as incorrect have flagged 1 to F4 rewritten to (il, 1.1), and are determined to be incorrect by 1 & CRC check code C. They shall be treated equally.

Effects of the Invention According to the present invention, it has become possible to actually detect erroneous data reads in G1.

[Brief explanation of drawings]

1 and 2 are diagrams for explaining a conventional error detector 1, and FIGS. 3 to 10 are diagrams for explaining the present invention. D1 to D4 are data words, P and Q are parity check codes, and F and F1 to F4 are flags for error pointers.

Claims (1)

[Claims] forming a data word at a predetermined focus of the digital signal;
A predetermined number of consecutive data words is used as a data block, and an error check code is provided according to a sequence within this data block, and a sequence different from the sequence within the data block is provided in a sequence of consecutive data blocks. When demodulating a data signal provided with a plurality of other error check codes according to a plurality of sequences, -1- data words that are simultaneously detected as errors by all of the other plurality of error check codes are demodulated. An error detection method that only considers errors as errors.