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JPS60145375U - Integrated circuit testing equipment - Google Patents

Integrated circuit testing equipment

Info

Publication number
JPS60145375U
JPS60145375U JP3360284U JP3360284U JPS60145375U JP S60145375 U JPS60145375 U JP S60145375U JP 3360284 U JP3360284 U JP 3360284U JP 3360284 U JP3360284 U JP 3360284U JP S60145375 U JPS60145375 U JP S60145375U
Authority
JP
Japan
Prior art keywords
integrated circuit
testing equipment
circuit testing
testing device
abstract
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3360284U
Other languages
Japanese (ja)
Inventor
森野　治美
正明 向井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3360284U priority Critical patent/JPS60145375U/en
Publication of JPS60145375U publication Critical patent/JPS60145375U/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本考案の一実施例の図、第２図は本考案の一
実施例の使用方法を示す断面図である。 １・・・・・・取り付は箱、２・・・・・・保護板、３
・・曲スペーサ、４・・・・・・試験基板、５・・・・
・・ソケット、６・・・・・・蓋、１２・・・・・・Ｄ
ＵＴ０FIG. 1 is a diagram of an embodiment of the present invention, and FIG. 2 is a sectional view showing how to use the embodiment of the present invention. 1...Mounting box, 2...Protection plate, 3
...Curved spacer, 4...Test board, 5...
...Socket, 6...Lid, 12...D
UT0

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 集積回路の寿命試験を行う試験装置上に、設けられたソ
ケットの開閉を蓋を押えて固定することを特徴とする集
積回路試験装置。An integrated circuit testing device for performing a lifespan test of an integrated circuit, characterized in that a socket provided on the testing device is fixed by pressing a lid to open and close the socket.
JP3360284U 1984-03-09 1984-03-09 Integrated circuit testing equipment Pending JPS60145375U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3360284U JPS60145375U (en) 1984-03-09 1984-03-09 Integrated circuit testing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3360284U JPS60145375U (en) 1984-03-09 1984-03-09 Integrated circuit testing equipment

Publications (1)

Publication Number Publication Date
JPS60145375U true JPS60145375U (en) 1985-09-26

Family

ID=30536204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3360284U Pending JPS60145375U (en) 1984-03-09 1984-03-09 Integrated circuit testing equipment

Country Status (1)

Country Link
JP (1) JPS60145375U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7633085B2 (en) 1999-03-29 2009-12-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7633085B2 (en) 1999-03-29 2009-12-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof

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