JPS60144963A - Mis type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of leakage currents just under a field oxide film after the projection of radiation by surrounding the periphery of a drain region by a gate region and surrounding the gate region by a source region connected to the minimum potential of the titled IC. CONSTITUTION:The periphery of a drain region 15 consisting of an N<+> diffusion region in an MOS transistor (TR) disposed to one main surface of a P type Si substrate 11 is surrounded by a gate region 16 in the MOS transistor, and the periphery of the region 16 is surrounded by a source region 14 as an N<+> diffusion region connected to grounding potential as the minimum potential of the titled MOSIC. Accordingly, even when the MOS type IC is irradiated by radiation and the threshold voltage of the isolated MOS TR by a field oxide film 12 reaches to supply voltage or lower, leakage currents do not flow because all of the potential of the N<+> diffusion region being in contact with the film 12 are brought to grounding potential together with the substrate 11.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to an MIS type semiconductor integrated circuit.

[Prior art]

Conventionally, an MO8 type field effect transistor (hereinafter referred to as a MOS transistor) is arranged as an insulated gate field effect transistor on the entire surface of a semiconductor substrate.
In integrated circuits, insulation isolation by a selective oxidation method (Locos method) is used as the most common method for isolating elements. FIG. 1 is a sectional view showing the main part of a conventional MO8 type integrated circuit for explaining this insulation separation.

As shown in FIG. 1, a thick field oxide film 2 (~1.theta. .mu.m) is formed on a silicon substrate 1 by a selective oxidation method to separate an adjacent source region 4 and drain region 5.

If necessary, immediately before selective oxidation, a channel stopper region 3 doped with impurities of the same polarity as the silicon substrate 1 is formed by ion implantation or the like just below the region other than the element region (field region) to form a thick field. By forming the oxide film 2, it was possible to prevent a channel from being induced in the oxide film-silicon substrate interface region directly under this field region due to an electric field effect.

By the way, according to this configuration, the FC shown in FIG.
If we assume that the field oxide film 2 is the gate oxide film of a MOS transistor and that there is a gate electrode 6 on it, then it is assumed that the source region 4 and drain region 5 of two normal transistors are electrically isolated from each other. The threshold voltage VT2 (hereinafter referred to as V,
and Q must be at least larger than the operating power supply voltage of the integrated circuit. Therefore, conventionally, the field oxide film thickness and the impurity concentration directly under the field oxide film have been set so that vT2 is 15 to 20.

In recent years, there have been many attempts to mount such MO8-type semiconductor integrated circuits on space satellites, but the problem is that
This is the radiation resistance of such an MO8 type semiconductor integrated circuit. In the case of the MO8 type semiconductor integrated circuit, a particular problem is the variation in the threshold voltage vT of the MOS transistor with respect to the amount of radiation exposure. FIG. 3 shows a change ΔvT in the radiation dose and threshold voltage of a conventional N-channel MO8) transistor. FIG. 4 similarly shows the relationship between the gate oxide film thickness and the change ΔvT in threshold voltage. (Je, Earl.

Adamus et al., @AradieshonHardeendfieldOxideI, E, E.

E,NS 24. Pond 6.1977.12. : J
.

R., Adams et al.
ion Harden-ed Field Oxide
” 1. E, E, I N5-24. Ah6゜Dec,
1977,) Figure 3 shows a case where the field oxide film thickness is 6000, and the threshold voltage change ΔVT2 of the transistor isolated by radiation irradiation is -15V to
It can be seen that it reaches -20v.

In the normal separation method, vT2 is set to 15 to 20v as an initial value.
Therefore, due to radiation irradiation, vT2 will vary from 0 to 5.
and electrical isolation becomes impossible. Also, FIG. 4 shows the threshold voltage change ΔVTN of the N-channel MO8) transistor.
and P-channel MO8) transistor threshold voltage ΔVT
This shows the results after radiation irradiation with a dose of 5 x 104 for both P. As the field oxide film thickness increases, the threshold voltage change ΔvT after radiation irradiation increases;
As the field oxide film thickness decreases, the threshold voltage change Δ
It can be seen that vT also tends to become smaller.

Thus, according to the prior art, after radiation irradiation, %1IC
This has the disadvantage that the threshold voltage of the isolation region on the N-channel side is significantly lowered, and the leakage current during circuit operation becomes extremely large.

[Purpose of the invention]

An object of the present invention is to provide a radiation-resistant MIS type semiconductor which prevents the threshold voltage of the isolation region from being significantly lowered due to radiation irradiation and obtains the desired circuit operation by eliminating the above-mentioned drawbacks. Its purpose is to provide integrated circuits.

[Structure of the invention]

An MIS type semiconductor integrated circuit according to the first aspect of the present invention is a MIS type semiconductor integrated circuit in which a plurality of insulated gate field effect transistors are disposed on the entire surface of a semiconductor substrate. The region is surrounded by a gate region, and the gate region is connected to the MI
It is constructed by being surrounded by a source region connected to the lowest potential of the S-type semiconductor integrated circuit.

An MIS type semiconductor integrated circuit according to a second aspect of the present invention is a MIS type semiconductor integrated circuit in which a plurality of insulated gate type field effect transistors are arranged on the entire surface of a semiconductor substrate, in which a drain region of the insulated gate type field effect transistor is provided. is the first
The first gate region is surrounded by a first source region, and the first source region is a gate connected to the lowest potential of the MIS type semiconductor integrated circuit. The periphery is surrounded by a second gate region having an electrode, and the second gate region is surrounded by a second source region connected to the lowest potential of the MIS type semiconductor integrated circuit. It consists of things.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 (al is a planar pattern diagram showing a main part of an embodiment of the first invention, and FIG. 5 1bl is a schematic cross-sectional view along x-x' thereof.

In this embodiment, a plurality of M
In an MO8 type semiconductor integrated circuit having an MO8 type transistor, the drain region 15 of the MO8 type transistor is surrounded by its gate region 16. The source region 14 is surrounded by a source region 14 made of an N+ diffusion region connected to a ground potential, which is the lowest potential of a semiconductor integrated circuit, through aluminum wiring or the like.

In FIG. 5 (al, (bl), 12 is a field oxide film with an oxide film thickness of 0.8 to 1.2 μm, 17
18 is a gate electrode made of N+ polysilicon, 19 is a gate electrode terminal, and 2 is a gate oxide film with a thickness of about 500 mm.
0 is a drain electrode terminal, and the P-type silicon substrate 11 is also connected to the ground potential.

According to this embodiment, N+ in contact with the field oxide film 12
All of the diffusion layers are source regions 14, and the potential is the ground potential, which is the lowest potential on the circuit, similar to the P-type silicon substrate 11.

Even when an integrated circuit is constructed on a P-type silicon substrate 11 by repeatedly using the transistor pattern shown in FIG.

Therefore, even if this MO8 type semiconductor integrated circuit is irradiated with radiation and the threshold voltage VT2 of the MOS transistor separated by the field oxide film 12 becomes lower than the power supply voltage, all the N+ diffusion layer regions in contact with the field oxide film 12 are Since it is at ground potential along with the mold silicon substrate, no leakage current flows.

In addition, the gate oxide film 17 in FIG. 5 (bl) has a thickness of 50 mm.
Since the field oxide film 12 is sufficiently smaller than the field oxide film 12, the threshold voltage change ΔVTN after radiation irradiation is sufficiently small. Therefore, this threshold voltage change ΔVTN
If the threshold voltage VTN of the MOS transistor is set as high as 2 to 3 V in consideration of this, unnecessary leakage current between the drain region 15 and the source region 14 can be ignored.

Furthermore, according to this configuration, the silicon substrate connected to the lowest potential is isolated from the source region, and a field oxide film for isolation is not necessarily required. The problem of threshold voltage drop due to irradiation can be solved.

By the way, when the source potential of the MOS transistor does not take the lowest potential but takes a certain predetermined potential, for example, in the case where the source region 14 becomes higher than the lowest potential in FIG. 5(a), Field oxide film 1 after radiation irradiation
There is a possibility that an inversion layer is formed under 2 and unnecessary leakage current flows.

The second invention has been made to address this problem.

FIG. 6 (al is a pattern plan view showing essential parts of an embodiment of the second invention, and FIG. 6 (bl is a schematic cross-sectional view along YY').

In this embodiment, in an MO8 type semiconductor integrated circuit in which a plurality of MO8 type transistors are arranged on one main surface of a P type silicon substrate 11', a drain region 15' consisting of an N+ diffusion region of the MO8 type transistor is 1 gate area 1
This first gate region IC is surrounded by a first source region 14' consisting of an N+ diffusion region, and this first source region 14' is surrounded by the MO8
The periphery is surrounded by a second gate region 22 having a gate electrode 24 connected to the ground potential, which is the lowest potential of a type semiconductor integrated circuit, and this second gate region 22 is connected to the MO8.
N+ connected to ground potential, which is the lowest potential of the type integrated circuit.
The periphery is surrounded by a second source region 25 consisting of a region.

In addition, in FIGS. 6(a) and (bl), 12' is a field oxide film 17' having an oxide film thickness of 0.8 to 1.2 μm.

be.

According to this embodiment, since the gate oxide film thickness 23 of the second gate region 22 is the same as the gate oxide film thickness of a normal MOS transistor, the gate oxide film thickness 23 of the second gate region 22 is connected to the ground potential which is generated by radiation irradiation. Unnecessary leakage current between the first source region 14' and the second source region 25 pulled to the lowest potential can be ignored.

Furthermore, since the second source region 25 in contact with the field oxide film 12' is at the lowest potential, no leakage current flows through the channel formed directly under the field oxide film 12 after radiation irradiation.

Furthermore, according to this configuration, as in the case of the first invention described above, the field oxide film for element isolation is not necessarily required, and the second gate electrode connected to the lowest potential and the second
are substantially separated in the source region. In this case, compared to the case of the first invention shown in FIG. You can take it.

Note that the above explanation uses N-channel type M as a transistor.
OS) Although it uses a transistor, it is a P-channel type MO8.
) The same applies to transistors such as sb and 1cMO8) The present invention is not limited to transistors, but can be similarly applied to MIS type semiconductor integrated circuits using insulated gate field effect transistors.

〔Effect of the invention〕

As described in detail above, since the MIS type semiconductor integrated circuit of the present invention has the above configuration, it is possible to prevent leakage current flowing directly under the field oxide film for element isolation after radiation irradiation. It has this effect.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view showing the main parts of a conventional MOS integrated circuit.
Fig. 2 is an explanatory diagram of the isolated MOS transistor that occurs in Fig. 1, Figs. 3 and 4 are radiation resistance characteristics of the conventional MOS transistor, and Fig. A plane pattern diagram showing the main parts of the embodiment, FIG. 5 (bl
is a schematic cross-sectional view taken along the x-x'line; FIG.
FIG. 6 (bl is a schematic cross-sectional view along Y-Y'lC. 1...Silicon substrate, 2...Field oxide film, 3...Channel stopper Area, 4.
...Source region, Li2...Source region, 14'...First source region% 15.15
'...Drain region, 16...Gate region, 16'...First gate region, 17...
...Gate oxide film, 1τ...First gate oxide film, 18...Gate electrode, 18'...
...first gate electrode, 19...gate electrode terminal, 19'...first gate electrode terminal, 20.
20'...Drain electrode terminal, 21...
・First source electrode terminal, 22...Second gate region, 23...Second gate oxide film, 24.
...Second gate electrode, 25...Second source region, D...Drain, G...
Gate, s...source. (A no (b) Kaya left mouth

Claims (2)

[Claims] (1) In an MIS semiconductor integrated circuit in which a plurality of insulated gate field effect transistors are arranged on the entire surface of a semiconductor substrate, the drain region of the insulated gate field effect transistor is surrounded by a gate region, and the drain region of the insulated gate field effect transistor is surrounded by a gate region. An MIS type semiconductor integrated circuit characterized in that the gate region is surrounded by a source region connected to the lowest potential of the MIS type semiconductor integrated circuit. (2) In an MIS semiconductor integrated circuit in which a plurality of insulated gate field effect transistors are arranged on the entire surface of a semiconductor substrate, the drain region of the insulated gate field effect transistor is surrounded by a first gate region. The first gate region is surrounded by a first source region, and the first source region is connected to a second gate having a gate electrode connected to the lowest potential of the MIS type semiconductor integrated circuit. MIS type semiconductor integrated circuit, characterized in that the second gate region is surrounded by a second source region connected to the lowest potential of the MIS type semiconductor integrated circuit. circuit.