JPS60124840A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the density of integration, reliability and yield preventing a disconnection from happening by a method wherein both perfect filling with polysilicon and surface flattening are performed regardless of the shape of U-shaped groove. CONSTITUTION:After successive forming of an SiO2 film 2 and an Si3N4 3 on an Si substrate 1, an etching mask is formed to etch a U-shaped groove 4. Firstly an SiO2 film 5 is formed on the wall. Secondly a poly Si 6 is grown up to the depth of 2-3mum to fill the U-shaped groove 4. At this time, an interface 12 is produced in the poly Si 6 subject to infirm chemical coupling. Thirdly the surface is annealed at the temperature of 700-1,200 deg.C in nitrogen (N2) atmosphere for moderate hours specified. Through this annealing process, the grains on the interface 12 is re-matched to make the interface 12 chemically firm not to be corroded by alkali solution. Also by this annealing process, any cavity around the interface 12, if any may be removed. After annealing process, the surface may be flattened by means of polishing as usual.

Description

Detailed Description of the Invention (11) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, a method for manufacturing a semiconductor device, in which a groove having a U-shaped cross section (hereinafter referred to as a U-groove) is formed in a semiconductor substrate, and an insulating material is embedded in the groove. The present invention relates to a method for forming an insulating separation layer.

(2) Background of the technology The method for forming an insulating separation layer using a U-groove is a method of filling a U-groove formed in a semiconductor substrate with polycrystalline silicon (1) (polysilicon) as an insulator, and is suitable for high integration. Are suitable. The process of forming an insulating separation layer will be explained below with reference to FIG. 1. First, as shown in FIG.
) A silicon dioxide (SiO2) film 2 is formed on a substrate 1, and then a silicon nitride (Si3N film) film 3 is formed.

Thereafter, a mask pattern is formed, a U-groove 4 is dug by reactive ion etching (RIB), and then a SiO2 film 5 is formed on the wall surface of the U-groove 4 by, for example, thermal oxidation.

Next, a polysilicon layer is grown by chemical vapor deposition (CVD) to fill the U-groove 4 (see figure (b)), and finally, the polysilicon layer on the nitride film 3 is removed by polishing to flatten it. ((C) in the same figure).

By the way, in the above-mentioned method of forming an insulating separation layer, it is desired that the U-groove 4 be completely buried with polysilicon and that the surface after polishing be flat.

(3) Prior art and problems In the conventional method of forming an insulating separation layer described above, chemically unstable parts (2) are created in the polysilicon buried in the U-groove, and potassium hydroxide (KOI+) is When polishing using such an alkaline solution, there is a problem in that scratches (areas where voids exist) are formed on the surface and flattening cannot be achieved. To explain this in more detail with reference to Figure 2, U
After forming the groove 4, the polysilicon layer is grown by the CVD method, as shown in the same figure (81 with dashed lines marked 7°8 and 9). Film growth progresses at the same rate at all locations on the film 3, and the polysilicon film 6 is gradually formed in the order of broken lines 7, 8, and 9.Then, the films indicated by the broken lines 7°8 and 9 are formed. During the growth process, grains
n) are formed by forming chemically stable bonds in the growth direction.

On the other hand, as the film growth progresses, the cavity in the U-groove 4 is gradually narrowed by the polysilicon film grown from the wall surface, and finally the film surfaces grown from the wall surface meet at the position of the broken line 10 and the U-groove 4 is filled. .

However, in the film growth process near the broken line 10 above, the newly grown grains (3) are fitted between the growing film surfaces, so the degree of freedom for bonding is lost and a chemically unstable interface is formed. Ru.

As a result, during polishing, the "-" surface is etched with an alkaline solution and cracks appear in this area.
As shown in the figure, a scratch 11 is formed on the surface after planarization.

This part 11 may cause disconnection in the wiring process,
This causes a problem that leads to a decrease in yield in the manufacture of semiconductor devices.

On the other hand, when forming U/II by RIE, it is ideal that the angle θ shown in the figure fal is 90 degrees and the wall surface is perpendicular to the excavation. It has been experienced that a wider U-groove can be created. In such a case, the chemical bond at the interface becomes even weaker, and in some cases, cavities may remain, making planarization more difficult. Due to the above-mentioned situation, there is also a problem in that the rate at which the U-groove is filled and flattened is achieved in the prior art is reduced.

(4) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention uses a U-groove (4) In a method for forming an insulating separation layer, the opening of the U-groove filled with polysilicon is flattened regardless of the shape of the U-groove. The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can be made into a semiconductor device.

(5) Structure and object of the invention According to the present invention, a cross section U is provided on a semiconductor substrate.
In this method, an oxide film is formed on the wall surface of the groove, and then the insulator is grown to bury the line groove, and then the substrate is removed. This is achieved by providing a method for manufacturing a semiconductor device, which includes the steps of annealing at a temperature below the melting point of the substrate, and then removing an insulator on the substrate to planarize it.

(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

As described in the above structure, the present invention provides chemical strength by aligning the interface, which was conventionally chemically weak, by annealing after polysilicon growth. The process will be explained in detail below.

First, as in the prior art, as shown in FIG.
) as (silicon substrate 1" 2 5i021! 2 and 5i
After forming the sN flag IK' 3, an etching mask is formed and a U groove 4 is dug using [E], and then 5i021 is formed on the wall surface.
Form 1 moxibustion 5. In this process, the opening width W of the U groove is, for example, 3 μm to 7 μm, and the SiO2
The film 5 is formed by thermal oxidation at a temperature of 900°C.
℃~1000℃, the film thickness formed is 500~3000.

Next, as shown in FIG. 3, polysilicon is grown to a thickness of 2 to 3 .mu.m by low pressure CVD to bury the U-groove 4. At this time, an interface 12 with a weak chemical bond is formed within the polysilicon layer. Then in a nitrogen (N2) atmosphere 700
Annealing is performed at a temperature of 900°C to 1200"C for an appropriately determined time. For example, according to the inventor of the present application, it has been confirmed that a sufficient effect can be obtained when the temperature is 900°C or more and the time is 30 minutes or more. .

The grains are realigned at the interface 12 by the hardening annealing, resulting in a chemically strong interface that will not be attacked by an alkaline solution. It was also confirmed that if the annealing is performed, the cavity can be eliminated even if there is a cavity at the interface 126).

On the other hand, the above-mentioned annealing does not require a processing temperature higher than the melting point of the silicon substrate (approximately 1320° C.), so it has the advantage of matching the daleins and strengthening the chemical bond at the interface without melting the substrate.

After the above-mentioned annealing, flattening is performed by polishing as in the conventional method. In this case, since the interface within the polysilicon has already been chemically strengthened, there is no formation of a hole indicated by reference numeral 11 in FIG. 2 fbl, and flattening as shown in FIG. 1 tel is achieved. Further, the present invention has the advantage that the angle θ shown in FIG. 2 (al) is 9.
Since flattening can be achieved even if a cavity remains in the polysilicon at a temperature of 0 degrees or less, it can be implemented regardless of the shape of the U-groove.

Note that the temperature and time for annealing are not limited to those in the above embodiments, but are appropriately set at a temperature below the melting temperature of the silicon substrate.

(7) Effects of the Invention As explained in detail above, according to the present invention, in the method of forming an insulating separation layer using a U-groove, the U-groove (7) is filled with polysilicon and the surface is flattened regardless of its shape. Since this can be achieved, the insulation distribution 11 of the semiconductor element formed on the substrate can be ensured, and the flat surface can also prevent disconnections during the wiring process, leading to higher integration and reliability of semiconductor devices. This has a great effect on the yield rate in equipment manufacturing.

[Brief explanation of the drawing]

Figures 1, 2, and 3 show insulation 111 by the U groove.
FIG. 1 is a cross-sectional view of a main part of a semiconductor device showing a layer forming step. ■-Silicone base 4 anti, 2, 5-3i02N, 3-5
i3N1 film, 4-U groove, 6-polysilicon, 11-su, 12-interface (8) Φ -〇Figure 3 C 174-0

Claims (1)

[Claims] A method of forming an insulating separation layer is to form a trench with a U-shaped cross section in a semiconductor substrate, and fill the trench with an insulating material.An oxide film is formed on the trench wall surface, and then the insulating material is grown to form a line trench. a step of annealing at a temperature below the melting point of the substrate after burying it;
A method of manufacturing a semiconductor device, comprising the step of: next removing an insulator on the substrate to planarize it;