JPS60114946A - File memory access method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an access method in a file memory such as a disk memory or a magnetic tape.

In general, when image data is stored in a disk memory device, the storage density is on the order of microns per pitch for both track and linear density, and the readout error rate is as high as about 104. Therefore, access errors occur frequently when accessing such file memory.

Conventionally, in consideration of the high incidence of access errors, error detection codes for cyclic redundancy checks (CRC) are added to address information stored in tracks and sectors of file memory, and each access information is The method is to perform a CRC check. However, if such a check method is used, the incidence of errors when reading the CRC information itself becomes quite high, making it difficult to perform a complete check. Further, in the CRC, only error detection is performed, but error recovery cannot be performed, and information reading attempts are repeated.

The present invention has been made in consideration of the above points, and provides a file memory access method that effectively suppresses the occurrence of access errors and increases the operational reliability of the file memory.

Seal bottom An embodiment of the present invention will be described in detail below.

In the file memory access method according to the present invention, address information is registered in the file memory together with necessary image data in the form of an image pattern, and pattern recognition of the address image information read out at the time of access is performed. We take measures to confirm the address by: In other words, in the present invention, instead of using conventional encoded address information to check for a complete match of the address information read out at the time of access, highly redundant image pattern information is used to detect errors that occur at the time of access. In this case, the recognition method that judges the degree of similarity between the read pattern and the standard pattern based on the size of the distance allows for changes in address information due to read errors, that is, changes that appear as partial deformations of the image pattern. It is intended to make it possible.

FIG. 1 shows one method for storing address image information on a file memory. Here, each pattern information "1" is written, for example, by a pit in each of the first to third pattern areas P], -P3 on the track T of the disk memory.

Address image information r123J is registered by storing one digit of address r2J and r3J, respectively. In the figure, It, I2. I3 each indicates an image restored on the two-dimensional memory. Furthermore, in the present invention, if a combination of numbers is used as the address image information, the precision of pattern recognition will be increased, so even if there is some damage to the address image information storage part of the file memory, the address check can be performed. You will be able to do it effectively.

FIG. 2 shows an example of a circuit configuration for specifically implementing the file memory access method according to the present invention. In the configuration shown in the figure, first, the DA converter 2 receives a coded address signal output from the servo controller 1.
The head 4 of the tisf memory device, which is drive-controlled via the servo driver 3, reads address image information stored in advance for each image data while detecting index and sector signals from the tracks on the disk 5. let The read address image information is sent to the buffer memory 7 via the amplifier 6, where image information for one digit of each address is accumulated.
The accumulated image information for one digit of each address is given to the pattern recognition circuit 8. The pattern recognition circuit 8 performs pattern recognition on the applied image information and sends a pattern code signal resulting from the recognition to the comparator 9. Further, the address signal held in the servo controller l is applied to the comparator 9 via the multiplexer 10, and the address signal A output from the multiplexer 10 and the pattern code output from the pattern recognition circuit 8 are input to the comparator 9. A comparison is made with signal B, and when the two human power signals A and B are equal, a match output is given to the file memory controller 11.

In response to the coincidence signal, the file memory controller 11 sends an address write signal to the buffer memory 7 to store image information for one digit of the next address read by the head 4. The file memory controller 11 can check the address image information read from the disk 5 by performing the above operations for all digits of the address image information and checking whether the comparator 9 matches each digit. Become.

FIG. 3 shows another embodiment of the present invention, in which an area A2 where address information based on a code is stored is provided in front of an area A1 where address image information based on an image pattern is stored, and a code code is provided within the area A2. The converted address information CI and CRC code information C2 are written.

Note that the area in the figure shows a storage unit for image data.

However, in this case, a CRC check is performed first when reading the image data, and pattern recognition of the address image information is performed only when an error occurs, which increases the processing time due to pattern recognition of the address image information described above. In order to deal with such cases, an address check based on pattern recognition of address image information can be used as a backup for the CRC check.

FIG. 4 shows another circuit configuration example for concretely implementing the present invention. In this case, in order to absorb the processing time in the pattern recognition circuit 8, a page memory 12 for image data and its memory An introler 13 is prepared separately, and the file memory controller 11 issues a memory access permission signal to the memory controller 13 only after address matching is confirmed to enable processing on the page memory 12. It is also possible to perform pattern recognition of address image information.

Furthermore, FIG. 5 shows another example of the circuit configuration, in which ten buffer memories 70 to 7 are provided on the output side of the amplifier 6.
9 are provided in parallel, and on the output side of each buffer memory as a pattern recognition circuit 8', there are similarity calculation units 80 to 89 that calculate the similarity with each number from 0 to 9, and each calculated similarity. A pattern determination section 90 is provided which supplies the pattern code signal B of the number with the highest degree of similarity to the comparator 9, and limits the patterns that can be used for address image information to only numbers, and image information for one digit of each address and O to 9 are provided. The pattern recognition speed can be increased by performing pattern recognition in parallel with the numbers up to.

As described above, in the file memory access method according to the present invention, address information is registered in the file memory together with necessary image data in the form of an image pattern, and pattern recognition of the address image information read out at the time of access is performed. This method takes a method to confirm the address by checking the address at the time of access, effectively suppressing the occurrence of errors, and greatly improving the operational reliability of the file memory. It has the excellent advantage of b.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a method for storing address image information related to a file memory access method according to the present invention;
FIG. 2 is a block diagram showing an example of a circuit configuration for implementing the present invention; FIG. 3 is a block diagram showing an example of the address information storage method according to the present invention; FIG. Fifth
FIG. 3 is a block diagram showing other examples of circuit configurations for concretely implementing the present invention. 1... Servo controller 2... DA converter 3
...Servo driver 4...Head 5...Disk 6...Amplifier 7,70-79...Novetsu Fa Memo 1 8゜8'...Pattern recognition circuit 9...
Controller (Rator 10...Multiplexer 11...
・File memo 1 controller 12...Page memory 13...Memo 1 controller 80-89・
...Similarity calculation unit 90...Pattern judgment unit negative '5 /Description Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] The address information is registered in the file memory together with necessary image data in the form of an image pattern, and the address is confirmed by recognizing the pattern of the address image information read at the time of access. File memory access method.