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JPS60105262A - thick film integrated circuit - Google Patents

thick film integrated circuit

Info

Publication number
JPS60105262A
JPS60105262A JP58212748A JP21274883A JPS60105262A JP S60105262 A JPS60105262 A JP S60105262A JP 58212748 A JP58212748 A JP 58212748A JP 21274883 A JP21274883 A JP 21274883A JP S60105262 A JPS60105262 A JP S60105262A
Authority
JP
Japan
Prior art keywords
thickness
dielectric layer
screen printing
squeegee
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58212748A
Other languages
Japanese (ja)
Inventor
Shunsuke Sasaki
駿介 佐々木
Mitsuto Miyazaki
光人 宮崎
Kazuo Arisue
有末 一夫
Kiyoshi Sawairi
澤入 精
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58212748A priority Critical patent/JPS60105262A/en
Publication of JPS60105262A publication Critical patent/JPS60105262A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/705Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thick-film circuits or parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To prevent the change of thickness of screen printing on the formation of a thick-film resistor through a dielectric by forming a dielectric layer in a region, in which a squeegee is not deformed by a thickness gap through the dielectric layer, while being adjoined to a circuit element running parallel with the direction of movement of the aqueegee on screen printing. CONSTITUTION:Patterns for dielectric layers are formed where adjacent to a circuit element such as a resistor, and these patterns are shaped in region in which a squeegee is not deformed. The dielectric layers such as dielectric layers 10 are formed on regions in which the deflection of the nose of the squeegee for screen printing is not changed while being adjoined to both side surfaces of a resistance film in order to display an effect by a minimum area required in a pattern for a dielectric layer 1 positioned at the lowe position of the resistor, and the deviation of the change of thickness of the resistor is minimized. Accordingly, the change of film thickness by the inequality of thickness of the dielectric layers shaped as the boundary layers of the circuit element in each layer in the formation of films through screen printing of a thick-film integrated circuit onto a circuit part can be prevented, and the usage of the material is mininized and the deviation of the quality of end products is inhibited easily at a minimum.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は厚膜集積回路に関する。[Detailed description of the invention] Industrial applications The present invention relates to thick film integrated circuits.

従来例の構成とその問題点 近年、厚膜集積回路は産業用および民生用の機器のあら
ゆる分野に用いられており、それらは高集積化(多層構
造)と高精度化(ファインパターン)ケねらいとして製
造技術の高度化の傾向となっている。そのため、回路形
成における膜の仕上がりとそのバラツキが問題となる。
Conventional configurations and their problems In recent years, thick film integrated circuits have been used in all fields of industrial and consumer equipment, with the aim of achieving high integration (multilayer structure) and high precision (fine patterns). As a result, manufacturing technology is becoming more sophisticated. Therefore, the finish of the film and its variations in circuit formation become a problem.

従来の回路形成方法は第1図および第2図に示すように
ベース材としての回路部品2の表面に誘電体層1(図中
破線で囲まれている領域)、導体3.抵抗4,5゜6.
7.オーバーコート9が順次印刷・乾燥・焼成の製造工
程を繰り返して形成される。誘電体層1が回路部品2上
に形成されているのは、回路部品2が例えばチタン酸バ
リウムから成るコンデンサや、厚膜回路の多層構造から
成る部品であり、各層の回路素子がお互いに干渉しない
ように境界層として設けられているためである。したが
って、この誘電体層1の形成に際しては多層化すればす
る程出来るたけ小面積で形成することが省材料となり望
せしい。
As shown in FIGS. 1 and 2, the conventional circuit forming method includes a dielectric layer 1 (area surrounded by a broken line in the figure), a conductor 3. Resistance 4.5°6.
7. The overcoat 9 is formed by sequentially repeating the manufacturing steps of printing, drying, and baking. The dielectric layer 1 is formed on the circuit component 2 because the circuit component 2 is, for example, a capacitor made of barium titanate or a component made of a multilayer structure of a thick film circuit, so that the circuit elements in each layer do not interfere with each other. This is because it is provided as a boundary layer to prevent this from occurring. Therefore, when forming the dielectric layer 1, it is desirable to form the dielectric layer 1 in as small an area as possible as the number of layers increases, as this will save material.

厚膜回路形成における印刷方法はスクリーン印刷が一般
的であシ、特に厚膜抵抗の形成には数多いプロセスの変
数要因ケいかにバラツキを少なくして最終製品の品質の
偏差を最小におさえるかが問題である。特にその中でも
基板の不均一による膜厚の変化が開票となる。それを第
3図で説明する。基板の不均一は反り、ねじれ、厚み、
基板上の膜形成状態と要因かあるが、第3図は単純に基
板の厚み変化か膜19に変化をもたらすことを示す。
Screen printing is the most common printing method used to form thick film circuits, and the problem with forming thick film resistors in particular is how to minimize variations in the quality of the final product due to the large number of process variables. It is. Among these, changes in film thickness due to non-uniformity of the substrate are particularly important. This will be explained with reference to FIG. Unevenness of the substrate is caused by warping, twisting, thickness,
Although this may be due to the state of film formation on the substrate or other factors, FIG. 3 shows that the film 19 changes simply due to a change in the thickness of the substrate.

第3図aに示す標準1阜さの基板1oに対して基板が厚
くなると、第3図すに示すようにスキージ11が変形し
てスキージ11の先端がたわみ、それに応じたアタック
角が低くなり、その結果として膜厚が)ソ<印刷される
。そして、それはより低い抵抗([になる。それたけに
多層化構造を構成する厚膜形成においては、常に膜面ケ
平坦にしておく必要がある。このことから第1図に示す
誘電体層2のパターン構造が1要であることが明らかで
ある。
When the substrate becomes thicker than the standard 1-height substrate 1o shown in FIG. 3a, the squeegee 11 deforms and the tip of the squeegee 11 bends as shown in FIG. , as a result, the film thickness is printed as ). And, it becomes lower resistance ([. It is clear that the pattern structure is essential.

第4図および第5図は第1図の誘電体層2のパターンと
各部位での1卑みを示してお9、図中矢印の方向でスキ
ージが移動するときに印刷面が変化していることを示す
。し/もがって、このような変化があると第1図にある
抵抗4,5,6.7&よいずれも印刷条件が最適に設定
されていても印刷面の厚み変化で膜厚が変化することが
前述し/ζ説明理由から明らかである。特に抵抗6,7
はスキージ方向と平行して抵抗の長さ方向のツキターン
が形成されており、抵抗の両側には抵抗4,6のように
引き出し電極がないため誘電体層2の厚み寸法の変化と
その影響が大である。
FIGS. 4 and 5 show the pattern of the dielectric layer 2 in FIG. 1 and the 1-substance at each location.9 The printed surface changes when the squeegee moves in the direction of the arrow in the figure. Show that there is. If such a change occurs, the film thickness will change due to changes in the thickness of the printed surface, even if the printing conditions are optimally set for resistors 4, 5, 6, 7, etc. shown in Figure 1. It is clear from the reasons explained above/ζ. Especially resistance 6,7
A longitudinal turn of the resistor is formed parallel to the squeegee direction, and there are no extraction electrodes on both sides of the resistor like resistors 4 and 6, so changes in the thickness dimension of the dielectric layer 2 and its effects are It's large.

発明の目的 本発明は、誘電体を介する厚膜抵抗の形成におけるスク
リーン印刷による厚み変化を防止するとともに誘電体の
使用面積を最小にして効果ならしめることができる厚膜
集積回路を提供することを目的とする。
OBJECTS OF THE INVENTION It is an object of the present invention to provide a thick film integrated circuit that can prevent thickness changes due to screen printing in forming a thick film resistor through a dielectric, and minimize the area used for the dielectric. purpose.

発明の構成 本発明は、上記の目的を達成するため、抵抗等の回路素
子と近接する位置に誘電体層のパターンを形成し、かつ
それらはスキージ変形を起こさない領域に形成したこと
を特長とするものである。
Structure of the Invention In order to achieve the above object, the present invention is characterized in that dielectric layer patterns are formed in positions close to circuit elements such as resistors, and they are formed in areas where squeegee deformation does not occur. It is something to do.

実施例の説明 以下本発明を実施例の図面にもとづき詳細する。Description of examples The present invention will be described in detail below based on drawings of embodiments.

第6図および第7図は本発明の一実施例を示しておυ、
第1図に示す抵抗6,7の下位置とじである誘電体層1
のパターンケ必要面積最小で効果ならしめるように抵抗
6,7の抵抗膜両側面に近接してかつスクリーン印刷の
スキージ先!H11のたわみ変化を起こさない領域に誘
電体層10ケ形成し、抵抗4,5,6.7の厚み変化の
偏差を最小におさえている。
Figures 6 and 7 show an embodiment of the present invention.
Dielectric layer 1 which is the bottom binding of resistors 6 and 7 shown in FIG.
The pattern is placed close to both sides of the resistive film of resistors 6 and 7 and at the tip of the screen-printed squeegee so as to minimize the area required and achieve the desired effect! Ten dielectric layers are formed in the area where no change in deflection occurs in H11, and the deviation in thickness change in resistors 4, 5, and 6.7 is minimized.

発明の効果 以上述べたように本発明によれば、回路部品上への厚膜
集積回路のスクリーン印刷による膜形成で各層の回路素
子の境界層として形成する誘電体層の厚み不均一による
膜厚の変化を防止でき、かつその材料使用ケ最小で最終
製品の品質の偏差を最小におさえることが容易となる等
の効果が得られる。その結果、高集積化が進み増大して
いる厚膜集積回路として非常にコストパーフォマンスに
優れて複雑なスクリーン印刷技術と技能を用いることな
く、均一な品質の製品が提供できる利点を有する。
Effects of the Invention As described above, according to the present invention, the film thickness is reduced due to non-uniform thickness of the dielectric layer formed as a boundary layer between circuit elements in each layer when a thick film integrated circuit is formed on a circuit component by screen printing. Effects such as being able to prevent changes in the quality of the finished product and making it easy to minimize deviations in the quality of the final product by minimizing the amount of material used are obtained. As a result, as thick film integrated circuits are becoming more and more highly integrated, they are extremely cost-effective and have the advantage of being able to provide products of uniform quality without using complicated screen printing techniques and skills.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の厚膜集積回路の平面図、第2図はそのA
−へ′線における断面図、第3図a、bは基板厚さとス
キージ状態ケ表わした説明図、第4図は同回路における
誘電体層パターンの平面図、第5図a 、 b 、、 
cはその誘電体層の各部位の厚み状態ケ表わした断面図
、第6図は本発明による誘電体層パターンの平面図、第
7図a、b、cは同誘電体層の各部位の厚み状態を表わ
した断面図である。 1・・・誘電体層、2・・・・・回路部品、3・・・1
体、4.5,6.7・・・・・・抵抗、8・・・回路部
品引き出し電極、9・・・・オーバーコート、10・・
−誘電体層。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 G 第2図 第3図 −b 第4図 第5図 (L /A IA’ b IBIB’ 第7図 α2A2A′ b282B′ G2G’ 2C’
Figure 1 is a plan view of a conventional thick film integrated circuit, and Figure 2 is its A.
3A and 3B are explanatory diagrams showing the substrate thickness and squeegee condition, FIG. 4 is a plan view of the dielectric layer pattern in the same circuit, and FIGS.
Fig. 6 is a plan view of the dielectric layer pattern according to the present invention, and Fig. 7 a, b, and c are cross-sectional views showing the thickness of each part of the dielectric layer. FIG. 3 is a cross-sectional view showing the thickness state. 1... Dielectric layer, 2... Circuit component, 3... 1
Body, 4.5, 6.7...Resistance, 8...Circuit component extraction electrode, 9...Overcoat, 10...
-Dielectric layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure G Figure 2 Figure 3-b Figure 4 Figure 5 (L /A IA' b IBIB' Figure 7 α2A2A'b282B'G2G'2C'

Claims (1)

【特許請求の範囲】[Claims] ベース材上にあらかじめ形成した誘電体層上にスクリー
ン印刷により導体接続回路パターンと抵抗コンデンサ等
の回路素子を一層もしくはそれ以上の多層で構成した厚
膜集積回路であって、スクリーン印刷時のスキージ移動
方向と平行する回路素子に近接して、かつ誘電体層を介
する厚みギャップによりスキージ変形を起こさない領域
に誘電体層全構成したことケ特徴とする厚膜集積回路。
A thick film integrated circuit that is constructed by screen printing conductor connection circuit patterns and circuit elements such as resistive capacitors in one or more layers on a dielectric layer formed in advance on a base material, and the squeegee movement during screen printing. A thick film integrated circuit characterized in that the dielectric layer is entirely constructed in a region close to a circuit element parallel to the direction and where squeegee deformation does not occur due to a thickness gap through the dielectric layer.
JP58212748A 1983-11-11 1983-11-11 thick film integrated circuit Pending JPS60105262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58212748A JPS60105262A (en) 1983-11-11 1983-11-11 thick film integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58212748A JPS60105262A (en) 1983-11-11 1983-11-11 thick film integrated circuit

Publications (1)

Publication Number Publication Date
JPS60105262A true JPS60105262A (en) 1985-06-10

Family

ID=16627766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58212748A Pending JPS60105262A (en) 1983-11-11 1983-11-11 thick film integrated circuit

Country Status (1)

Country Link
JP (1) JPS60105262A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01316991A (en) * 1988-06-17 1989-12-21 Nippon Chemicon Corp Manufacture of thick film integrated circuit
JPH0470765U (en) * 1990-10-31 1992-06-23
EP1629509A4 (en) * 2003-05-30 2009-10-21 Motorola Inc Polymer thick film resistor, layout cell, and method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01316991A (en) * 1988-06-17 1989-12-21 Nippon Chemicon Corp Manufacture of thick film integrated circuit
JPH0470765U (en) * 1990-10-31 1992-06-23
EP1629509A4 (en) * 2003-05-30 2009-10-21 Motorola Inc Polymer thick film resistor, layout cell, and method

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