JPS6455794U - - Google Patents
Info
- Publication number
- JPS6455794U JPS6455794U JP15132987U JP15132987U JPS6455794U JP S6455794 U JPS6455794 U JP S6455794U JP 15132987 U JP15132987 U JP 15132987U JP 15132987 U JP15132987 U JP 15132987U JP S6455794 U JPS6455794 U JP S6455794U
- Authority
- JP
- Japan
- Prior art keywords
- headphone
- headphone jack
- line output
- detecting
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 1
- 230000005236 sound signal Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Headphones And Earphones (AREA)
- Stereophonic Arrangements (AREA)
Description
第１図は本考案の第１の実施例のブロツク図、
第２図は第２の実施例のブロツク図、第３図は従
来の方式例のブロツク図である。
１……ヘツドホンジヤツク、２……リレー、３
……ヘツドホンアンプ、４……ライン出力端子、
５……マイクロコンピユータ、６……リレードラ
イバ。
FIG. 1 is a block diagram of the first embodiment of the present invention.
FIG. 2 is a block diagram of the second embodiment, and FIG. 3 is a block diagram of a conventional system. 1...Headphone jack, 2...Relay, 3
...Headphone amplifier, 4...Line output terminal,
5...Microcomputer, 6...Relay driver.
Claims (1)
まれたことを検知する第１の手段と、該第１の手
段の検知信号により音響信号のライン出力を停止
する第２の手段とを有するヘツドホンジヤツク付
きの音響機器。 A headphone jack equipped with a first means for detecting that a headphone plug is inserted into the headphone jack, and a second means for stopping line output of an audio signal based on a detection signal of the first means. Sound equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15132987U JPS6455794U (en) | 1987-10-01 | 1987-10-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15132987U JPS6455794U (en) | 1987-10-01 | 1987-10-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6455794U true JPS6455794U (en) | 1989-04-06 |
Family
ID=31425276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15132987U Pending JPS6455794U (en) | 1987-10-01 | 1987-10-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6455794U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7286415B2 (en) | 2004-11-10 | 2007-10-23 | Samsung Electronics Co., Ltd. | Semiconductor memory devices having a dual port mode and methods of operating the same |
| US8547776B2 (en) | 2000-12-20 | 2013-10-01 | Fujitsu Semiconductor Limited | Multi-port memory based on DRAM core |
-
1987
- 1987-10-01 JP JP15132987U patent/JPS6455794U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8547776B2 (en) | 2000-12-20 | 2013-10-01 | Fujitsu Semiconductor Limited | Multi-port memory based on DRAM core |
| US7286415B2 (en) | 2004-11-10 | 2007-10-23 | Samsung Electronics Co., Ltd. | Semiconductor memory devices having a dual port mode and methods of operating the same |
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