JPS5962968A - Constitution controlling system of control station in multicomputer system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides that a plurality of computers (common) I! J.
The present invention relates to a multi-subtraction four-machine system for controlling multiple input/output devices.

Here, "configuration planes 11111 j and 6" 1 are connected to the common node ("") of multiple control stations, then one fC is the master surface /
If the master station fails, one of the remaining standby control stations (monitor spoon station) will take over as the master station in place of the current master station. ,
This means controlling the control station to perform overall management of the common bus.

Here, "integrated management" refers to all control or U management related to the use of the common bus.In a system where a total of 3V devices occupy the common bus and control specific input/output devices, Controlling the occupancy of the common bus is a major benefit.

The control station that supervises the T1 is to monitor the control station that can act as the master C8T in place of the master C8 'I' when it fails. Idol C8T, !: Nickname "j."

[Prior art]

One form of the common bus is a loop-shaped transmission line.

In recent years, proposals have been made in which loop-shaped transmission lines are multiplexed to improve the reliability of the transmission lines themselves.

In addition, a plurality of C8Ts are connected to the loop-shaped transmission line,
Master any one CS 'I', flD'(r
Monitor CS 'l'' or idle C8T, C8
By controlling the configuration of the C8T, even if a specific C8T goes down, the system connected to the loop transmission path is prevented from going down.

Conventionally, the CST 1jif-l9 machines were connected to a common bus independently, and each C8'l'l<t, independently.
C S T .

"Determine monitor C8'l'," it said.

That is, by monitoring the (, () signals on the monitor C8'L'tJ, , Lll bus
If it is determined that the C8T has failed, the own C8T is made the master CRT and centrally manages the common bus. In this case, monitor C8T is 2
If there are more than one monitor, which monitor C8T is the master C
In many cases, it is decided in advance whether the monitor C8T will become the master C8T, but managing this is complicated, and two monitor C8Ts may try to become the master C8T at the same time.

In addition, even if the master C8T itself is not malfunctioning, if the monitor C8T loses the signal on the 311 bus, it will assume that the master (-N SIl+) has failed and the monitor C8T There are cases where it tries to become 4.

Conventionally, attempts have been made to prevent such inconveniences by providing a special signal line between the C8T and the signal line, but the control becomes complicated. C,
Reliable configuration control of CS 'l'' has been difficult.

[Purpose of the invention]

An object of the present invention is to select one of a plurality of C8Ts on a common bus.
The purpose of the present invention is to provide a control station configuration control system in a multi-computer system that reliably controls only one CAT as a master C8T and other CATs as monitor C8T or idle C8'l'.

[Summary of the invention]

The features of the present invention are that each CAT is connected in correspondence with a plurality of computers that control input/output devices connected to a common bus, and that the monitor C8T is made the master csT by a command from the corresponding computer; Each C3Tii:'lReports the state of the C8T itself and the state of the signals on the common bus to the corresponding computer, and information about which C8T is the master C8T, is shared by each machine. Each computer stores and updates it in a common memory used for
This is to perform configuration control by referring to fill information.

According to the present invention, since configuration control information is managed in one common memory, two or more C8Ts will not become master C8Ts by mistake.

When the divider connected to the master CAT receives a failure report of the CS 'El' self-H from the master (ST), it refers to the configuration control information in the common memory and determines whether the C8T connected to itself It recognizes that it has become the master C8T, immediately rewrites it to the idle C8T, and reports to other computers that the cST is down.

When the computer receives this report, it refers to the configuration control information in the common memory and changes the C8T connected to itself to the monitor C5.
In this case, change this to master C8T and issue a command to the CST connected to yourself to become master C8T.

In this case, since the common memory cannot be accessed by the two H1'' initial machines at the same time, reliable configuration control is possible.

[Embodiments of the invention]

FIG. 1 shows an embodiment of a multicast computer system to which the present invention is applied.

In FIG. 1, reference numerals 1 to 3 indicate controllers (hereinafter referred to as CI U), which have a built-in program and control a plurality of input/output devices 16 to 18 by executing this program.
+111. 4 is a common memory commonly used by each of the CPUs 1 to 3, and as described later, configuration control information of the C8T is stored in this memory. 5-7 are each CP
U1~3 are common buses, here they are stations (hereinafter referred to as ST) that connect to the loop-shaped transmission line 11.12 in the opposite direction, and 8~1O are the integrated control functions of the loop-shaped transmission line 11.12. 'eWaiting for the control station (c
s'r). C3T8-10 each have connection legs 80
90.100 = connected to the corresponding CPUI, 2.3. 13 to 15 are input/output devices (hereinafter referred to as I10)
16 to 18 (hereinafter referred to as MST) to connect the loop-shaped transmission lines 11 and 12. 19 is each CPUI.

C8 as described later in the common signal line connecting between 2 and 3.
Used when controlling the T configuration. Each MS'I" has a configuration that stores which CPU's request the Ilo connected under itself should service, and a function to break the loop based on commands from the C8T. The request from which CPU should be serviced is decided when the CPU to be serviced is not determined (this state is called the neutral state), and the MST receives the occupied Yasugi from the CPU. This occupied state is released when a command is received from the occupied CPU, or when a command is forcibly released from another non-occupied CPU. .

This occupancy request command is sent to C0NC-R8V (Connec
t &几6s6rve) command, C0NC-FRii'zE (Connect &
Free) -z 77 de, command to forcibly release possession '5f: RE, SET -I'f also EE (LLe
set & pree) -t -q command. M
When a command for Ilo connected under ST is sent from the CPU, if the command is from a CPU other than the CPU occupying 10, the ST will RESE'l it.
'-Unless it is a FREE command, the command will not be accepted. By providing this mechanism, Ilo connected to the loop bus via the MST can be appropriately shared by multiple CPUs. That is, even if an input/output request is erroneously issued from the user program of CPU 2 to l1016 which is occupied by the CPU, l1016 will not cause any disturbance in the processing currently being serviced. CI) Since the I/O request from U2 is rejected by the MAT.

Each CPU manages the connection state of Ilo, and a table for managing the connection state of Ilo is stored in the memory of each CPU. When the operating system (OS) of each CPU needs to switch the occupation state of Ilo, it contacts the CPU that is currently occupying Ilo and sends a CONC.
Request to issue F-EE command. The CPU that received the request is C0NC-FIIEE =ff cloak'f
r:Issued to iI10, released the possession, and requested eP
Returns a response to U stating that the possession was released at [7]. C0NC after receiving the requester's response.
- Issue all ft5V commands and occupy the l10k. J
When it is detected that the CPU occupying the M4110 is stopped or not operating normally, the requesting CPU issues the R,ESET-Fil,EE command to check the occupied state of the I10. After canceling C0NC・R,
Issue the SV command and occupy the cough I10'a-occupy. The management table in each CIU is rewritten in accordance with the transfer of the occupation of Ilo, but this management table may be placed in the inter-CPU shared memory 4.

In order to increase the reliability of the system, multiple CSTs are connected to the same loop. If there is only one C8T, that C8T may fail, but if something goes wrong at the stations on both sides of the C8T, control information may not be transmitted from the C8T to the other stations. This is because the loop will no longer function. If these multiple CS i' control loops independent of each other, they may perform contradictory control [7], so only one of the multiple CS i'r can be given the authority to control the loop. . This authority f puts the empowered C8T in Master mode (7)
It is called CS '1' (master C3T). other C
8T is a loop status monitoring mode (Monite).
R mode) or just passive Ht production mode (1dle mode).
C3Tf in Olli ter mode: Monitor C
It is called ST. MS' only from master C8T
II', ST can be commanded to turn back the loop, and can also be used to switch between loop 11, which is normally used for data transmission with CI3, IJ, and Ilo, and loop 12, which is used to transmit loop monitoring signals, etc. Can give commands.

Master C8T sends a supervisory signal to the loop.

The monitor CAT monitors the monitoring signal sent from the master C8T, and when this monitoring signal cannot be detected for a certain period of time, it determines that the master C8T has failed, and the CPU
, and reports the abnormality of the master C8T. When master C8T detects loop signal disconnection,
9 loop changes of duplicated loops (loop 11 and loop 11)
12). If you can continue operation with this, you can leave it as is, but if you cannot step-up, you can change the loop configuration information (which stations are connected in what mutual relationship; topology) stored in your C8T. Based on this, each station is instructed to perform roofback operation (loop return) f:. Loop configuration information 18 When C8T is commanded by the CPU to become the master, it is transferred from the CPU to C8'l', but before being commanded to become the master,
It may be transferred to each C8T in advance. When the master C8T detects a disconnection even after the master C8T has checked all sections of the loop control, and when the monitor C8T detects its own abnormality, the master C8T sends an interrupt to the CPU. Kake master C8
Transition from T to idle C8'v. C3Tfd in the idle C8T does not actively work on the loop, and does not monitor the state of the loop yet. Idol CS T It, Ishi Monitor C8T is C
When it receives a command from the PU to become a master (this command is called an all-master command), it becomes a master and obtains 111 loops.

In addition, the reset command from the master C3Tr, t, CI)U is transferred to the monitor cs'r. FIG. 2 shows this state transition. C8T
When the power is turned on, the CPU goes into idle mode.
When the receiver receives the C0NC-11 and SV command from the controller, it shifts to monitor mode. This is to avoid unnecessary error handling due to differences in power-on sequence when the system is first started. That is, when the power of the C8T is first turned on and the C8T is placed in monitor mode, the monitor C8T starts monitoring the loop. Between this timing and the time when master mode C8T is defined (C8T in master mode is defined by one -C in command from the CPU, CI), before U is powered on and becomes capable of operation T'jJ. C in master mode for
The C8T in the monitor mode will determine that there is an abnormality in the loop (an abnormality in the master mode C8T) during the period in which ST does not exist.
This problem does not occur if there is a shift to the monitor mode based on a command from the computer.

FIG. 3 shows the transition of the operation mode of the loop bus.

NL operation is a normal operation mode in which data is transmitted between the CPU and I10 on one side of the duplex loop (called the N0rnlal Loop), and on the other side (called the N0rnlal Loop).
This is called BL) to monitor the loop. During NL operation, if an abnormality is detected in NormaI T, oop, Cl in Back i, oop)
Data transmission between U and I10 takes place. No rnl
If both Back Lin6 (L1LOOI) and Back Lin6 become abnormal (for example, when both loops are disconnected) and the Loogo loop signal is no longer detected, the Master C8
T instructs each station to turn back the loop, so that a significant signal can be transmitted by going around the loop (loop connecting NOrllaILOOp and the turning point and Backl, □op and the turning point). Instructs all loop configuration control (loopback control). As a result, there is a significant signal that circulates around the loop bus, and the operation mode that functions as a loop bus is changed to T or B operation (L0
0 pBaCk operation), and the station at which the turnaround point has been reached is disconnected from the loop. Third
In the figure, the dashed arrow indicates the return command (lL) from CI)U to J1 normal operation for C8T in MaS16r mode.
, T, , DC command) is issued. The CPU commands the CST in MaSfer mode to shift to LB operation (SL
BC command). At this time, MaSfe
The C8T in the r mode is instructed as to the station that should be the turning point, but the CST in the M3st6r mode performs processing according to the stored loop configuration information.

The above operation will be specifically explained using the drawings.

Here, CP tJ l and CPU 1 connection C8T
8 will be explained as an example. C, tJJ2, 3 and C3
The same applies to T9.10.

FIG. 4 shows a block diagram of C3T8. C3T8 is a readout intelligence memory (OM) 8-2, which has a built-in microprocessor 8-11 microprogram.
]' FI memory (1, LAM) s-a, interrupt control LS I (PT (, 1U) 8-4, ko [1 signal 11i
l control LS 1 (IIDLC) 8-5, general-purpose human output control J, SL (PPI) 8-6, timer (PTM) 8
-7, and <-: Write down the contents of the interrupt from p 1
．． These are common interrupt registers 8-9.
Connected by US 8-8.

Furthermore, a multiplexer (MPXI3) 8-t selects between the monitoring signal 411 from the monitoring signal generator 8-11 and the data signal from the HDLC 8-5, which prompts data transmission.
2. Multiplexer (1'vH) 'vlPXA) 8-17, and a reverse multiplexer (Ml) XI)) 8-22, a detector 8-15 that detects signal disconnection of all multiple loops, and a Loop that issues selection commands to these multiplexers.
CON'l' 0L8-14, signal receiving circuit 8-20.
21, signal transmitting circuits 8-18 and 19. There is also a report register 8-27 for reporting to the connected G1 computer. Interrupt register 8-9 and report register 8-27
is connected to the CPU 1 via a connection line 80.

Using the above configuration, specific processing will be explained using FIGS. 5 to 9. Figure 5 shows the inside of C3TB.
It shows the process started by a command from the CPU 1 or by turning on the power of the C3T8. First of all, when the C3T8 is powered on,
Unconditionally shifts to IDLE mode and stores IDLE mode in AM8-3. In IDLE mode,
itself (LOOI) 11. It transitions to the pass state for 12. This is done by J, oop CTL 8-14 and multiplexer 8-17 or 8-22. Also C
When the command from P U 1 is MA, S position L command, RAM8-.
3, :t, oop t i(Norm31 J
, oop) and starts the monitoring signal-wait timer 8-7. Also, if the command from CPU1 is reset (Re56t), it will itself
Shift to ONITOIL mode, LOOpH, 12
i) Transition to ASS state. In addition, seven moves%1ASTE11. A timer 8-7 for waiting for a supervisory signal from C8'J' is activated. FIG. 6 shows an example of interrupt processing activated by an interrupt from the current loop. Here, current use means Normal], J during oop operation, and oop 1.
1. During Back LOOp operation, J, 001) l
I'll say 2 things. Interrupt e, Loop 11 or 12
The reception from l'1l is via multiplexer 8-13i.
) The LC8-5 receives the interrupt, and the interrupt from the LIDLC8-5 is received by the interrupt side #1.5I8-4 receives the reception interrupt to Mp U 8-t. This interrupt starts the interrupt processing program shown in FIG.
II-J, Monitoring signal wait timer 8-7' (i = restart and die. Also, this interrupt is HD?, 10 when CLSI failure occurs. If ST is MASTER, LOOI) 1
11 It was determined that the management of 12 could not be maintained, and ■yo00p
In contrast, it shifts to p3rs mode and shifts to IDLE mode. Furthermore, the own CS 'I' 8 MA is sent to the connected CPU1.
8TJfffl, late 11? Ji k report register 8
-27 cents and report.

FIG. 7 shows -II/ll of the current loop 11 or 12's 1d line disconnection check process g++. iK signal disconnection/D check is performed only by MASTEF (C8T), signal disconnection is detected by signal detection B'4B-15, and i is also detected by servant output side (
d41 Detected by reflecting it on the LSI status. Signal disconnection No rrnl lDuring operation (i, +oo
p t t ), the current loop is Back
Switch to LOOp (1100pl 2 ). The switching process is performed by switching multiplexer A3-17 with the Loop CTL 8-t4 (1) command.
, multiplexer I) 8-22 so that the signal is sent from multiplexer B8-12 to LOOP12. History Back LoOp (r3 L) L 2
In addition to sending a monitoring signal to NormBI J
, oop failure is reported to all CPUIs. When the signal is cut off, Ba
Ck l, if in oop operation, LOOpl 1
S'1. '5. '6.7 and zc3T13,14°15, l, oop Bac
Sends k command and shifts to I, oopB ack mode. Furthermore, 13ack l1oop j/% always C
Report to PU1. In addition, if the signal is cut off during LoopBack operation, it is determined that the LO calls 111 and 12 cannot be managed, and the connection CI) is sent to the own MA S T F.
, CAT Qive up k<4. Figure 8 shows an example of timeout processing within C8T.
AM8-3N self-memory cs'r mode is MONIT
When in OR mode, the other party's MAN setting (.

If the POL signal from mode C8T is not received within a predetermined period of time, this timeout occurs. If this timeout occurs, the other MASTER
It is determined that mode C8T has failed and is reported to CPU Ul via an interrupt. or[? , AM8-3 record 1. If the C8T mode is also the MASTEf mode, the monitoring signal sent by the own C3T8 will time out within a certain period of time, but if this timeout occurs, the own M
Report ASi"l rtcs'i" failure to CPUI.
DLE Move to E mode. FIG. 9 shows an example of processing when the means of communication between the own C8T and the CPU is interrupted. In this example, if the report to CPU1 is done using DMA (Direct Memo Access), LA
When an MA error occurs, it is assumed that the means of communication with the self (, 8T and connected CI) U has been interrupted, and the c S T in RAM 8-3 is
When the mode is MA S 1' ]=:IL mode, the mode is changed to III) L and E modes, and for L OOl), it is assumed to be PASS-like νM.

connected to roots °)/Q(16・~18) &;
It is possible for each J to be occupied by a separate CI) U, but is it also possible to have all 10 connected to the loop occupied by a CPU all at once? ) to sing. In order to perform this JL, from the CPU that occupies the loop all at once, send eoNe・l, 1 port, F, I to all I10 under the loop.
(CI that wants to issue a command and occupy a new loop)
C0NC・几SV from U to metalwork 10 of the loop
Issue a command? Go. At this time, the loop is in the 1.13 operating state, and Ilo is disconnected from the loop. 7 If ## is in the state, C0NC・几S■ for the corresponding ■10
Since the command does not arrive, only the I10 newly occupies the loop, and the lt-CPU no longer occupies it. In order to prevent this inconvenience, the CPU R12 memorizes whether or not the allocated Ilo was reported by an interrupt from C8T in MaSfer mode, and after returning the loop to normal operation (MaSfer C in ter mode
After issuing all the LBC commands to B'J')1
Issue the c o N C R8V command to 1 and ■10. In this way, Lp, the operation of the loop 'F
Regardless of +J, the loop is collectively occupied between each C and tl U, and the switching of occupation is 1 hF:.

Now, go to multi-computer system 1.
Four things are done on the CPU component side 6η1. For example, in Figure 1, if work A and 13°C have been executed at C1)tJl and 2.3, and work A is an important work for the entire Nostem, then CPU
caused an error and went down (when it was 7, the remaining CPUs 2 and 3
Business 13. In addition to C, Uj1' and L'C may also have no meaning as a whole system. In such a case, CPU 2-tc (CI) 0
Jλ(r): will not be able to take over the work Af that was being done in 1.In addition, all the resources occupied by the CPU that caused the error will be taken over!!Fb!y, I, -c, and other cptJs.
In order to avoid any disturbance or disturbance while carrying out the above three steps, CI) Ul must be stopped. This kind of processing is called CI) U configuration control. Also, C1)
Even if there is no abnormality in the CPU, the operation of a certain CPU may be stopped for reasons of system operation or operation.
The content of work being carried out within the company may also be changed. This is also called CI) U configuration control. When performing all such configuration control, MaSler 7-rd CS
I) When U performs configuration control such that U stops at result and 17, other surviving CIs I) Set C8T connected to the CPU connected to U to Mast6r mode. There must be.

This is because when the connected CPU is stopped, the C8T in Master mode cannot report loop abnormalities and cannot update the stored loop configuration information based on instructions from the CPU. It is from.

Also, from C8T in Ma8fer mode to C8'll'
The CPU that receives the notification that it is no longer able to maintain the MaSter mode issues a notification to one of the other CPUs to set the connected C 8 T as the MaSfer mode.

Due to CPU configuration control, C in 1ast6r mode
The 8T switch is one switch as shown in Figure 1O. In Figure 10 rcl) U's Kihi AL, J and 1, object Cl' U
The entire process is to stop the CPTJ and release the resources occupied by the CPTJ. ``CPU relocation'' means stopping the work that was previously being performed on that CPU,
This refers to the process of releasing the resource iT j'/F that was occupied by the task and starting a new task.

That's what "starting up the CPU" means! Stop at L (7 CI) Refers to the process of starting U and starting a new task. The processing flow when the CPU is turned off is shown in FIG. 1 and FIG. 12, respectively.

In FIG. 12, whether the loop is connected to Cl1lU or not can be determined by having a table as shown in FIG. 13, for example? = "4 can be found. In Figure 13, 31 is stored in the common memory (1M (4 in Figure 1), which is a shared memory between CPUs that can be commonly referenced from each CPU. This table is stored in the system memory. Total number of loop buses (with loop each bit O, l, 2...Th C l)
If bit 2 for loop 2 is 1, loop 2 is connected to CPU + 2, and if it is 0, loop 2 is set.
), U indicates an unconnected cow. Also, this table shows the C 8 T 'ft- M of F of other e PU
Also used when requesting aster mode. The CST module connected to the loop is Ma.
A diple having the same structure as that in FIG. 13 is used to determine whether it is in the ster mode. However, when managing MaSter mode c 8 T, MaS'er seventh card C
ST, % (represented by 171 In Fig. 13, the fact that there is only one bit in each column that is l'' in the table for each loop indicates the connection relationship between each loop and CI) U. Figure 14 shows that each loop has a Master
This indicates whether or not the mode cST is being set. It is used to establish an interlock so that two C8T "j5Ma'ster modes are not set at the same time. These tables When referring to table 'f', it is necessary to take an interlock so that it is not referenced by multiple CPUs at the same time.
nd S. F, '1. 'Take an interlock using commands, etc.

Next, FIG. 15 and FIG. 16 show configuration control of the CST based on reports from the CST side. In addition, Fig. 11.
In Figures 12 and 16, when sending a message to other CPUs to set the Master mode, there is a method for deciding who to contact. For example, from the connection information of the loop and CST in Figure 13, the method is Find CS'P, (1yc
S'r f: Among the connected CPUs, Cl)U is the target of disconnection.

By arbitrarily selecting one of the CPUs excluding the CPU that is currently stopped, the CPU is stopped. This is done by using the common signal line 19' in FIG. As mentioned above, this communication may be issued after selecting one CI), but the CPU that sends the communication to all CI) and receives the communication will win the first one. Its CP
Even if you set it to CST'kMaster mode connected to U, it will take 2 hours. However, in that case, M
C connected to CST which was in aSfer mode
PU must ignore this communication.

〔Effect of the invention〕

As described above, according to the present invention, each computer collectively manages the states of all C8Ts using a common memory and controls the configuration of each C8T, so that conflicts between modes of each C8T,
For example, if there are multiple C8Ts that collectively manage a common bus,
The inconvenience of causing an unmanageable state of the common bus is eliminated9
By performing reliable C8T configuration control 1114, it is possible to reduce simultaneity (reliability of the system).

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of a multi-computer system to which the present invention is applied, FIG. 2 is a diagram showing state transitions of C8T modes, FIG. 3 is a diagram showing transitions of loop bus operation modes, and FIG. FIG. 4 is a block diagram of an embodiment of CS 'l' used in the present invention, and FIGS. 5 to 9 are flowcharts used to explain the operation of FIG. 4. 1Q1ml'l:
FIG. 11 is a flowchart showing the processing when the CPU is disconnected (9) and the CPU is turned off. 13 is a flowchart showing the processing at the time of raising the configuration control i1 used to explain the operation in FIG. 12.
Figure 14 shows C8 in Master mode.
Fig. 15 is a flowchart showing an interrupt processing of the CPU connected to the C8T in MaSter mode, and the 16th figure is the master CS not mode
Interrupt processor J'! of the CPU connected to T! 1 (il- There is a flowchart shown. 1-3... Computer, 4... Co-system 11" Memory, 8-1
0...Control station (Cs']"),
11.12...Loop-shaped transmission line (common bus), so,
90゜ㅅ 1 口■ 2nd ward Komasodo No. g Oral sound Fig. 19 Fig. 70 hole, Fig. 11 c, rume cut AIL ox〉 Perforation t, fl K 13 Fig. 14-mouth 1S Fig. Mo-5te tot -Do m1 SeasonFushirishiI'R-"7-1st diagram ■U Hitachi University University Mika-cho 5-2-1 Hitachi, Ltd. Omika Factory 0 Inventor Masao Sueki Hitachi University University Mika-cho 5-2 No. 1 Inside the Omika Factory, Hitachi, Ltd. Author: Keiji Hayashi 5-2-1 Hitachi, Ltd. Omika-cho No. 1 Inside the Omika Factory, Hitachi, Ltd. Author: Ken Onuki 5-2-1, Hitachi, Ltd. Inumika Factory, Hitachi, Ltd. Author: Toshiyuki Ide, 5-2-1 Hitachi Daimika-cho Omika Factory, Hitachi, Ltd. Author: Sadao Mizokawa, 5-2-1 Hitachi Daimika-cho Hitachi, Ltd. Inside the Omiga factory

Claims (1)

[Claims] 1. A plurality of total η machines connected to the first machine of the plurality of sides
A common memory commonly used among machines, a common bus connecting the plurality of computers, and a common memory connected to the common bus and the H1
A plurality of input/output devices controlled by a computer, and a plurality of devices connected to the common bus, controlled so that only one of them acts as a master station and performs overall management of the common bus at a time. In a multimeter/q machine system with control stations, each its machine and multiple control stations are connected in correspondence, and each control station responds to a status signal indicating whether the common bus is being used normally. Each computer refers to the configuration control information stored in the common memory based on the status signal from the corresponding control station and the command from the other machine. '7sei11i1J jllll tff 'i'14 (D,
fil! li, configuration to the corresponding control station 1till mll 4'R command was issued 'tc fl'Y <'+: Multi n1 with Q
Control system for 3'f aircraft system.