JPS5961315A - Multichannel switch circuit - Google Patents
Multichannel switch circuitInfo
- Publication number
- JPS5961315A JPS5961315A JP17122782A JP17122782A JPS5961315A JP S5961315 A JPS5961315 A JP S5961315A JP 17122782 A JP17122782 A JP 17122782A JP 17122782 A JP17122782 A JP 17122782A JP S5961315 A JPS5961315 A JP S5961315A
- Authority
- JP
- Japan
- Prior art keywords
- switch
- fet
- fets
- control signal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
Landscapes
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
（ａｌ 発明の技術分野
本発明はマイクし１波周波数弗域で使用可能なＩＣ化、
高速、超広帯域の緒特性を有する電界すＪ果トランジス
タによる′１゛形スイッチを単位としたマトリックスス
イッチになる多チヤンネルスイッチ回路に関する。Detailed Description of the Invention (al) Technical Field of the Invention The present invention relates to a microphone that can be used in an IC that can be used in a single wave frequency range;
The present invention relates to a multi-channel switch circuit that is a matrix switch in which each unit is a '1' type switch using electric field J-effect transistors having high-speed, ultra-wideband characteristics.
ｆｂｌ 従来技術と問題点
従来マイクし１波周波数帯域で使用されるスイッチには
同軸スイッチが主として用いられらているが、該同軸ス
イッチはその制御に大電力を必要とするゲ「点があり、
またスイッチング速度が遅く。fbl Prior Art and Problems Conventionally, coaxial switches have been mainly used as switches for microphones and single wave frequency bands, but coaxial switches have the disadvantage of requiring large amounts of power to control them.
Also, the switching speed is slow.
構造が人形なのでマトリックススイッチを構成して高速
な伝送速度を有するネットワーク等で使用する多チヤン
ネルスイッチ回路には適さないもので あ っ ）こ。Since the structure is a doll, it is not suitable for multi-channel switch circuits used in networks with high-speed transmission speeds that form matrix switches.
また、高速ロジックを使用したスイッチが開発されつ−
うあるが、スイッチングの制御に使用される消費電力が
大きくアナログ回路系に使用できない欠点がある。In addition, switches using high-speed logic are being developed.
However, the disadvantage is that the power consumption used for switching control is large and it cannot be used for analog circuit systems.
このため、使用周波数帯域が広帯域であり、ス・イソヂ
ング時間が高速であり、制御に使用される電力が少なく
、ＩＣ化が可能な多チヤンネルスイッチ回路が要望され
ている。Therefore, there is a need for a multichannel switch circuit that uses a wide frequency band, has a fast isostatic time, uses less power for control, and can be integrated into an IC.
（Ｃ１発明の目的
本発明は」−記の欠点に鑑みてこれを解決するために、
広帯域周波数特性のＦＥＴを使用して使用周波数帯域を
広帯域化し、スイッチング特性が高速化し、制御電力が
少なく且つＰ ＩＦ、’Ｉ’の素子数の少なく、更に７
トリンクススイソチの構成が可能でＴＣ化に適した新規
な電界効果ｉ・ランジスタを用いた′１゛形スイソヂを
構成素子にした多チヤンネル回路を提供することを目的
とする。(C1 Purpose of the Invention The present invention is intended to solve the following drawbacks:
Using FETs with wide frequency characteristics, the frequency band used is widened, the switching characteristics are faster, the control power is lower, and the number of PIF and 'I' elements is smaller.
It is an object of the present invention to provide a multi-channel circuit using a '1'' type transistor as a constituent element, which uses a novel field-effect i-transistor that can be configured as a link switch and is suitable for use in a TC.
叶）発明の構成
本発明は」−１記の目的を達成するために、第１及び第
２電界効果トランジ゛スタを入出力端子に幻し直列接続
し、該第１及び第２電界効果１ヘランジスタの中間の接
続点に第３電界効果トランジスタを入出力端子に対し並
列接続して′Ｉ゛形スイッチを構成し、該′ｌ゛形スイ
ッチを単位スイッチ素子としてツー・リソクススイソチ
を構成したことを特徴とする。(a) Structure of the Invention In order to achieve the object stated in ``-1, the present invention connects first and second field effect transistors in series with input/output terminals, and the first and second field effect transistors A third field effect transistor is connected in parallel to the input and output terminals at the intermediate connection point of the helangistor to form an 'I' type switch, and a two-resource switch is constructed using the 'I' type switch as a unit switch element. Features.
（ｅｌ 発明の実施例
以下２本発明を図面に基づいて説明する第１図は本発明
の詳細な説明する図で、電界効果１−ランジスタ（以下
Ｆ Ｅ Ｔとも記す）を用いた′Ｆ形ス・インチを示す
。Embodiments of the Invention The following two examples of the present invention will be explained based on the drawings. Figure 1 is a diagram for explaining the present invention in detail. Indicates inches.
第１図において、第１ＦＣＴＩ、第２ Ｆ Ｉｕ Ｔ
２を入出力端子３，４に対し直列接続にし、その中間の
接続点５に第３ Ｆ Ｅ ｉ’ ６を入出力端子３．４
に対し並列になる如く接続し、第１及び第２ Ｆ ＩＥ
Ｔｌ、２の夫々ゲート７．８を接続して１ＭＡ１子１１
主１１一の制御信号９を入力して同時に動作さ−Ｕ。In FIG. 1, the first FCTI, the second F Iu T
2 are connected in series to the input/output terminals 3 and 4, and the third F E i' 6 is connected to the input/output terminals 3 and 4 at the intermediate connection point 5.
1st and 2nd F IE
Connect the gates 7 and 8 of Tl and 2 respectively to 1 MA 1 child 11
The control signals 9 of the main 11 and 1 are input to operate at the same time.
第３ Ｆ Ｅ”］’ ６のゲート１０には前者の符号に
対して逆レベルの符号の制御信号を端子１２により入力
して′Ｉ゛形スイッチを構成する。即ち、第１及び第２
ＦＥ’Ｆ１．２のゲート７、ＩＯの入力端子１１よりパ
１”レベル制御信号を入力して第１及び第２ＦＥＴｌ、
２を導通（ＯＮ）にする。この時第３ Ｆ ＩＥ Ｔ
６ ノ）ｊ’ −） ニは端子１２より” ｏ”レベル
の制御信冒が人力されて第３ ＦＩＥ ′Ｆ６は不導ｉ
［）路（ＯＦ＋”）になる。この様に制御信号” ｌ”
レベルに刻し、第１ＦＥＴｌ、第２ Ｆ Ｅ ′ＶがＯ
Ｎし、第３ Ｆ ＩＥ ′Ｉ”はＯＦ Ｆ状態になる。A control signal having a sign at a level opposite to that of the former is inputted to the gate 10 of the third F E"]'6 through a terminal 12 to form an 'I' type switch. That is, the first and second
The gate 7 of FE'F1.2 inputs the P1'' level control signal from the input terminal 11 of IO, and the first and second FETl,
2 becomes conductive (ON). At this time, the 3rd FIET
6) j' -) D is the "o" level control input from terminal 12, and the 3rd FIE 'F6 is nonconducting i.
[) path (OF+”). In this way, the control signal “l”
level, and the first FETl and the second FET'V are O.
Then, the third FIE 'I'' becomes OFF state.
また制御漬汁“０“レー＼ルに対し、第１ Ｆ ｒ？、
ｉ’ ｌ 、第２ Ｆ ＩＥ′Ｉ゛２は０ＦＦＩ、、第
３ＦＥＴはＯＮする。コノＯＦ Ｆの時、第３ Ｆ Ｉ
Ｅ ’Ｆ６はショート状態になるが。Also, for the control pickling juice “0” rail, the first F r? ,
i' l , the second FIE'I'2 is 0FFI, and the third FET is turned on. At the time of Kono OF F, 3rd F I
E 'F6 will be shorted.
第１ Ｆ ＩＥ ｌ’ Ｉ 、第２ Ｆ Ｅ Ｔ ２が
ＯＦ Ｉｉ状態になるので、このショート状態による負
荷（ＩＩ＋への影響が防止できる。またＯＮ、ＯＦ＋”
時における第１ＦＬ１．ＴＩ、第２ＦＥＴ２と第３ＦＥ
Ｔ６との損失比を大きくとれる。Since the first F IE l' I and the second F E T 2 are in the OF Ii state, the influence on the load (II+) due to this short-circuit state can be prevented.
1st FL1 at the time. TI, 2nd FET2 and 3rd FE
The loss ratio with T6 can be increased.
上記の′Ｉ゛形スイソヂに使用されているＦ ＩＢ Ｔ
はゲーＩ・に印加される制御電圧を０ポル１〜からピン
チオフ（Ｖｐ）まで変化させることでＦＥＴのチャン不
ルニ１ンダクタンスが数百ミリモーから数マイクロモー
まで変化し、この変化した値をスイツチングに利用する
。F IB T used in the above 'I' type switch
By changing the control voltage applied to the gate I from 0pol1 to pinch-off (Vp), the channel inductance of the FET changes from several hundred mmhos to several micromohos, and this changed value is switched. Use it for.
］゛形スイソヂの直列の第１．第２Ｆ［Ｅ′ｒ”ｌ、２
に対し、中間点５にて入出力端子３，４に並列接続され
た第３ Ｆ Ｅｉ’ ６が入出力端子３．４にりｊし対
称な位置にあるのでＦ ＬＦ、ｉ’のＯＮ、ＯＦＦ時に
おいて他のスイッチ素子に漏話的妨害を与えることが殆
どない。] The first in series of ゛-shaped suisoji. 2nd F[E′r”l, 2
On the other hand, since the third F Ei' 6 connected in parallel to the input/output terminals 3 and 4 at the intermediate point 5 is in a symmetrical position with respect to the input/output terminal 3.4, F LF,i' is ON, There is almost no crosstalk interference to other switch elements when the switch is OFF.
第２図は本発明に係わるＴ形スイノヂの基本回路で、こ
のスイッチの通過ｔ８失は負荷抵抗Ｒ１，によって決定
される。FIG. 2 shows the basic circuit of a T-type switch according to the present invention, and the loss of t8 passing through this switch is determined by the load resistance R1.
第２図において、第１図と同一番月は１〜１２は第１図
と同一機能の同部月を示すならば、第２図において入力
信号Ｖｉｎは入力端子３より入力される。この場合、第
１ＦＥ’Ｔ”１．第２ Ｆ Ｂ ’Ｆ２は制御漬汁入力
端子１１より入力された制御信号でＯＮ状態ニあり、第
３ Ｆ Ｅ ｉ” ６はＯＦ Ｆ状態にあるものとする
。In FIG. 2, if the first month is the same as that in FIG. 1, and 1 to 12 indicate the same month with the same function as in FIG. 1, the input signal Vin is input from the input terminal 3 in FIG. In this case, the first FE'T"1 and the second FE'F2 are in the ON state due to the control signal input from the control juice input terminal 11, and the third FE'T"6 is in the OFF state. do.
人力漬汁■ｉｎはＦＥ′Ｆ１．ＦＥＴ２を通過して出力
端子４を経て負荷（ＲＬ）１３に入力される。Manual pickle soup ■in is FE'F1. The signal passes through the FET 2 and is input to the load (RL) 13 via the output terminal 4.
この時の入力インピーダンスＺｉｎをＺ ｉｒ＋＃ Ｒ
Ｌとし、第３ Ｆ ＩＥ ’Ｖ６のＯＦＦのインピーダ
ンスを無限大として、ＯＮ状態の第１及び第２ Ｆ Ｅ
ｉ”の未飽和時のインピーダンスをＴとすれば、′１
゛形スイッチの挿入１員失りは次式で表示される。The input impedance Zin at this time is Z ir + # R
L, and the OFF impedance of the third F IE 'V6 is set to infinity, and the first and second F E in the ON state
If the unsaturated impedance of i'' is T, '1
The insertion and loss of one member of the ゛ type switch is expressed by the following formula.
Ｌ＝２０ ｌｏｇ（（Ｖｉｎ／２ＲＬ）／ （Ｖｉｎ
／ （２ＲＬ４−２ ｒ） ｌ ）＝２０ ｌｏｇ（
１＋Ｔ／ＲＬ）
となる。ここでＦ Ｅ ｉ’のＯＮの時（未飽和時の抵
抗）Ｔがほぼ一定値であれば負ｆ７抵抗ＲＬによって′
１゛形スイノヂの挿入ｉｎ失が決定される。L=20 log((Vin/2RL)/(Vin
/ (2RL4-2 r) l )=20 log(
1+T/RL). Here, when F E i' is ON (resistance at unsaturated state), if T is approximately a constant value, '
Insertion and loss of the 1-shaped Suinoji are determined.
第３図は本発明の原理（第１図、第２図で説明した内容
）を適用した実施例を示す。FIG. 3 shows an embodiment to which the principle of the present invention (the content explained in FIGS. 1 and 2) is applied.
第３図に示すマトリックススインチは、第２図に示した
Ｆ Ｆ、Ｔスイッチをマトリックス構成にしたものであ
る。該７トリソクス構成のスイッチは。The matrix switch shown in FIG. 3 is a matrix configuration of the FF and T switches shown in FIG. 2. The switch has a seven-trisox configuration.
説明の都合」−４チヤンネル×４ヂヤンネル（以下Ｃ１
ｆとも記す）の多ヂャンネルスイソチ回路について説明
する。For convenience of explanation - 4 channels x 4 channels (hereinafter C1
The multi-channel isochi circuit (also referred to as f) will be explained.
同図のＦ）ＥＴ′？ｌ・リソクスの構成において、各Ｃ
１ｌに対応した入力端子１４−１．１４−２．］４−３
．１４−４をＣｌ１ｌ、 Ｃ１１２，ＣＩ（３，Ｃ１１
４で表し、夫々のチャンネルに対応した出力端子１５−
１． １５−２． １５−３． １５−４をＣｌ１ｌ、
Ｃ１１２，Ｃｆｌ３．Ｃｆｌ４で示す。F) ET′? In the configuration of l.lisox, each C
Input terminal 14-1.14-2 corresponding to 1l. ]4-3
．． 14-4 as Cl1l, C112,CI(3,C11
4, and output terminals 15- corresponding to each channel.
1. 15-2. 15-3. 15-4 as Cl1l,
C112, Cfl3. Denoted as Cfl4.
横行の第１行Ｆ Ｅ ’ｒを１６−１．．１７−１．１
８−１．１９−１とし縦列の第１列のＦＥ′ｒを１６−
１．１６−２．１６−３．１６−４とし第２列を１７−
１．１７−２．１７−３．１７−４とし第３列を１８−
１．１８−２．１８−３．１８−４とし、第４列を１９
−１．１９−２．１９−３．１９−４とする。The first row F E 'r of the horizontal row is 16-1. ．． 17-1.1
8-1.19-1 and FE'r of the first column is 16-
1.16-2.16-3.16-4 and the second column is 17-
1.17-2.17-3.17-4 and the third column is 18-
1.18-2.18-3.18-4 and the fourth column is 19
-1.19-2.19-3.19-4.
以上の入力側のＦ ＥＴは第１図に示したＴ形スインチ
の第１ＦＥＴに相当するもので第１図の第２ＦＥＴに対
応するＦ Ｅ Ｔは出力側の各Ｃｆ対し。The above FET on the input side corresponds to the first FET of the T-type switch shown in FIG. 1, and the FET corresponding to the second FET in FIG. 1 corresponds to each Cf on the output side.
ＦＩＥＴ２０−１．２（１２，２０−３，２０−４であ
り、第１図の第３ Ｆ Ｅ ’Ｆに相当する各ＣＩ＋に
対しｉｐ、するＦ Ｅ Ｔは２１−１．２１−２．２１
−３゜２１−４となっている。FIET 20-1.2 (12, 20-3, 20-4, ip for each CI+ corresponding to 3 FE'F in FIG. 1, FET is 21-1.21-2. 21
-3°21-4.
以上の４ ＣＩｔ ｘ ４ ＣＩＩスイッチに使用され
る７トリノクスのＦ ＩＥ ｉ’数は４×４−１４＋４
＝２４ケである。これに対し、前記のＴ形スイッチを中
位スイッチとして従来のマトリックススイッチを構成す
るとＦ ＩＥ ′ｒ〕数は４ＣＬＩｘ４ＣＩＩ＝１６，
１６Ｘ３＝４８ケとなり１本発明によればマトリックス
ス・インチに使用されるＦＥ’ｒの数は約２になる利点
がある。The number of F IE i' of 7 trinox used in the above 4 CIt x 4 CII switch is 4 x 4 - 14 + 4
=24 digits. On the other hand, if a conventional matrix switch is constructed using the above T-type switch as a middle-level switch, the number of F IE 'r] is 4CLIx4CII=16,
16×3=48, and according to the present invention, there is an advantage that the number of FE'r used in the matrix inch is about 2.
（「）発明のりノ果
以」三木説明によれば、広（（）域周波数特性のＦＥ１
’を使用し′ζいるので周波数特性がよ（、ＦＦ、Ｔを
１−！用しているので制信号の消費電力が少なく。According to Miki's explanation of the fruit of the () invention, FE1 with wide () range frequency characteristics.
Since 'ζ is used, the frequency characteristics are good. (Since 1-! is used for FF and T, the power consumption of the control signal is low.
また周波数特性がよいのでアナしＩり、デジタル両方の
スイッチ回路に適用できる。出力側に用いられる直列接
続されるＦ Ｅ ’］”数、及び並列接続されるＦ Ｅ
ｌ”の数は何れも出力側のチャンネル数に対応してい
るので一ントリノクススイソチのＦ Ｅ ′ｌ”の数を
減小させることが出来る素子がＦＥＴで構成されている
のでＩＣ化に適している利点を有する。Also, because of its good frequency characteristics, it can be applied to both analog and digital switch circuits. The number of series-connected F E']” used on the output side and the parallel-connected F E
Since the number of ``l'' corresponds to the number of channels on the output side, it is possible to reduce the number of F E ′l'' in one linox switch. It has the advantage of being suitable.
第１図は本発明の詳細な説明するための図、第２図は本
発明の基本回路、第３図は本発明の実施例を示す。
図中、１は第１ＦＥＴ、２は第２ＦＥＴ、３は入力端子
、４は出力端子、５は接続点、６は第３ＦＥＴ、７．８
．１０はゲート、９は制御（ｄす。
１１．１２は制御信号の入力端子、１３は負荷抵抗、１
４−１．１４−２．１４−３．１４−４はＣ１ｌの入力
端子、 １５−１． ｌ ５−２． １５−３゜ｌ
５−４はＣｆｌの出力端子、１６−１〜１６−４゜１７
−１〜４．１８−１〜１Ｂ−４，１９−１〜１９−４は
直列素子のＦＥＴ、２０−１〜２〇−４は出力端子に接
続される直列素子のＦＩＥＴ、２１−１〜２１〜４は並
列素子のＦＥＴ。
蔦 １ 図
見２ 図FIG. 1 is a diagram for explaining the invention in detail, FIG. 2 shows a basic circuit of the invention, and FIG. 3 shows an embodiment of the invention. In the figure, 1 is the first FET, 2 is the second FET, 3 is the input terminal, 4 is the output terminal, 5 is the connection point, 6 is the third FET, 7.8
．． 10 is a gate, 9 is a control (d), 11.12 is an input terminal for a control signal, 13 is a load resistance, 1
4-1.14-2.14-3.14-4 is the input terminal of C1l, 15-1. l 5-2. 15-3゜l
5-4 is the output terminal of Cfl, 16-1 to 16-4°17
-1~4.18-1~1B-4, 19-1~19-4 are series element FETs, 20-1~20-4 are series element FIETs connected to the output terminal, 21-1~ 21 to 4 are parallel element FETs. Ivy 1 Illustration 2 Illustration
Claims (1)
し直列接続し、該第１及び第２電界効里トランジスタの
中間の接続点に第３電界効果トランジスタを人出力αｇ
＋子に対し並列接続して′１゛形スイッチを構成し、該
′Ｖ形スイッチを中位スイッチ素子としてマトリックス
スイッチを構成したことを特徴とする多チヤンネルスイ
ッチ回路。The first and second field effect transistors are connected in series to the input/output terminal, and the third field effect transistor is connected to the connection point between the first and second field effect transistors for output αg.
1. A multi-channel switch circuit characterized in that a '1' type switch is configured by connecting in parallel to a positive terminal, and a matrix switch is configured using the 'V type switch as a middle switching element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17122782A JPS5961315A (en) | 1982-09-30 | 1982-09-30 | Multichannel switch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17122782A JPS5961315A (en) | 1982-09-30 | 1982-09-30 | Multichannel switch circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5961315A true JPS5961315A (en) | 1984-04-07 |
Family
ID=15919397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17122782A Pending JPS5961315A (en) | 1982-09-30 | 1982-09-30 | Multichannel switch circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5961315A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4998101A (en) * | 1988-08-08 | 1991-03-05 | Siemens Aktiengesellschaft | Broadband signal switching matrix network |
| US5635745A (en) * | 1994-09-08 | 1997-06-03 | National Semiconductor Corporation | Analog multiplexer cell for mixed digital and analog signal inputs |
| WO2000040040A1 (en) * | 1998-12-28 | 2000-07-06 | Sun Microsystems, Inc. | High-speed switching network using t-switches |
-
1982
- 1982-09-30 JP JP17122782A patent/JPS5961315A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4998101A (en) * | 1988-08-08 | 1991-03-05 | Siemens Aktiengesellschaft | Broadband signal switching matrix network |
| US5635745A (en) * | 1994-09-08 | 1997-06-03 | National Semiconductor Corporation | Analog multiplexer cell for mixed digital and analog signal inputs |
| US5639680A (en) * | 1994-09-08 | 1997-06-17 | National Semiconductor Corporation | Method of making analog multiplexer cell for mixed digital and analog signal inputs |
| WO2000040040A1 (en) * | 1998-12-28 | 2000-07-06 | Sun Microsystems, Inc. | High-speed switching network using t-switches |
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