JPS5922435A - Latch circuit - Google Patents

Abstract

PURPOSE:To simplify a control line and to decrease the number of elements, by inserting an FET of the same conduction type in series to an FET of a conduction type in one inverting circuit of two inverting circuits comprising C-MOSes. CONSTITUTION:A clock terminal C is connected to a gate of an N MOST14 and a gate of a P MOST17. An input terminal D is connected to a source of the N MOST14. When an H level is inputted to the terminal C, the N MOST14 is conductive, the P MOST17 is nonconductive, and when a terminal D is at an L level, an output terminal Q goes to the L level, a P MOST20 is conductive, an N MOST21 is nonconductive and an output terminal Q' goes to an H level. When the terminal C changes from H to L level, the N MOST14 is nonconductive and the P MOST17 is conductive, and the output terminal Q is kept to the L level and the Q' is kept at the H level.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary field effect transistor (hereinafter referred to as C-MO8
The present invention relates to a C-MO8 latch circuit, in particular to a C-MO8 latch circuit.

The latch circuit of C-MO8 is a P channel enhancement ff1M08) transistor (hereinafter P
A transfer gate, which is a pair of a type MO8T) and an N-channel enhancement type MOS transistor (hereinafter referred to as an N-type MO8'I'), is constituted by two pairs and two inverter circuits.

In this configuration, D is a data input terminal, C and C are clock terminals Q, and Q is an output terminal.

Here, the operation shown in FIG. 1 will be briefly explained.

Clock terminal C is NmMO8T2 and P type MO8TIO
The clock terminal connected to the gate of PmMo5't'
1, c1my, and os'r11(7), and the input signal of the clock terminal C and the input signal of the four clock terminal C are inputted with opposite phases to each other. P-type HO8TI source and N-type MO8'l! The source of MO8T2 is connected to the input terminal, and the drain of P-type MO8T1 and the drain of N-type MO8T2 are connected to the gate of P-type MO8T4 and the drain of N-type MO8T5.
connected to the gate. P type MO8T4 and N type MO8T
5 constitutes a first inverter circuit, and the output of the inverter circuit is Q.

A second inverter circuit is composed of the P-type MO8T7 and the 8th generation MO8Ta, and the output of the inverter circuit is
The input of the inverter circuit is connected to the Q.

The source of the P-type MO8TIO and the source of the N-type MO8T11 are connected to the gates of the P-reduced MO8T4 and N-type MO8T5, and the drain of the P-type MO8T10 and the NfiMO8
The drain of T11 is connected to the output Q of the inverter.

Here, a high level (VDD level) signal is input to the clock terminal C, and a low level (Vss level) signal is input to the clock terminal C. ! : PWMO8T1 and N-type MO8T2u conductive signals from the input terminals are transmitted to the first inverter circuit, at this time P-type MO8Txo and N-type MO8T1
1 is non-conductive.

If the input signal is at a high level, the output Q of the first inverter circuit will be at a low level, and the output Q of the second inverter will be at a high level. If the input signal is low level, the output Q of the ml inverter circuit is...invel υ
The output Qh of the second input/output circuit becomes low level.

Next, a low level is applied to the clock terminal C, and the clock m terminal Uv
When the c level is input, P-type MO$T1 and N-type MO8T2 become non-conductive υ, and P-type MO8T10 and N-type MO8T11 become conductive. υThe information of the input signal is latched and the data is held. Ru.

According to the conventional circuit shown in FIG. 1 explained above, the clock signal requires a fourth signal with an opposite phase, and a transfer gate circuit for data retention is required, resulting in complicated control lines and an increase in the number of elements. It becomes a cause of increase.

An object of the present invention is to provide a 0MO8 latch circuit with simplified control lines and reduced number of elements.

Next, the present invention will be explained with reference to the drawings.

FIG. 2 shows an embodiment of the present invention. In FIG. 2, the clock terminal C is connected to the gate electrode of the N-type MO8T14 and the Pi
The input terminal is connected to the gate electrode of MO8T17 and the input terminal is connected to the source electrode of N-type MO8T14.
The drain electrode of No. 4 is connected to the drain electrode of P-type MO8T17. P-type MO8T 17 (0 so = x [pole is PW
MO8T16(D)' is connected to the rain electrode and the P-type MO
The source electrode of the 8T16 is connected to the power supply terminal VDD (which has the highest potential), and the gate electrode of the P-type MO8T16 is connected to the output terminal Q. The drain electrode of N-type MO8T18 is connected to the drain electrode of N-type MO8T14.
The source electrode of the type MO8T18 is connected to the power supply terminal Vss (the lowest potential), and the gate electrode of the N type MO8'i''18 is connected to the output terminal Q.P type MO8T17
The drain electrode of the N-type MO8T and the drain electrode of the N-type MO8T are both connected to the output terminal Q. Output terminal Q is P type MO8T
20 and the gate electrode of N-type MO8T21, and the source electrode and drain electrode of P-type MO8T20 are connected to power supply terminal VDD and output terminal Q, respectively.
A source electrode and a drain electrode of the N-type MO8T21 are connected to a power supply terminal VSS and an output terminal q, respectively. ' The operation shown in FIG. 2 will now be explained.

When no signal is input to the clock terminal C, the N-type MO
8T14 is conductive and P-type MO8T17 is non-conductive.
At this time, if the input terminal Q is at a low level, the output terminal Q will not be at a low level, the P-type MO8T20 will be conductive, and the N-type MO8T20 will be conductive.
O8T21 becomes non-conductive and the output terminal Q becomes /.inbel. When the output terminal Q becomes 7 invel, N type MO
8T18 becomes conductive and P-type MO8TJ6 becomes non-conductive. Next, when the clock terminal C changes from no impel to low level, N-type MO8T+4 becomes non-conductive, and P-base MO8T17 becomes non-conductive.
is not conductive, the output terminal Q is held at low level, and the output terminal Q is held at knee level.

When the clock terminal C is at an invert level and the input terminal is at a high level, the output terminal Q is at an invert level, the N-type M, 08T21 is conductive, and the P-ya MO8T20 is non-conductive. Q is low level υ, therefore N type M
O8T18 becomes non-conductive.

Next, when the clock terminal C becomes low level, the N-type MO8T
14 is non-conductive, and the P-type MO8T17 is conductive.The output terminal Q...the invert output terminal Q is held at a low level.

FIG. 3 shows another embodiment of the invention.

In the embodiment shown in FIG. 3, the gate electrodes of the P-type MO8Ts 16 and 17 are connected to the output terminal Q1 and the clock terminal C in FIG.
Connect the gate of 7 to the clock terminal C to create a P-type MO8T28.
The same effect as the configuration shown in FIG. 2 is obtained by connecting the gate electrode of 1 to the output terminal Q.

FIG. 4 shows another embodiment of the invention.

In FIG. 4, the clock terminal C is connected to the gate electrode of P-type MO8T36 and the gate electrode of N-type MO8T39, the input terminal is connected to the source electrode of P-type MO8T36, and the drain electrode of P-type MO8T36 is connected to the gate electrode of N-type MO8T39.
It is connected to the drain electrode of 9.

The source electrode of the N-type MO8T39 is connected to the drain electrode of the N-type MO8T40, the source electrode of the N-type MO8T40 is connected to the power supply terminal VSS, and the gate electrode of the N-type MO8T40 is connected to the output terminal Q. PiMO8T3
80)'The rain electrode is connected to the drain electrode of NWMO8T39, and the gate electrode of the P-type MO8T38 is connected to output terminal Q. P-type MO8T41 gate electrode and N
The gate M1 poles of the MO8T42 type are both connected to the output terminal Q, and the P-type MO8T41 and N-type MO8T42 form an inversion circuit, and the output of the inversion circuit is connected to the output terminal Q.

In the embodiment shown in FIG. 4, when a low level is input to the clock terminal C, the P-type MO8T36 becomes conductive, and the N-type MO8T39 becomes conductive.
Information from the input terminals that are non-conductive is transmitted to the output terminals Q, Q. When clock terminal C becomes low level, P type M
The O8T36 is non-conductive, the N-type MO8T39 is not conductive, and the information of the output terminals Q and Q is held. .

FIG. 5 shows another embodiment of the invention.

In the embodiment shown in FIG. 5, N-type MO8T39 is shown in FIG.
By reversing the connections in which the gate electrodes of and N-type MO8T40 are connected to the clock terminal C1 and the output terminal Q,
The gate electrode of the N-type MO8T49 is connected to the clock terminal port, and the gate electrode of the N-type MO8T4B is connected to the output terminal Q to obtain the same effect as the configuration shown in FIG.

As described above, according to the present invention, it is possible to obtain a 0MO8 latch circuit in which the control signal is simple and the number of elements is reduced.
It is particularly effective for use in large-scale logic integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a conventional C-MOS latch circuit diagram, FIG. 2 is a circuit diagram of one embodiment of the present invention, and FIGS. 3 to 5 are circuit diagrams of other embodiments of the present invention. In Figure 1, 1.4.7.10 is a P-channel enhancement mMO8 transistor 2.5.8°11 is N
Channel enhancement mMO8 transistor, 16.17°20.27.28 in Figures 2-3
．． 31 is a P-channel enhancement type MO8) transistor, 14.18.21.25.29゜32 is an N-channel enhancement lJIMOB transistor, 36.38゜41.45, 47 in Figs. 4 and 5.
．． 50 is a P-channel enhancement type MO8) near-y transistor, and 39.40.42.48.49.51 is an N-channel enhancement type MO8 transistor. Moe 1m Vss Vss Figure 2 Section 3

Claims (1)

[Claims] The output of one of two inverting circuits constituted by complementary field effect transistors is mutually connected to the input of the other,
In one inverting circuit, a transistor of the same conductivity type is inserted in series with a transistor of the L conductivity type, and a transistor of the opposite conductivity type to the inserted transistor is inserted between the output and the input terminal of the inverting circuit, and the two A latch circuit characterized in that a control signal is input to the gate electrode of a transistor inserted.