JPS59151389A - large scale integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a high-density integrated circuit, and particularly to an integrated circuit suitable for a high-density semiconductor memory.

[Prior art]

Conventionally, in order to achieve high integration of semiconductor memory, Japanese Patent Application Laid-Open No. 1987-
No. 104276 proposes a technique that combines two types of gate oxide film thicknesses and two types of gate region surface concentrations.

In addition, JP-A-50-11.9543 discloses that by implanting ions into the Si surface of a part of the memory array at a high concentration, the channel length of the transistor in the memory array can be further reduced, and the distance between the diffusion layers can be further reduced. Techniques have been proposed to improve the degree of integration. However, when the dimensions of circuit elements such as transistors are reduced by such techniques, the withstand voltage of these circuit elements against dielectric breakdown inevitably becomes smaller. Therefore, the power supply voltage applied to these circuit elements or the signal voltage generated by these circuits needs to be reduced as the dimensions of the circuit elements are reduced.

On the other hand, from the user's perspective, there is a desire to keep the externally applied voltage (voltage applied to the power supply pin of the memory LSI package) constant regardless of the dimensions of the transistors that make up the memory. be. Therefore, it is not desirable to reduce the externally applied voltage. Therefore, with the above-mentioned conventional techniques, it is not possible to realize a highly integrated memory that can use a high external voltage. This applies not only to memories but also to other integrated circuits.

In order to solve these problems,
In this paper, a method for realizing a highly integrated circuit that can use a high external voltage, has small dimensions, and internally carries circuit elements that operate at a low operating voltage is proposed.

The present invention has the following features: (1) In general, circuit elements connected to external input terminals in an integrated circuit must have a high withstand voltage.

This is to prevent this element from being destroyed even if a high voltage is supplied to this terminal from the outside or even if electrostatic force is generated. Therefore, it is actually necessary to make the dimensions of the circuit elements connected to this external input terminal very large.

(2) As mentioned above, the internal circuits of integrated circuits are made smaller in size, and in order to prevent damage even if the withstand voltage is reduced, the power supply voltage supplied to them or the signals generated by them are reduced. It is desirable to reduce the voltage value. Considering these two points, the circuit elements in the first circuit that respond to a signal with a large amplitude are formed with large dimensions so as to have a large withstand voltage, and the circuit elements in the second circuit that respond to the output signal of this circuit are formed with large dimensions so that the withstand voltage is large. It is proposed that the circuit elements of the circuit be formed with small dimensions in order to achieve high integration. Further, a power supply circuit made of large-sized circuit elements is provided to which the high first power supply voltage is input and for supplying the second circuit with a second power supply voltage lower than the first power supply voltage, The first power supply voltage is input to the first circuit, and the second
The internal signal is configured to generate an internal signal having a voltage corresponding to the power supply voltage. The second circuit is proposed to be configured to receive a second power supply voltage, be activated by this internal signal, and output a signal having a voltage corresponding to the second power supply voltage. .

As a result, 1. The second circuit C. There is no problem with the withstand voltage.Furthermore, since the second circuit is formed of small-sized circuit elements, the area occupied by the second circuit is small in the entire integrated circuit. Because it is thick, high integration is achieved when looking at the integrated circuit as a whole.

FIG. 1 is a sectional view of a memory chip for a dynamic memory made of a blank P-type substrate 10, showing the concept of the system disclosed in the above application. N-type MOS transistor (MO8T)
Q, P gate oxide film t. X, is made thicker than the gate oxide film tOXl of MO8T, Qm, and MOS T,
A high drain voltage, for example, an external voltage Vcc (for example, 5■) is supplied to the drain Dp of MO8.
The drains Dm of T, Q, and m are supplied with a voltage Vnp lower than Vcc (for example, 3. 5 V) is supplied.

The external voltage Vcc is input to the substrate voltage generation circuit 2o,
Here, a bias voltage of, for example, -3V is generated for the substrate 10. Although the circuit 20 is shown outside the substrate 1°, it is actually provided inside the substrate 1o. Normally, the density of memory depends on the peripheral circuitry (direct peripheral circuitry) that is directly connected to the memory array, such as the memory array and sense amplifiers (not shown) that drive it or amplify the minute signals output from it. ) is determined by the degree of integration of the first circuit section 40. Therefore, the MOS of this part
The dimensions of T and Qm were made small. This dimension is Mos
In general, it is possible to reduce the voltage by lowering the operating voltage, considering the breakdown voltages of 'r, o, m, hot electrons, substrate current, etc. Here U, MO8
The gate oxide film TO4 of T, Q, and m is made thinner, the drain voltage is set to Vnp lower than vcc, and the channel length is made smaller than LMO8. Of course, the maximum value of the voltage of the gate G m also generally needs to be i'j: V Dp. On the other hand, the second circuit section 50 that includes other control circuits, that is, the circuits that control the surface peripheral circuits (indirect peripheral circuits), occupies about 10% of the entire chip area, so it is especially important for small dimensions. There is no need to use 40 ST. Rather, since this indirect peripheral circuit is connected to an external input terminal, it is necessary to have a sufficiently high level of suppression of electrostatic discharge damage. For this purpose, it is generally necessary to thicken the gate oxide film tox2 of the MO8T Op and to use MOSTs Q and P with correspondingly large dimensions (for example, chamfer length). Here, this gate oxide film jOX2 is replaced with a gate oxide film to
x, Due to the lengthening of the channel length, the drain 1M1 voltage of QP is reduced to the drain voltage V of Qm.
Set Vcc higher than op. Of course, the maximum value of the evening pressure of the gate Gp is generally set to Vcc.

Note that the sources Sp and Sm of OP and 0 are both held at ground potential. As shown in FIG. 1, the dimensions of MO8T Om of the first circuit section 40 consisting of memoria l/- and direct peripheral circuits, which affect high integration, are small, and the dimensions of MO8T Om of the second circuit section 50 consisting of indirect peripheral circuits are small. It is made thicker depending on the dimensions of MO8T Q and p. By doing so, by using the power supply voltage (Vcc: 5V, for example) from outside the chip as the operating voltage,
Op becomes operable 4, and the switched Om converts Vcc within the chip to become operable at a lower operating voltage (VDP: 3.5V, for example). Generally, the lower the operating voltage is, the more desirable it is to correspondingly lower ■th from the viewpoint of high speed. In this regard, from the general characteristics of MO8T, if the gate oxide film tax becomes smaller, the th also becomes lower, so that the operating speed of the first circuit section, which accounts for a large portion of the operating speed of the memory, can be increased.

Therefore, this method is advantageous in terms of speeding up.

Now, with the above circuit system, the memo IJLSI
When configured, the memory array and direct peripheral circuits such as sense amplifiers, word drivers, and decoders that control it are composed of small-sized elements t, and the voltage used there is an operating voltage lower than the externally applied voltage. Will be using it. Therefore, it is possible to realize a memo 'JLSI' that can be used with high power supply and pressure, and that is sieved. However, low voltages must be used for the memory array and all direct peripheral circuits, there is a limit to the power supply driving ability of the internal power supply voltage circuit, and many control circuits are required to lower the voltage for many internal signals. As a result, the memory circuit operation becomes complicated and the layout area increases. There is no need to go to the trouble of using small-sized transistors in circuits with a flexible layout and plenty of space.

Large-sized transistors can be used in such circuits, and the circuit design becomes easier as it eliminates the need to apply a voltage limiter circuit method.

[Purpose of the invention]

Therefore, an object of the present invention is to provide a memo IJL8I that has a simple circuit configuration and has a circuit that uses an externally applied voltage as it is and a circuit that lowers the voltage internally and uses this voltage. The object of the present invention is to provide a memory circuit suitable for high integration.

[Summary of the invention]

The present invention provides a memory circuit that can achieve high integration and is easy to design. is kept to a minimum. That is, in the memory circuit of the present invention, basically only the voltages applied to the data lines and word lines are lower than the externally applied power supply voltage, and the dimensions of the transistors connected to them (MOS
-The channel length and gate oxide film thickness of the FET are reduced. More specifically, the precharge voltage of the data line is set to a voltage lower than the external power supply voltage, and the voltage amplitude of the word line driving pulse signal is also set to a voltage lower than the external power supply voltage.

Further, in the memory circuit, the precharge voltage of the common data line for taking out the data line signal is set to a low voltage, and the voltage for writing the memory signal into the memory cell is also set to a low voltage.

Further, the memory circuit is a memory circuit in which the transistors forming the memory cell, dummy cell, and word line drive circuit are small in size, and the other circuits are formed by large transistors.

In addition, when rewriting or writing 1, the voltage is set to 40 or more of the word line voltage or data line voltage and the threshold voltage of the MOS transistor of the memory cell, and this MO8+-
Prevents signal loss due to transistors.

[Embodiments of the invention]

FIG. 2 shows a one-transistor type MOS dynamic memory circuit according to an embodiment of the present invention, and shows a memory array circuit that mainly uses a voltage lower than the externally applied power supply voltage and its related circuits. In the figure, circuit group 1 surrounded by a dashed-dotted line is a memory array circuit, and circuit group 2 surrounded by a dashed-dotted line is a circuit that controls the memory array circuit and amplifies the signal from the memory cell (direct peripheral circuit). A circuit group 3 surrounded by a chain line is a circuit (indirect peripheral circuit) that provides a signal to the surface peripheral circuit, amplifies the memory signal from the memory array circuit, and writes the memory signal to the memory array circuit.

In the memory array circuit, only the (11) circuit of one pair of data lines (D, D) is shown), and a large number of such circuits are arranged to constitute the memory array. Here, the memory cell is constituted by a small-sized transistor OM1 and a capacitor CM1 so as to be suitable for high integration, and the other memory cells are similarly small-sized transistors OM, .about.0. Mn
, and capacitors CM2 to CMn. The dummy cell that outputs a comparison signal with respect to the signal from the memory cell is also composed of a small-sized transistor Q and a capacitor C1, and the other dummy cells are similarly composed of a small-sized transistor 0.11 and a capacitor C2. . These will operate at low voltages.

Note that the transistors Q,o,Q,. constitutes a circuit that discharges the charge of the dummy cell when the memory is on standby. Nodes P of capacitors C1, C1, CM, ~cMn are set at ground level or a certain voltage level. When applying a certain voltage, usually the memory power supply voltage is applied, but
Depending on the structure of the capacitor, a voltage p lower than that may be applied.

(12) Direct peripheral circuits include word line related circuits that take out signals from memory cells to data lines, sense amplifier related circuits that amplify signals taken out to data lines, and data line selection to take out the amplified signals to the main amplifier. It can be divided into related circuits. In the word line related circuit, the word line W connected to the memory cell receives the timing pulse φX1 from the indirect peripheral circuit and the signal from the decoder A.
In terms of layout area, the word driver circuit that drives 1 to Wn is composed of small transistors QD1 to QDn.
The dummy word driver circuit for driving the dummy word lines WD, WD, connected to the dummy memory cells must also be constructed from small-sized transistors Q1°, Ql. Even if the transistor has such a small size, the word voltage is low in relation to the memory cell, so there is no problem with the device breakdown voltage. in this way,
The voltage of the word line and dummy word line is the externally applied power supply voltage (voltage applied to the package power supply bin Vcc = 5■)
In order to make the voltage lower, the positive amplitude of the φx1 signal (13) is controlled to a lower voltage by circuit G. A word latch and a dummy word latch that prevent transient fluctuations due to noise on word lines or dummy word lines during non-selection or standby are transistors QL.

~OLn and 0. +t, Qxs K, and a circuit for setting the selected word line voltage to 1 and setting the dummy word line voltage to the ground level; transistors OC1 to OCn and Q;
, , , Q, , , are configured. Here decoder A
Although the circuit is not shown, this circuit is
．． A circuit as shown in No. 49897 may also be used. Also, the address signal used in this decoder is an external address signal (
The address buffer circuit for generating this address signal may be a circuit as shown in Utility Model Application No. 56-2777.

In the sense amplifier related circuit, the sense amplifier that amplifies the signal taken out from the memory cell to the data line is composed of transistors O, r, Q, and t, and the circuit that separates the sense amplifier and the memory array is composed of transistors Q,
It is composed of s -0,4. (14) The data line short circuit at the time of retention V- is the transistor Q.
.

The data line precharge circuit is composed of transistors Q, a, Q, . Since the data line precharge voltage is set to a voltage lower than the externally applied power supply voltage, the precharge circuit is connected to the data line precharge power supply circuit F. The sense amplifier drive circuit is composed of transistors Q+s + Q, +or Q20.

Note that circuits other than the sense amplifier drive circuit are provided for each data line pair. The data line selection related circuit is almost the same as the word line related circuit, and includes a decoder circuit, but these are omitted here. Only the switch circuit with data linework 10°Ilo is shown. This switch circuit is composed of transistors 0.21 + Q, tt.

The indirect peripheral circuit mainly consists of a timing pulse generation circuit section that generates timing pulses used to drive the surface peripheral circuit, a main amplifier section that amplifies the memory signal from the memory array and outputs the data to the outside, and a memory cell data amplification section. (15) A circuit section for writing, which is composed of a circuit section that generates a low voltage used inside the memory. The timing pulse generation circuit section was built in 1930.
A timing pulse train is created by cascading pulse circuits as shown in 69 of the 4th year National Conference on Semiconductors and Materials of the Institute of Electronics and Communication Engineers.

Here, only the timing pulse circuit B used for driving the word line is shown. The main amplifier section is transistor Q,
27-01. It is composed of: Here, the common data line short circuit and precharge circuit is the transistor Q
, 27 to 0.29.

Amplification circuit for signals from memory array C, transistor Q
, se~Q, 40. In addition, the compensation circuit on the high potential side when amplifying the above signal is the transistor Q
It is composed of 3°~o+tg. Note that transistor 0
41 to Q are circuits for outputting data read from the ASID memory array to the output bin of the package.

Write circuit part c, transistor 0.23 to 0.26
It consists of Note that the circuit C is a circuit (data manual buffer circuit) for determining input data applied to the bin of the package, and is a circuit similar to the address buffer circuit described in (16) above. Here, the precharge voltage of the common data line, the high potential compensation voltage during signal amplification, and the
Since the included voltage is lower than the externally applied power supply voltage, the circuits related to these are connected to the power supply circuit H. The circuit parts that generate low voltages are a data line precharge power supply circuit F1, a word line drive pulse voltage control circuit G1, a common data line related power supply circuit H, and a circuit E that supplies a reference voltage for voltage control to these circuits. Configure.

The circuit E that supplies the reference voltage has two types of reference voltages (for example, VLt=4.5 V, VLt=3.5 V
) Use a circuit as shown in the circuit where all occurrences occur. The word line drive pulse voltage control circuit G receives the higher voltage (V+, 1=4.5V) of the reference voltages and generates a timing pulse φXj (4.5V) which controls the signal voltage (5■) of the timing pulse φX. ), which is a circuit that outputs
No. 68698, using a circuit as shown in FIG. 23, VLt in the same figure becomes VLI in FIG. 2, and φ.

is φX in Fig. 2, and φ. ' is compared to φx1 in Fig. 2 (17
) respond. Therefore, the data line precharge power supply circuit F1 which applies a voltage controlled to be lower than the externally applied power supply voltage to the word line and the dummy word line, and the common data line related power supply circuit 11, are connected to the lower reference voltage. The power supply circuit receives the voltage (V L2 = 3.5 V) and generates a voltage (3.5 mm) lower than the timing pulse φxt. Therefore, a voltage lower than the word line voltage is often supplied to the data line and the common data line. Here, the word line voltage is determined from the data line voltage by the memory cell's transfer transistor (for example, OMI).
By increasing the voltage by the threshold voltage of the transistor, it is possible to eliminate memory signal loss due to the threshold voltage of this transistor during reading. Furthermore, since the write voltage to the memory cell can be increased by this amount, stable memory operation is possible.

Next, the operation of the circuit shown in FIG. 2 will be explained, focusing mainly on the memory read operation, using the timing pulse waveform shown in FIG. 3.

Immediately after the sense amplifier and main amplifier operate and the data of the memory (18) cell is output from the memory, the data pair line D, the common data pair line I10. I/O has a high potential (precharge level) and a low potential (O
v) is separated into After this, when the memory enters the standby state, first the l signal is set to a high potential (power supply voltage 5V), and the data lines I) are short-circuited by transistors Q, . Next, the 6 signal is set to a high potential (5V), and the data line and sense amplifier drive circuit are connected to the transistor 0.6 signal. , ,0. and Q
A low voltage (3.5 V) generated in the power supply circuit F through
). At this time, the φC signal is at a high potential (5
v), and the sense amplifier circuit is also precharged at the same time. The φP signal is also set to a high potential (5V), and the potential of the capacitors C, , C, of the dummy memory cells is set to the transistor Q, o.
,Q,+. Ground level (OV) through,! :do.

In addition, the φP4 signal is also set to a high potential (5■), and the common data lines I10. I10 is a transistor Q2a + Q,t
. The low voltage (3,5V) generated in the power supply circuit H through
) K precharge. At this time, φd times the signal high potential (5
v), and the high potential compensation circuit (19) is also precharged at the same time. Here, φa times the signal high potential (5
V), and the transistors QC, ~QCn and o
l, I Q! 3 holds the word line and dummy word line at ground level (OV).

After this, Cl1pl, #p2, $;3,
(llp4, φ signal is set to low potential (0■), and after the memory period state ends, φ, double signal is set to high potential (5V)
Then, the word line driving signal φx (5
V) is output. This φX signal is controlled by the voltage control circuit G to be the reference voltage V J (4,
5V), the signal φ whose voltage amplitude is controlled to 4.5V
X.

becomes. Furthermore, this φχI signal is transmitted to the word line and dummy word line through the word driver and dummy word driver selected by the decoder. therefore,
A lower voltage (4.5 V) than that of the externally applied power supply is applied to the word line and dummy word line. Note that at this time, the φd times signal is applied to the word latch circuit and the dummy word latch circuit, but the φb times signal voltage is around 2 mm, and the resistance of the word latch circuit is high.

(20) The word latch circuit of the dummy word line and the voltage drop caused by the dummy word latch circuit can be ignored. Here, φXI
Assuming that the signal is transmitted to the word line W1 and the dummy word line I)W, the data line DK is transmitted to the memory cell capacity (11',
The signal that was on CM, H is output through the transistor OM, and the signal for comparison of the data line DK (fil) dummy memory cell capacitance C1 is output through the transistor Q. Next, the φ2 signal and, after a little delay, the φ3 signal are output high. potential(
5V), the sense amplifier drive circuit is operated, and the memory signal is amplified by operating the sense amplifier. Note that by slightly lowering the φC signal level from 5V at the start of this amplification, a drop in level on the high potential side of the data line is prevented. After amplifying the memory signal in this manner, the φ4 signal is set to a high potential (5V), and the switch circuits of the data line and common data line are turned on. Therefore, the amplified memory signal is transmitted to the common data line, and φ,
By increasing the potential of the signal to a high potential (5V), this signal is further amplified (21) by an amplifying circuit constituted by transistors Q, aa to Q, and 40. At this time, transistor Q. ~0.3! l f
In the high-voltage first compensation circuit, a voltage corresponding to the voltage of the common data line is applied to the transistor 0. ,, I Q311
The high potential is compensated for by holding the signal at the gate of φ and double the signal high' (5V). That is, after amplification is performed in the amplifier circuit using the transistor Q, s 6 to 0.40, the common data line I10. If I10 is separated into a high potential side and a low potential side (Ov), the gates of transistors Q, ss, and 0.34 are at a high potential and a low potential (Ov), respectively. Therefore, only the MO8 capacitor is formed by the transistor QsH. In this state, when the φ7 signal is set to a high potential (5■), the transistor 031 is turned on and a voltage is supplied from the p1 power supply circuit H to the high potential side of the common data line, so that high potential compensation can be performed. Here, when the φd-times signal amplification starts, the level of transistor Q5 drops slightly from the level of 5■.
(or Q34) prevents a drop in the high potential held at the gate. The signals amplified as described above are transmitted to the transistors 041 to 03. In the amplifier circuit, φ, the signal (22) is further amplified by making it high voltage 1 (5V), and output to the output bin of the package.

The above describes the memory read operation, but the write operation is performed as follows.Input data J applied to the data input bin of the package An internal data input signal dln with a voltage amplitude of 5V is generated by the manual buffer circuit C.
, d, In. Next, this data input month code is input to a write circuit composed of transistors 0.23 to 026, and the input data is written into the memory cell via the common data line and the data line. Here, the output voltage of the write circuit is the same voltage as the voltage of the power supply circuit H (3.5 V).

The method of using a low voltage for both the data line and the word line has been described above, but depending on the structure of the memory cell, it is also possible to use a low voltage only for the data line. Furthermore, since the levels of dIn and dln are always OV except during writing, the writing circuit is separated from the common data line.

As explained above, by setting the voltage applied (23) to the data line and word line to a voltage lower than the externally applied power supply voltage, memory cells, dummy memory cells, etc.
It is possible to reduce the dimensions of transistors constituting word drivers and the like, thereby improving the degree of integration. However, by making the word line voltage higher than the data line voltage by the threshold voltage of the transistor constituting the memory cell, it is possible to eliminate memory signal loss due to this transistor.

Furthermore, since the word line voltage is higher than the data line voltage, there is no need to boost the word line voltage to a level above the power supply voltage using a capacitor or the like, as was conventionally done, and therefore a simple circuit occupying a small area can be used. Due to the small size, the word latch circuit can be constructed of one transistor having a direct current path as shown in FIG. Therefore, the l/i-aud area of the word latch can be reduced.

Now, the dimensions of the transistor of this method (MOS-PET) are determined by the channel length Lg and the gate oxide film thickness Tox, depending on the layout area occupied by the transistor and the stress voltage applied to the transistor (24).
As an example, the dimensions of the transistor used in the circuit shown in FIG. 2 are shown in Table 1.

Below, Lg and Tox of each transistor in Table 1 are (25
) State the reason for your selection.

The transistors Q and Q that make up the sense amplifier are small and heavy, but if there is a difference Δ■th between the threshold voltages of Q and Q, the effective noise will be increased by that difference. Therefore, it is normal to match these threshold voltages as much as possible. To this end, from the general characteristics of transistors, the thicker Lg is, the more ToX
is small, so L g is determined in balance with the layout area.
= 2.7 μm.

Tox = 2Q nm is chosen. Qs r
Q, 4 +Qa l Qe l Q7 y Qo +
QIO+ Q+t I Q, 13 +QC+ ~Q, C
”, Q, +4− QIO, QLI ~QLn.

Qlg + Q+o + Q, 20 * Qt+ +
Q, tt 'I''j Nilayud L g = 2.1 μm because there is a margin in terms of area.

'["ox = 4Qnm, a relatively large size transistor can be used. Therefore, the operating voltage of these is basically not required to be the output voltage of the voltage IJ transmitter.
It may be a voltage based on c. Qa + Q+t +QM
l-QM, l-j is the memory cell transistor that contributes most to high integration, g = 1.3 μm, Tax (26
)=:2Qnm, the smallest transistor is used.

Also, Q, +e, Q, 17, QDt ~Q, D
In terms of layout area, L is relatively small.
g = 1.6 μm.

Tax=2Qnm transistor is used.

Note that the transistors in the decoder and indirect peripheral circuits are
For example, it is sufficient to construct the transistor with a large transistor having a channel length L g =2.1 μm and a gate oxide film thickness 'l''ox =4Q nm or more, so these values are omitted.

In the above embodiment, all the circuits are composed of n-Mo5, but memory cell-related components include n-channel transistors, direct peripheral circuits, or indirect peripheral circuits UC-MO5.
8) It is obvious that the present invention can also be applied to a case composed of transistors.

FIG. 4 shows an embodiment of the present invention in a static memory. The figure shows n −M O inside the memory array.
Only one memory cell formed of S is selected and shown together with circuits related to the operation of the memory cell. This embodiment is also similar to the previous embodiment in that the voltage applied to the data line D and word line W (27) is set to a voltage lower than the power supply voltage for applying an external voltage.

In FIG. 4, circuits I and L correspond to the circuits F and E of the previous embodiment, and are circuits that generate a voltage lower than the power supply voltage to which an external voltage is applied. In the same figure, the memory cells are n-channel transistors Q, +04~QIQ? and resistance R,,R,,
It is composed of: The low voltage mentioned above is applied to this memory cell to reduce power consumption during data retention. The sense amplifier that amplifies the signal from the memory cell is a 0-channel transistor Q. , ~Q1. . and p-channel transistors QIIll+Qs+a.

Note that these transistors Q, 115 + Q, ++e are n-channel transistors Qll? r Q, ++s
It also operates when the write circuit is operated by r Q, tz+. Also, this transistor QII5 s QIea
The above-mentioned low voltage is applied to the drain of . n channel (・ransistor Qth tr Q114 r Qrz
o and p-channel'' transistor Qnt + QI
ear Q119 is a circuit that further amplifies the memory signal amplified by the sense amplifier and outputs the signal (28) to the out line. This amplifier circuit also operates at the low voltage mentioned above. Word line W drive circuit
Channel transistor Q, +tIl* (J+t., p
It consists of a channel transistor Q+ts + (J+□) and a decoder circuit, TK. This word line drive circuit also outputs a low voltage. Note that the data line.

D precharge circuit 1rlp channel transistor Q
It is constructed of InI-QIos and supplies a low voltage to the data line.

Next, the operation of the circuit shown in FIG. 4 will be explained using the timing pulse waveform of FIG. 5, mainly focusing on the memory read operation.

The φIJQ signal is set to a low potential from a high frost level, and the data line is
D is precharged into the circuit to a lower voltage limited than LK. Next, the φPIG signal is raised from a low potential to a high potential to end the memory's standby state. After this, select decoder J, and transistor Q of the word line drive circuit, +24 + Q
The gate potential of Iea is set to a low potential. Next, φ1. The signal is set to a low potential, and the low voltage is applied to the transistor Q, 2spQ1.
24 to the word line W (29). Accordingly, the transistor Q of the memory cell,
lO4t Q r Of is turned on, and the memory signal is output to the data line D. Thereafter, the φS signal is set to a high potential, the sense amplifier is operated, and the memory signal is amplified. At this time, the data line D is separated into high potential and low potential, but if the data line l/pel on the high potential side falls below the precharge level, the transistor Qllllr
A circuit using QIea raises the potential to the precharge level. This amplified signal is transmitted to transistor Q1,1
~Q, further amplified by a circuit constituted by 114.

Next, by setting the φy times signal to a high potential and the φY times signal to a low potential, the amplified signal is output to the Dout line. The read operation has been described above, but the write operation is performed as follows. The transistor Qll? uses the din and din signals as complementary signals. + QIea, then φy
If the signal is doubled in potential, the data line, D, and dln.

Separates into high potential and low potential depending on the dln signal.

At this time, if the potential of the word line W is set to a high potential 17, a signal can be written into the memory cell. (30) When the data line is separated into high potential and low potential, if the level on the high potential side is reduced to 1- as in the case of sense amplifier operation, the precharge level can be changed using a circuit using transistors Q++a + Q++a. Increase the potential.

〔Effect of the invention〕

As explained above, when applied to data lines and word lines,
By setting the width and voltage to a voltage lower than the externally applied power supply voltage, the dimensions of the transistors constituting the memory array can be reduced and high integration can be achieved. Furthermore, since the voltage used to hold data in the memory cell is low, power consumption can be reduced.

[Brief explanation of drawings]

FIG. 1 is a drawing explaining the prior art, FIG. 2 is an embodiment of the dynamic memory of the present invention, FIG. 3 is a timing pulse waveform used in the embodiment shown in FIG. 2, and FIG. 4 is a static memory of the present invention. Embodiment Regarding Memory, FIG. 5 shows timing pulse waveforms used in the embodiment shown in FIG. 1...Memory array circuit, 2...Interface peripheral circuit, 3
...(31) (32) 陀 IJ1禮 1゜ミ 4 S 連 J S Sχ
4 Go to figure 5 -

Claims (1)

[Claims] 1. In a memory circuit in which the entire large-scale integrated circuit operates at a high external power supply voltage even if the main element is a fine transistor, a circuit group including an external interface circuit that requires a high withstand voltage can operate directly at the external power supply voltage. The memory array-related circuits, which are composed of large-sized transistors and require high density, are large-scale integrated circuits composed of microscopic transistors that operate on an internal power supply whose voltage is lowered by an on-chip voltage limiter. 2. The large-scale integrated circuit according to claim 1, which operates based on a method in which memory cells are selected after precharging the data line, and the precharging voltage is lower than the externally applied voltage. 3. The large-scale integrated circuit according to claim 1, wherein the word line voltage is set to be higher than the sum of the data line voltage at the time of rewriting or writing and the threshold voltage of the MOS transistor.