JPS59112489A - Ic memory - Google Patents
Ic memoryInfo
- Publication number
- JPS59112489A JPS59112489A JP57220652A JP22065282A JPS59112489A JP S59112489 A JPS59112489 A JP S59112489A JP 57220652 A JP57220652 A JP 57220652A JP 22065282 A JP22065282 A JP 22065282A JP S59112489 A JPS59112489 A JP S59112489A
- Authority
- JP
- Japan
- Prior art keywords
- speed
- low
- memory
- output
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 (a) 発明の技術分野 本発明はICメモリにおける出力機能の改良に関する。[Detailed description of the invention] (a) Technical field of the invention The present invention relates to improvements in output functionality in IC memories.
(b) 技術の背景
近年半導体技術の発達に伴い優れたIC特にICメモリ
が廉価に提供されるようになった。(b) Background of the Technology In recent years, with the development of semiconductor technology, excellent ICs, especially IC memories, have become available at low prices.
ICメモリの市場価格は本来需要供給のバランスの上に
形成されるが、製造側にお−ける量産効果の要因による
低価格化が極めて大きい。従って製造対象となるIce
種が限定され、割合に短年月の経過であっても次第に新
品種に置換えられ、同一容量においても通常はより高速
動作の改良品種が提供されて旧品種は採算割れのため製
造中止となシ入手出来ない場合がしばしば存在する。一
方情報処理システムを始めとして広い分野で種々の装置
における制御機能を小形、高信頼且多様化する手段とし
て例えばマイクロプロセッサとICメモリおよびソフト
ウェアの組合せに置換えるいわゆる電子化の傾向にある
。そしてこれ等の電子化回路における動作速度通常同期
方式によるサイクルタイムは広範囲に亘る。Although the market price of IC memory is originally determined based on the balance between supply and demand, the price has been significantly lowered due to mass production effects on the manufacturer's side. Therefore, Ice to be manufactured
The varieties are limited, and even over a relatively short period of time, they are gradually replaced by new varieties, and even with the same capacity, improved varieties with faster operation are usually provided, and the old varieties are discontinued because they are unprofitable. There are often cases where it is not available. On the other hand, in a wide range of fields including information processing systems, there is a trend toward so-called computerization, in which control functions in various devices are replaced with a combination of a microprocessor, IC memory, and software, for example, as a means of making the control functions of various devices more compact, highly reliable, and diversified. The cycle time of these electronic circuits due to the normal synchronized operating speed ranges over a wide range.
(C) 従来技術と問題点
通常ICメモリの高速化は上記の電子化回路例えばデー
タ処理システムの機能向上をもたらす点で好ましく、ラ
イトサイクルについてはICメモリに堰込んだデータの
ICメモリ内部における処理速度が早くなることで関連
回路に悪影響を及ぼすことはない。然しリードサイクル
については高速化ICメモリを入手の都合によって例え
ば補修のため旧設計の低速回路に適用する場合単純に置
換するのには不具合を生じる0第1図に従来におけるI
Cメモリ回路のブロック図および第2図に従来における
低速および高速ICメモリ使用時のタイムチャートを示
す。(C) Prior art and problems Normally, increasing the speed of IC memory is preferable in that it improves the functionality of the above-mentioned electronic circuits, such as data processing systems. Regarding write cycles, the processing of data stored in IC memory within IC memory is desirable. The increased speed does not adversely affect related circuits. However, regarding the read cycle, due to the availability of high-speed IC memory, for example, when applying it to a low-speed circuit of an old design for repair purposes, it may be difficult to simply replace it. Figure 1 shows the conventional IC memory.
A block diagram of a C memory circuit and a time chart when conventional low-speed and high-speed IC memories are used are shown in FIG.
図において1はICメモリ、2はラッチ回路である。In the figure, 1 is an IC memory, and 2 is a latch circuit.
遅いリードサイクルタイムtRcを持つICメモリ1の
リードサイクルにおいてアドレス信号ADD。Address signal ADD in the read cycle of IC memory 1 with slow read cycle time tRc.
〜mを印加してその出力データDoutaの立上り即ち
アドレスアクセスタイムtAA、立下り即ち次サイクル
アドレスからのデータホールドタイムtOHが得られる
とすれば通常この出力データl)□utaを受信してラ
ッチ回路2にストローブクロックCT、KSを印加しラ
ッチさせるタイミングtcはtAA−dtc(tRc
+to)Iに設定される。こ′1で図示省略したがより
高速のリードサイクルタイムt+tc’を持つ別のIC
メモリを従来の遅い回路に適用しようとすれば高速IC
メモリのアドレスアクセスタイムtAA′<jAA、デ
ータホールドタイムtoH’(toHとなりストローブ
クロックCLKSのタイミングtcが第2図(C)対(
2)のようにずれて了いそのit適用出来なくなる欠点
があった。~m is applied to obtain the rising edge of the output data Douta, that is, the address access time tAA, and the falling edge, that is, the data hold time tOH from the next cycle address. Normally, upon receiving this output data l)□uta, the latch circuit The timing tc for applying strobe clocks CT and KS to 2 and latching is tAA-dtc(tRc
+to)I. Although not shown in this '1, there is another IC with a faster read cycle time t+tc'.
If you want to apply memory to conventional slow circuits, high-speed ICs
Memory address access time tAA'<jAA, data hold time toH'(toH), and timing tc of strobe clock CLKS is as shown in FIG. 2(C) vs.
As in 2), there was a drawback that it could not be applied due to deviation.
(d) 発明の目的
本発明の目的はこの欠点を除去するため高速ICメモリ
にあって従来の遅いICメモリに置換えても容易に対応
出来るよう高低速切換回路を有するICメモリを提供し
ようとするものである。(d) Object of the Invention In order to eliminate this drawback, the object of the present invention is to provide a high-speed IC memory having a high-speed and low-speed switching circuit so that it can be easily replaced with a conventional slow IC memory. It is something.
(e) 発明の構成
この目的はメモリセルアレイよυの出力信号を3−
バッファする出力部に別途高低速切替の設定に伴い正相
または逆相信号を出力するバッファ/インバータ回路、
高速出力信号をバッファする否定論理和によるゲート回
路および低速出力信号をバッファする信号遅延手段と否
定論理和よりなるゲート回路を備えてなり、前記バッフ
ァ/インバータ回路をして設定する高低速切替に従い両
ゲート回路の何れか一方を選択して高速または低速によ
る出力信号を送出せしめることを特徴とするICメモリ
を提供することによって達成することが出来る0
(f) 発明の実施例
以下図面を参照しつ\本発明の一実施例について説明す
る。)
第3図は本発明の一実施例におけるICメモリによるブ
ロック図および第4図はその出力部における具体化例ブ
ロック図である。図において1aはICメモリ、2はラ
ンチ回路、SWはスイッチ、Rは抵抗更にBUFF/I
NVはバッファ/インバータ、N0R1,N0R2は否
定論理和回路、INV4−
はインバータおよびRpは抵抗である1、本発明の一実
施例では従来の1出力のバッファ回路に代えて高低速設
定手段こ\ではスイッチSWオフは高速、オンは低速に
よって出力信号を選択設定したが、実用としてはスイッ
チSWは必要なく例えば入力端子INHLを開放または
抵抗Rを介してVEgに固定接続するか、あるいは必要
によっては低レベルまたは高レベル電位を与えてもよい
。(e) Structure of the Invention The purpose of this invention is to provide a buffer/inverter circuit that outputs a positive phase or negative phase signal according to the setting of high/low speed switching to the output section that buffers the output signal of the memory cell array.
The gate circuit is equipped with a gate circuit based on NOR for buffering high-speed output signals, a gate circuit consisting of signal delay means and NOR for buffering low-speed output signals, and the buffer/inverter circuit is configured to perform high-speed and low-speed switching according to the high-low speed switching set. This can be achieved by providing an IC memory characterized in that either one of the gate circuits is selected to send out an output signal at a high speed or a low speed. \One embodiment of the present invention will be described. ) FIG. 3 is a block diagram of an IC memory according to an embodiment of the present invention, and FIG. 4 is a block diagram of an embodiment of the output section thereof. In the figure, 1a is an IC memory, 2 is a launch circuit, SW is a switch, R is a resistor, and BUFF/I
NV is a buffer/inverter, N0R1 and N0R2 are NOR circuits, INV4- is an inverter, and Rp is a resistor1.In one embodiment of the present invention, a high/low speed setting means is used in place of the conventional one-output buffer circuit. In this case, the output signal is selected and set by turning the switch SW OFF at high speed and turning ON at low speed. However, in practical use, the switch SW is not necessary. For example, the input terminal INHL may be left open or fixedly connected to VEg via the resistor R, or if necessary. A low level or high level potential may be applied.
このようにすればSWオフ相当時はN0R1が選択され
てメモリセルアレイの出力はN0R1をバッファとして
出力され第2図(C)データ出力fJ)o u t b
のタイミング、SWオン相当時にはN0R2が選択され
更にN0R2の出力はこ\ではINVe経由することで
予め設定された遅延を受けて第2図(b)のデータ出力
po u t aのタイミングによJICメモリ1aの
出力信号が得られる。尚上記は、否定論理和回路NOR
を基本として構成したが論理和/積回路(ANDloR
)にても同様に構成出来ることはいう迄もない。In this way, when the SW is off, N0R1 is selected and the output of the memory cell array is output using N0R1 as a buffer.
When the timing corresponds to SW ON, N0R2 is selected, and furthermore, the output of N0R2 is transmitted via INVe, receives a preset delay, and is output to JIC according to the data output po ut a timing in Figure 2 (b). The output signal of memory 1a is obtained. Note that the above is a negative OR circuit NOR
It was configured based on the logical sum/product circuit (ANDloR
) can also be constructed in the same way.
(g) 発明の効果
以上説明したように本発明によればICメモリの出力部
における高低切替入力端子T’1sJHLの操作によっ
て高速または低速側れか任意のデータ出力が得られるの
で低速から高速に亘る広い動作速度範囲に容易に対応出
来るので有用である6(g) Effects of the Invention As explained above, according to the present invention, by operating the high/low switching input terminal T'1sJHL in the output section of the IC memory, any data output can be obtained from the high speed side or the low speed side. It is useful because it can easily handle a wide operating speed range6.
第1図は従来におけるICメモリ回路のブロック図、第
2図は従来における低速および高速ICメモリ使用時の
タイムチャート、@3図は本発明の一実施例におけるI
Cメモリ回路のブロック図、第4図はその出力部におけ
る具体化例ブロック図を示す。
図において1,1aはICメモリ、2はラッチ回路RU
F’F/INVはバッファインバータ、N0Rt。
N0R2は否定論理和回路およびINVはインバータで
ある。Fig. 1 is a block diagram of a conventional IC memory circuit, Fig. 2 is a time chart when using conventional low-speed and high-speed IC memories, and Fig. 3 is an I/O diagram of an embodiment of the present invention.
FIG. 4 shows a block diagram of an embodiment of the C memory circuit at its output section. In the figure, 1 and 1a are IC memories, and 2 is a latch circuit RU.
F'F/INV is a buffer inverter, N0Rt. N0R2 is a NOR circuit and INV is an inverter.
Claims (1)
に別途高低速切替の設定に伴い正相または逆相信号を出
力するバッファ/インバータ回路。 高速出力信号をバッファする否定論理和によるゲート回
路および低速出力信号をバッファする信号遅延手段と否
定論理和よりなるゲート回路を備えてなり、前記バッフ
ァ/インバータ回路をして設定する高低速切替に従い両
ゲート回路の何れか一方を選択して高速または低速によ
る出力信号を送出せしめることを特徴とするICメモリ
。 1ニー″ 2−;。[Claims] A buffer/inverter circuit that outputs a positive phase or negative phase signal to an output section that buffers an output signal from a memory cell array according to a separate setting for high/low speed switching. The gate circuit is equipped with a gate circuit based on NOR for buffering high-speed output signals, a gate circuit consisting of signal delay means and NOR for buffering low-speed output signals, and the buffer/inverter circuit is configured to perform high-speed and low-speed switching according to the high-low speed switching set. An IC memory characterized in that either one of the gate circuits is selected to send out a high-speed or low-speed output signal. 1 knee''2-;.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57220652A JPS59112489A (en) | 1982-12-16 | 1982-12-16 | Ic memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57220652A JPS59112489A (en) | 1982-12-16 | 1982-12-16 | Ic memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59112489A true JPS59112489A (en) | 1984-06-28 |
Family
ID=16754321
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57220652A Pending JPS59112489A (en) | 1982-12-16 | 1982-12-16 | Ic memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59112489A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4574469A (en) * | 1984-09-14 | 1986-03-11 | Motorola, Inc. | Process for self-aligned buried layer, channel-stop, and isolation |
US4583282A (en) * | 1984-09-14 | 1986-04-22 | Motorola, Inc. | Process for self-aligned buried layer, field guard, and isolation |
-
1982
- 1982-12-16 JP JP57220652A patent/JPS59112489A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4574469A (en) * | 1984-09-14 | 1986-03-11 | Motorola, Inc. | Process for self-aligned buried layer, channel-stop, and isolation |
US4583282A (en) * | 1984-09-14 | 1986-04-22 | Motorola, Inc. | Process for self-aligned buried layer, field guard, and isolation |
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