JPS59111533U - Handbag handle attachment - Google Patents
Handbag handle attachmentInfo
- Publication number
- JPS59111533U JPS59111533U JP633883U JP633883U JPS59111533U JP S59111533 U JPS59111533 U JP S59111533U JP 633883 U JP633883 U JP 633883U JP 633883 U JP633883 U JP 633883U JP S59111533 U JPS59111533 U JP S59111533U
- Authority
- JP
- Japan
- Prior art keywords
- fitting
- handbag
- handle attachment
- hole
- abutment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Landscapes
- Purses, Travelling Bags, Baskets, Or Suitcases (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図及び第２図は本考案の使用状態を示す斜視図、第
３図及び第４図は第１図及び第２図の要部拡大横断面図
、第５図は本考案の分解斜面図。
１・・・・・・手提鞄の蓋、２・・・・・・当接金具、
３・・・・・・取付部材、４・・・・・・結合手段、５
・・・・・・突起状筒部、６・・・・・・座部、７．９
・・・・・・取付孔、８・・・・・・嵌入孔、１０・・
・・・・鋲着。Figures 1 and 2 are perspective views showing the present invention in use, Figures 3 and 4 are enlarged cross-sectional views of the main parts of Figures 1 and 2, and Figure 5 is an exploded slope view of the present invention. figure. 1... Handbag lid, 2... Contact metal fittings,
3...Mounting member, 4...Coupling means, 5
...Protruding tube part, 6... Seat part, 7.9
...Mounting hole, 8...Fitting hole, 10...
...Racked.
Claims (1)
下面に重ねる一対の取付部材３と、前記型なり状態を結
合する結合手段４とから成る手提鞄の提手取付具におい
て、前記取付部材としては一端の突起状筒部ど他端の重
層状態の座部６とを゛ 一体形成し、また座部には取
付孔７を形成し、当接金具２としては前記筒部５を嵌入
する嵌入孔８並びに取付孔９を対設し、前記嵌入孔８に
筒部５を嵌入したる後、当接金具２と取付部材３と蓋１
を鋲着１０した手提鞄の提手取付具。A handle attachment for a handbag, which comprises an abutment fitting 2 that is placed on the lid 1 of the handbag, a pair of attachment members 3 that are placed on the lower surface of the abutment fitting 2, and a connecting means 4 that connects the shaped state. As the mounting member, a protruding cylindrical portion at one end and a seat portion 6 in a multilayered state at the other end are integrally formed, and a mounting hole 7 is formed in the seat portion. A fitting hole 8 into which the fitting 5 is inserted and a mounting hole 9 are provided oppositely, and after fitting the cylindrical portion 5 into the fitting hole 8, the abutment fitting 2, the mounting member 3 and the lid 1 are fitted.
Handbag handle attachment with 10 rivets attached.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP633883U JPS59111533U (en) | 1983-01-19 | 1983-01-19 | Handbag handle attachment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP633883U JPS59111533U (en) | 1983-01-19 | 1983-01-19 | Handbag handle attachment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59111533U true JPS59111533U (en) | 1984-07-27 |
Family
ID=30137896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP633883U Pending JPS59111533U (en) | 1983-01-19 | 1983-01-19 | Handbag handle attachment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59111533U (en) |
Cited By (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6868476B2 (en) | 2001-08-27 | 2005-03-15 | Intel Corporation | Software controlled content addressable memory in a general purpose execution datapath |
| US6876561B2 (en) | 1999-12-28 | 2005-04-05 | Intel Corporation | Scratchpad memory |
| US6895457B2 (en) | 1999-12-28 | 2005-05-17 | Intel Corporation | Bus interface with a first-in-first-out memory |
| US6934951B2 (en) | 2002-01-17 | 2005-08-23 | Intel Corporation | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section |
| US6941438B2 (en) | 2003-01-10 | 2005-09-06 | Intel Corporation | Memory interleaving |
| US6976095B1 (en) | 1999-12-30 | 2005-12-13 | Intel Corporation | Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch |
| US6983350B1 (en) | 1999-08-31 | 2006-01-03 | Intel Corporation | SDRAM controller for parallel processor architecture |
| US7020871B2 (en) | 2000-12-21 | 2006-03-28 | Intel Corporation | Breakpoint method for parallel hardware threads in multithreaded processor |
| US7107413B2 (en) | 2001-12-17 | 2006-09-12 | Intel Corporation | Write queue descriptor count instruction for high speed queuing |
| US7126952B2 (en) | 2001-09-28 | 2006-10-24 | Intel Corporation | Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method |
| US7149226B2 (en) | 2002-02-01 | 2006-12-12 | Intel Corporation | Processing data packets |
| US7158964B2 (en) | 2001-12-12 | 2007-01-02 | Intel Corporation | Queue management |
| US7181573B2 (en) | 2002-01-07 | 2007-02-20 | Intel Corporation | Queue array caching in network devices |
| US7181594B2 (en) | 2002-01-25 | 2007-02-20 | Intel Corporation | Context pipelines |
| US7191321B2 (en) | 1999-08-31 | 2007-03-13 | Intel Corporation | Microengine for parallel processor architecture |
| US7216204B2 (en) | 2001-08-27 | 2007-05-08 | Intel Corporation | Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment |
| US7225281B2 (en) | 2001-08-27 | 2007-05-29 | Intel Corporation | Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms |
| US7269179B2 (en) | 2001-12-18 | 2007-09-11 | Intel Corporation | Control mechanisms for enqueue and dequeue operations in a pipelined network processor |
| US7305500B2 (en) | 1999-08-31 | 2007-12-04 | Intel Corporation | Sram controller for parallel processor architecture including a read queue and an order queue for handling requests |
| US7328289B2 (en) | 1999-12-30 | 2008-02-05 | Intel Corporation | Communication between processors |
| US7337275B2 (en) | 2002-08-13 | 2008-02-26 | Intel Corporation | Free list and ring data structure management |
| US7352769B2 (en) | 2002-09-12 | 2008-04-01 | Intel Corporation | Multiple calendar schedule reservation structure and method |
| US7421572B1 (en) | 1999-09-01 | 2008-09-02 | Intel Corporation | Branch instruction for processor with branching dependent on a specified bit in a register |
| US7434221B2 (en) | 1999-12-30 | 2008-10-07 | Intel Corporation | Multi-threaded sequenced receive for fast network port stream of packets |
| US7433307B2 (en) | 2002-11-05 | 2008-10-07 | Intel Corporation | Flow control in a network environment |
| US7437724B2 (en) | 2002-04-03 | 2008-10-14 | Intel Corporation | Registers for data transfers |
| US7443836B2 (en) | 2003-06-16 | 2008-10-28 | Intel Corporation | Processing a data packet |
| US7471688B2 (en) | 2002-06-18 | 2008-12-30 | Intel Corporation | Scheduling system for transmission of cells to ATM virtual circuits and DSL ports |
| US7480706B1 (en) | 1999-12-30 | 2009-01-20 | Intel Corporation | Multi-threaded round-robin receive for fast network port |
| US7487505B2 (en) | 2001-08-27 | 2009-02-03 | Intel Corporation | Multithreaded microprocessor with register allocation based on number of active threads |
| US7610451B2 (en) | 2002-01-25 | 2009-10-27 | Intel Corporation | Data transfer mechanism using unidirectional pull bus and push bus |
| US7620702B1 (en) | 1999-12-28 | 2009-11-17 | Intel Corporation | Providing real-time control data for a network processor |
| US9128818B2 (en) | 1999-12-27 | 2015-09-08 | Intel Corporation | Memory mapping in a processor having multiple programmable units |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5648821B2 (en) * | 1978-02-08 | 1981-11-18 |
-
1983
- 1983-01-19 JP JP633883U patent/JPS59111533U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5648821B2 (en) * | 1978-02-08 | 1981-11-18 |
Cited By (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6983350B1 (en) | 1999-08-31 | 2006-01-03 | Intel Corporation | SDRAM controller for parallel processor architecture |
| US7191321B2 (en) | 1999-08-31 | 2007-03-13 | Intel Corporation | Microengine for parallel processor architecture |
| US7305500B2 (en) | 1999-08-31 | 2007-12-04 | Intel Corporation | Sram controller for parallel processor architecture including a read queue and an order queue for handling requests |
| US7424579B2 (en) | 1999-08-31 | 2008-09-09 | Intel Corporation | Memory controller for processor having multiple multithreaded programmable units |
| US7421572B1 (en) | 1999-09-01 | 2008-09-02 | Intel Corporation | Branch instruction for processor with branching dependent on a specified bit in a register |
| US9128818B2 (en) | 1999-12-27 | 2015-09-08 | Intel Corporation | Memory mapping in a processor having multiple programmable units |
| US7620702B1 (en) | 1999-12-28 | 2009-11-17 | Intel Corporation | Providing real-time control data for a network processor |
| US6895457B2 (en) | 1999-12-28 | 2005-05-17 | Intel Corporation | Bus interface with a first-in-first-out memory |
| US6876561B2 (en) | 1999-12-28 | 2005-04-05 | Intel Corporation | Scratchpad memory |
| US7480706B1 (en) | 1999-12-30 | 2009-01-20 | Intel Corporation | Multi-threaded round-robin receive for fast network port |
| US7434221B2 (en) | 1999-12-30 | 2008-10-07 | Intel Corporation | Multi-threaded sequenced receive for fast network port stream of packets |
| US6976095B1 (en) | 1999-12-30 | 2005-12-13 | Intel Corporation | Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch |
| US7328289B2 (en) | 1999-12-30 | 2008-02-05 | Intel Corporation | Communication between processors |
| US7020871B2 (en) | 2000-12-21 | 2006-03-28 | Intel Corporation | Breakpoint method for parallel hardware threads in multithreaded processor |
| US7487505B2 (en) | 2001-08-27 | 2009-02-03 | Intel Corporation | Multithreaded microprocessor with register allocation based on number of active threads |
| US6868476B2 (en) | 2001-08-27 | 2005-03-15 | Intel Corporation | Software controlled content addressable memory in a general purpose execution datapath |
| US7216204B2 (en) | 2001-08-27 | 2007-05-08 | Intel Corporation | Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment |
| US7225281B2 (en) | 2001-08-27 | 2007-05-29 | Intel Corporation | Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms |
| US7246197B2 (en) | 2001-08-27 | 2007-07-17 | Intel Corporation | Software controlled content addressable memory in a general purpose execution datapath |
| US7126952B2 (en) | 2001-09-28 | 2006-10-24 | Intel Corporation | Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method |
| US7158964B2 (en) | 2001-12-12 | 2007-01-02 | Intel Corporation | Queue management |
| US7107413B2 (en) | 2001-12-17 | 2006-09-12 | Intel Corporation | Write queue descriptor count instruction for high speed queuing |
| US7269179B2 (en) | 2001-12-18 | 2007-09-11 | Intel Corporation | Control mechanisms for enqueue and dequeue operations in a pipelined network processor |
| US7181573B2 (en) | 2002-01-07 | 2007-02-20 | Intel Corporation | Queue array caching in network devices |
| US6934951B2 (en) | 2002-01-17 | 2005-08-23 | Intel Corporation | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section |
| US7302549B2 (en) | 2002-01-17 | 2007-11-27 | Intel Corporation | Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access |
| US7610451B2 (en) | 2002-01-25 | 2009-10-27 | Intel Corporation | Data transfer mechanism using unidirectional pull bus and push bus |
| US7181594B2 (en) | 2002-01-25 | 2007-02-20 | Intel Corporation | Context pipelines |
| US7149226B2 (en) | 2002-02-01 | 2006-12-12 | Intel Corporation | Processing data packets |
| US7437724B2 (en) | 2002-04-03 | 2008-10-14 | Intel Corporation | Registers for data transfers |
| US7471688B2 (en) | 2002-06-18 | 2008-12-30 | Intel Corporation | Scheduling system for transmission of cells to ATM virtual circuits and DSL ports |
| US7337275B2 (en) | 2002-08-13 | 2008-02-26 | Intel Corporation | Free list and ring data structure management |
| US7352769B2 (en) | 2002-09-12 | 2008-04-01 | Intel Corporation | Multiple calendar schedule reservation structure and method |
| US7433307B2 (en) | 2002-11-05 | 2008-10-07 | Intel Corporation | Flow control in a network environment |
| US6941438B2 (en) | 2003-01-10 | 2005-09-06 | Intel Corporation | Memory interleaving |
| US7418571B2 (en) | 2003-01-10 | 2008-08-26 | Intel Corporation | Memory interleaving |
| US7443836B2 (en) | 2003-06-16 | 2008-10-28 | Intel Corporation | Processing a data packet |
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