JPS59111533A - Digital data calculation circuit - Google Patents

Abstract

PURPOSE:To accelerate the arithmetic speed by dividing a memory part into plural groups to write the data read out by a command to the memory part of a group and the data on the arithmetic result to the memory part of the other group respectively. CONSTITUTION:The data read out by a command is written to a memory part of one of plural divided groups of memories along with the data on arithmetic result written to a memory of the other group respectively. Thus the data is read and written at a time. For instance, the data D2 is read out of a designated address of a memory element 2 and held at an input holding part 5 together with the input data D4 to be calculated. Then data D5 and D7 are supplied to an arithmetic device 4 to perform an operation. The data D3 calculated by the device 4 is held at an output holding part 6, and at the same time the device 4 is replaced for the next calculation. Then the data D6 on the arithmetic result held at the part 6 is stored in a memory element 7. Meanwhile the replaced data is supplied to the device 4 to give an operation to the next replaced data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a digital data arithmetic circuit, and particularly relates to a digital data arithmetic circuit suitable for using digital data stored in a memory section as various arithmetic data. .

[Prior art]

2. Description of the Related Art When performing various calculations based on digital data, it has been conventional practice to use digital data stored in a memory section made up of storage elements. When such arithmetic processing is classified based on function, it can be divided into the following two types.

(1) The purpose is to preserve data before and after calculation.

(2) The purpose is to increase the speed of arithmetic processing.

An example of (1) is a so-called general-purpose computer.
An example of (2) is a digital image measurement circuit.

(For example, as shown in FIGS. 1 and 2, for example, the signal P1 of the program data D1 output from a predetermined program medium is output from timing T1 to
It is decoded at T4, and address setting of the storage element 2.3 is performed at timing T4 using control signals CI and C2. The addresses of the memory elements 2.3 are determined by the signals P2.3, respectively. P
The settings are as shown in 7. At this time, a read permission signal P3, a write permission signal P8, etc. are also set.

The signal P4 of the data D2 output from the storage element 2 is established near timing T5. At this time, since the signal P5 of the other calculation input data D4 has already been established around timing T4, these two data signals are supplied to the calculation unit 4 and are established as the calculation result data D3 around timing T6. Ru. Subsequently, data D3 is stored in storage element 3 by write permission signal P8 until timing T7.

In this way, in the arithmetic processing circuit shown in FIG.
Memory elements 2.3 can store data before and after operation, respectively. However, in the case of the arithmetic processing circuit shown in FIG. 1, the arithmetic processing process always includes instruction decoding time T1 to T4, and the arithmetic processing process requires time from timings T1 to T4. Therefore, from the viewpoint of processing speed, it is difficult to apply the above-mentioned arithmetic circuit to an image measurement circuit or the like in which simple repetitive arithmetic operations are performed.

Therefore, an arithmetic circuit that does not require time for decoding timings T1 to T4 has been proposed. This arithmetic circuit is
For example, it is shown in FIG. 3, and is calculated according to the procedure shown in FIG.

That is, the address of the storage element 2 is specified at timing T4, data D2 is read out as a signal pH by read permission signal PIO, and is established around timing T5.

At this time, the input data holding signal P13 is held in the input holding section 5 together with the input data D4 to be operated on. Note that the memory element 2 is enabled to write data by the write permission signal P17.

Data D5. output from input holding unit 5. D7 is simultaneously supplied to the arithmetic unit 4, where a predetermined arithmetic operation is performed and output as data D3. The signal P14 of this data D3 is established near timing T6.

Then, the data D3 is stored in the storage element 2 by the write permission signal P17.

In this way, in the case of the arithmetic circuit shown in FIG. 3, the processing time of timings T1 to T4 for decoding data is not required, so the total calculation time is significantly shorter than that of the arithmetic circuit shown in FIG. Can be shortened.

However, to process one group of data, timing T4~
Since this method requires a time of T7, there is an inconvenience that the scope of its use is limited even if it is applied to image measurement that requires high-speed data processing.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to provide a digital data calculation circuit that can shorten the time required to calculate digital data.

[Summary of the invention]

In order to achieve the above object, the present invention includes a memory unit that stores digital data, and an arithmetic unit that operates on the digital data according to a command, and the digital data given by the command is read out from the memory unit. In the digital arithmetic circuit that calculates the calculated digital data and stores the calculated digital data in the memory section, the memory section is divided into at least two groups, and the memory section of one group has a memory section that is read out according to a command. The digital data is stored, and the digital data of the calculation result is written to the memory section of the other group.
It is characterized by reading and writing digital data in parallel.

[Embodiments of the invention]

Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

FIG. 5 shows the configuration of a preferred embodiment of the present invention. In FIG. 5, the arithmetic circuit in this embodiment has two
It is composed of storage elements 2 and 7, an input holding section 5, an arithmetic unit 4, and an output holding section 6, which constitute a memory section divided into groups.

In the arithmetic circuit shown in FIG. 5, the address of the storage element 2 is designated at timing T4, as shown in FIG.
Data D2 is read by read permission signal P19. Next, at timing T5, this data D2 is held in the input holding unit 5 along with the input data D4 to be operated by the input holding signal P22, and the data D5. It is supplied as D7 and the calculation is started. After this, the input holding section 5 becomes able to update the input data, and the next data is read out after timing T5.

The data supplied to the arithmetic unit 4 is established near the middle between timings T4 and T5, and is held in the output holding section 6 as data D3 by the output holding signal P24. At this time, the arithmetic unit 4 waits for updated data to be supplied from the input holding section 5 until the next arithmetic operation is possible.

On the other hand, data D6 of the calculation result held in the output holding unit 6
is stored in the memory element 7 at timing T6 to T7. Timing T6 when data D6 is stored in storage element 7
The updated data is supplied to the computing unit 4 between T7 and T7, and the next updated data is computed.

As described above, in this embodiment, data reading and writing are performed in parallel, so if we focus on the operation of the arithmetic unit 4, we can see that two calculations are performed between timings T4 and T7. become. Therefore, the calculation processing time can be reduced to 172 times compared to the case of the calculation circuit shown in FIG.

Note that the flow of data when performing an operation using the same address is in the order of storage element 7 -> input holding section 5 -> arithmetic unit 4 -> output holding section 6 -> storage element 2.

In addition, when the arithmetic circuit in this example was applied to an automatic blood image classification device to determine the arithmetic processing speed for red blood cell classification and reticulocyte calculation, it was found that in the case of the conventional arithmetic circuit, one screen for red blood cell classification and reticulocyte calculation The processing time for each is 263
m5 and 184 m5, and the processing time of the calculation section was 207 m5 and 136 m5, respectively. On the other hand, in the case of the arithmetic processing circuit in this embodiment, the calculation time by the arithmetic unit is 103.5 mS and 68 m8, respectively.
The total processing speed for one screen is 163.5 mS and 116 mS, respectively.
It became m5. Further, according to the processing arithmetic circuit in this embodiment, the processing time for red blood cell classification and reticulocyte calculation is 47.
8%.

This can be reduced to 47%.

〔Effect of the invention〕

As explained above, according to the present invention, digital
The memory section for storing digital data is divided into at least two groups, the read digital data is stored in the memory section of one group, the digital data of the calculation result is written in the memory section of the other group, and the digital data is stored in the memory section of the other group. Since reading and writing of data are performed in parallel, there is an excellent effect that the total calculation processing time can be reduced compared to the case of an arithmetic circuit in which reading and writing of digital data are performed alternately.

[Brief explanation of drawings]

Figures 1 and 3 are conventional circuit configuration diagrams, Figures 2 and 4 are
Each figure is a timing chart of each circuit, FIG. 5 is a circuit configuration diagram showing one embodiment of the present invention, and FIG. 6 is a timing chart of FIG. 5. 2.7...Storage element, 4...Arithmetic unit, 5...Input holding section, station, yIZJ static 4m P7 = Engineering===="=

Claims (1)

[Claims] 1゜ A memory section that stores digital data, a calculation section that calculates the digital data according to the command, and a calculation section that calculates the digital data given by the command and the digital data read from the memory section. In the digital data calculation circuit that stores digital data in the memory section, the memory section is divided into at least two groups,
The memory section of one group stores all the digital data read out by the command, and the memory section of the other group writes the digital data of the calculation result, and the reading and writing of the digital data is performed simultaneously. Digital data calculation circuit.