JPS59119929A - Equalizing system of circuit distortion - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (a) 1 Technical Field of the Invention The present invention relates to a line distortion equalization method for equalizing line distortion, and particularly relates to a line distortion equalization method for data transmission using an analog line. It is something.

(b), Prior art and problems Figure 1 shows that in data transmission using an analog line,
1 is a block diagram illustrating an example of a conventional technique for equalizing line distortion;

In FIG. 1, 5END represents a transmitter, REC represents a receiver, DELAY-EQL in the receiver REC represents a delay equalizer, AUTO-EQL represents an automatic equalizer, and DET represents a discriminator.

The details of one embodiment according to the prior art will be described below with reference to FIG.

Conventionally, when equalizing line distortion, the receiving unit REC measures the line distortion of the line in advance, and then manually sets the delay equalizer DELAY-EQL that adapts to the line characteristics. Furthermore, a method has been adopted in which an automatic equalizer AUTO-EQL is used to automatically equalize the line distortion that occurs thereafter.

However, the former method is time-consuming and the latter method has the disadvantage that the equalization range is limited.

(C)0Object of the invention The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art,
It is an object of the present invention to provide a method for efficiently equalizing delay distortion of a line when the line distortion changes greatly or at the time of initial setting.

According to the present invention, in a line distortion equalization method for equalizing line distortion in an analog line, a plurality of delay equalizers prepared in advance are used. Switch them sequentially and put them on the line,
The error ray Y when using the delay equalizer is measured, and based on the measurement result, the delay equalizer that can compensate for equalization by an automatic equalizer is determined and used in the actual line. This is achieved by providing a line distortion equalization method characterized by the following.

(e) 2 Embodiment of the invention FIG. 2 is a block diagram showing an embodiment of the invention.
In the figure, 5TART-5TOP is the start/stop part, SEQ is part of the sequencer, C0NT is the control judgment part, RL-DR
I VE is the relay drive unit, RL is the relay circuit, DEL
AY-EQL is a delay equalizer, a, b, and C are terminals,
A is a terminal to which a human power signal is applied, b is an output terminal, and C is a terminal to which a start signal is applied.

FIG. 3 is a sequence diagram for explaining the operation of the block diagram of FIG. 2.

Figure 4 shows the frequency r and delay time DE in an actual line.
It is a graph showing the relationship between LAY'rIME.

The present invention is a delay equalizer DELAY-EQL
When the line distortion is not properly equalized, it cannot be equalized by the own gJ equalizer, so to take advantage of the fact that synchronization is lost and more errors occur, relays are switched and the delay equalizers are scanned one after another. , the delay equalizer is automatically set by stopping scanning when sufficient equalization is achieved.

Generally, the relationship between frequency and delay distortion of a line has characteristics as shown by the solid line in FIG. 4 due to the influence of filters and the like. Therefore, prepare several delay equalizers in advance as shown by the dotted lines, and use these delay equalizers by switching them sequentially to measure the error ray 1- at that time and perform sufficient automatic equalization. This method attempts to automatically determine a delay equalizer when equalization can be converged by the equalizer (error rate is about 1/10000).

The present invention will be described in detail below with reference to FIGS. 2 and 3.

While the input signal is applied to the terminal a, the start signal is input to the start/stop section 5TART-3TOP. For this reason, the start/stop unit 5TART-5TOP starts operating and drives the sequence diagram unit SEQ.

As a result, the relay drive unit RL-DRIVE operates, and the relay circuit RL also operates, and the delay equalizer DEL A V
- A first delay equalizer housed in E Q L is connected, and the input signal applied to the a terminal is connected to this first delay equalizer.
is input to the delay equalizer. Error Ray I in this state
* is measured, and the result is input to the control determination section C0NT.

If the result is 1/10000 or more, control judgment unit C0NT
operates to drive the sequencer part SEQ, operate the relay drive unit RL-DRIVE and the relay circuit RL, and send an input signal to the second delay equalizer housed in the delay equalizer DE LΔY-EQL. is applied, the error rate is measured as before, and the result is input to the control determination section C0NT. In this way, the delay equalizer DELAY
- When n (for example, 4) delay equalizers accommodated in E When the following occurs), the control judgment unit determines the start/stop unit 5TART・5
Sends a stop signal to TOP and outputs the delay equalizer D at that point.
Retains the ELAY-EQL settings.

Once the above operations are completed, subsequent adjustments can be sufficiently converged using a conventional automatic equalizer.

(f) 9 Effects of the Invention As explained in detail above, according to the present invention, when the line distortion changes (when it changes, at the time of initial setting, etc.), the delay distortion of the line is mechanically equalized. This has the great effect of being able to be carried out both efficiently and efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a system of an embodiment according to the prior art. In FIG. 1, 5END represents a transmitter, REC represents a receiver, and D E in the receiver RIE C. LAY-EQT- is a delay equalizer, TO-EQL is an automatic equalizer, and DET is a discriminator. Fig. 2 is a production diagram showing one embodiment of the present invention.
Q is the sequence diagram section, CON T is the control judgment section, 1?
L - D R I V E is a relay drive unit, RL is a relay circuit, I) E L A Y - E Q L is a delay vase, a, b, and C are terminals, respectively, and a is a terminal to which an input signal is applied, b is an output terminal, and C is a terminal to which an activation signal is applied. FIG. 3 is a sequence diagram for explaining the operation of the block diagram of FIG. 2. Figure 4 shows the frequency f and delay time in an actual line1)
It is a graph showing the relationship between ELAYTIMB.

Claims (1)

[Claims] In a line distortion equalization method that equalizes line distortion in an analog line, an error occurs when multiple delay equalizers prepared in advance are sequentially switched and applied to the line, and the delay equalizer is used. - A line distortion equalization method characterized in that the rate is measured, and based on the measurement result, the delay equalizer that can compensate the equalizer by an automatic equalizer is determined and used for the actual line.