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JPS589360A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPS589360A
JPS589360A JP56107025A JP10702581A JPS589360A JP S589360 A JPS589360 A JP S589360A JP 56107025 A JP56107025 A JP 56107025A JP 10702581 A JP10702581 A JP 10702581A JP S589360 A JPS589360 A JP S589360A
Authority
JP
Japan
Prior art keywords
chip
thick film
wiring board
film wiring
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56107025A
Other languages
Japanese (ja)
Inventor
Satoru Yahagi
矢萩 覚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56107025A priority Critical patent/JPS589360A/en
Publication of JPS589360A publication Critical patent/JPS589360A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment

Landscapes

  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To enable the automatizing of a chip component mounting process by a method wherein conductors and resistors are printed and fired on a thick film wiring substrate, chip components are positioned in prescribed regions, and then a laser beam is applied for the formation of grooves whereat dicing is performed for the substrate to be separated into chips. CONSTITUTION:Conductors and resistors are printed and fired on a slitless ceramic substrate to be separated into a multiplicity of units for the formation of a slitless thick film wiring substrate 6 to be sectioned into a multiplicity of units. On the substrate 6, by means of a mounting machine, a multiplicity of chip type transistors 3a-3f and chip type capacitors 4a-4f are fixed. Next, by means of a laser scribing machine, separating grooves 9 are provided. Separation may be effected by further applying laser or applying bending force leading to separation. The laser beam diameter should be no more than 10mum so that chips are not affected by the beam. This setup reduces the number of manufacturing processes and realizes low price hybrid integrated circuits.

Description

【発明の詳細な説明】 本発ahチップ部品搭載後の多数個取り厚膜配線基板の
基板分割の仕方に特徴を有する混成集積回路の製造方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a hybrid integrated circuit characterized by the method of dividing a multi-chip thick film wiring board after mounting AH chip components thereon.

従来、小量の厚膜混成集積回路においては、混成集積回
路1個嶺シの印刷工数を低減するため。
Conventionally, in the case of small-volume thick film hybrid integrated circuits, this was done to reduce the number of printing steps for one hybrid integrated circuit.

次のような方法で行なってい良。すなわち、第1図に示
されているように、先ずセラミック基板1を用意し、そ
の裏[K分割用のスリット2を入れて、多数個取シセ2
ミック基板とする。次に、多数個取りセラミック基板の
表側に導体、抵抗等の印刷をし、続いて焼成およびトリ
ミングをする。
You can do it in the following way. That is, as shown in FIG.
Mic board. Next, conductors, resistors, etc. are printed on the front side of the multi-chip ceramic substrate, followed by firing and trimming.

その後、多数個取り厚膜配線基板を分割し、多数個の厚
膜配線基板を得る。
Thereafter, the multi-chip thick film wiring board is divided to obtain a large number of thick film wiring boards.

第2図の5は分割後の1個の厚膜配線基板を示す。分割
されて多数個の厚膜配線基板が得られた後、そ01個1
個にチッグ蓋トツンジスタ3Toるいはテッグ減コンデ
ンサ4を取p付けて、混成集積回路を完成する〇 とζろが、最近で社、チップ型部品の基板への取り付け
も、工数低減のため、自動化の傾向KT。
5 in FIG. 2 shows one thick film wiring board after division. After dividing and obtaining a large number of thick film wiring boards, 01 pieces 1
A hybrid integrated circuit is completed by attaching a chip lid capacitor 3To or a Tegg reduction capacitor 4 to each chip.Recently, companies have begun to automate the attachment of chip-type components to the board in order to reduce the number of man-hours. The trend of KT.

り、チップ型部品の基板への取υ付けがチップ部品の自
動搭載機(以下搭載機という)により1行なわれる様に
なってきた。チップ部品の基板への取り付けを搭載機で
行なう場合、基板としては大型の基板を用い、それにチ
ップ部品を多数搭載するようにした方が、能率も良く、
工数低減の効果が大きい。そのため、多数個取り厚膜配
線基板に適用する場合、基板分割前に、チップ部品を搭
載し先方が効率が^いのは、当然でらる〇しかし、#i
記し九スリット2が入った、多数個取C**基板を使用
し、チップ部品搭載後に基板を基板分割装置により1分
割しようとすると、現在の1&板分割装置は前記スリッ
トの近辺に大きな機械的衝撃力を与えて分割する方式で
あるため、チップ部品がじゃまになシ、又分割時の振動
によりチップ部品に故障が起り、容易にかっ歩1ilシ
良く分割することが出来なかった。
As a result, mounting of chip-type components onto a board has come to be carried out by an automatic chip component mounting machine (hereinafter referred to as a mounting machine). When attaching chip components to a board using a mounting machine, it is more efficient to use a large board and mount a large number of chip components on it.
Great effect in reducing man-hours. Therefore, when applying to a multi-chip thick film wiring board, it is natural to mount chip components before dividing the board to improve efficiency. However, #i
When using a multi-piece C** board with 9 slits 2 and trying to divide the board into 1 pieces with a board dividing device after mounting chip components, the current 1 & board dividing device has a large mechanical part near the slits. Since the method is to divide by applying an impact force, the chip parts do not get in the way, and the vibration during division causes failures in the chip parts, making it difficult to divide the chip parts easily and accurately.

このため、前記した従来技術と同様に、始めに、厚膜配
曽がなされ九多数個取り配線基板の分割を行な−)先後
、チップ部品の搭載を行なわなければならず、搭載機を
使用しても、効率の曳いテップ部品搭載の自動化ができ
ないという欠点が6つ九。
For this reason, as in the prior art described above, thick film placement is first performed and the nine-multiple wiring board is divided. Even if it is used, there are six drawbacks such as efficiency and the inability to automate the installation of tip parts.

本発明の目的は、上記し九従来技術の欠点をなくし、効
率の良いチップ部品搭載の自動化を可能とした混成集積
回路の製造方法を提供するにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a hybrid integrated circuit which eliminates the above-mentioned nine drawbacks of the prior art and enables efficient automation of chip component mounting.

以下に、図面を参照して本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.

先ず、第3I!lに示されているように、スリット無し
多数個取り上2ミック基板上に導体および抵抗を印刷・
焼成してスリツ(無し多数個取シ厚膜配線基板26を作
る。次に第4図に示されているように、第3図のスリッ
ト声ζ℃数個取り厚膜配線基板6上に、搭載機により、
チップ型ト2/ジスタ。
First, 3rd I! As shown in Figure 1, conductors and resistors are printed on a multi-cavity top 2-mic board without slits.
By firing, a thick film wiring board 26 with many slits (without slits) is made.Next, as shown in FIG. Depending on the installed machine,
Chip type To2/Jista.

3&〜31、及びテップll:!ンデンサ4&〜4fを
搭載して固定する。その後レーザスクライバ装置によp
、基板上にレーザ光を照射し、レーザ光の照射による切
断溝9を形成する。
3&~31, and step ll:! Mount and fix the capacitors 4&~4f. After that, a laser scriber device is used to
, a laser beam is irradiated onto the substrate, and a cutting groove 9 is formed by irradiating the laser beam.

この工程時におけるスリット無し多数個取抄厚膜配線基
板6の一部の拡大断面図を第5図に示す。
FIG. 5 shows an enlarged cross-sectional view of a part of the thick film wiring board 6 without slits during this step.

図において、4′はチップ型コンデンサ、7は電極バタ
ーy、8は半田、9は集束されたレーザ光照射によって
作られ九切断溝、1Gはセラミック基板である0切断溝
9はレーザ光の照射によシ、容易に任意の深さにするこ
とができる。切断溝9の深さは深くすればするほど、そ
の後の外割工糧で竜う建ツク基板を容易に分割すること
ができることは勿論である。本実施例では、セラミック
基板10にわずかな歪あるいけ一部等を与えた時に分割
される横変に切断溝9を深くする。なお、レーザ光がセ
ラミック基板10を貫通するまで、レーず光をセラミッ
ク基板に照射してもよいことは勿論で参る。畳は、その
後の分割工程で容易に分割することのできる深さKなる
まで、IV−ザ光を照射すればよい。スリット無し多数
個取り厚膜配線基板6が分割された後は、さらに別の工
程をへて混成集積回路が完成させられる〇 本実施例によれば、レーザスクライバ装置を用いている
ため、きわめて容易にセラミック基板に溝tあ妙ること
ができる。またレーザスクライバ装置から発射されてレ
ーザの径は約10/J!E1m!度と細くできるので、
チップ部品が搭載され九多数個取p厚膜配線基板ヘレー
ず光を照射してもチップ部品がじゃまになることはない
。また、基板の分11にあたって、基板に機械的振動が
殆んど加わらないで、搭載され九チップ部品が故障する
恐れはない。
In the figure, 4' is a chip type capacitor, 7 is an electrode butter y, 8 is solder, 9 is a nine cutting groove made by focused laser beam irradiation, 1G is a ceramic substrate, and 0 cutting groove 9 is a laser beam irradiation. Easy to use, can be easily made to any depth. It goes without saying that the deeper the cutting groove 9 is, the easier it will be to divide the warp building board using subsequent cutting tools. In this embodiment, the cutting grooves 9 are deepened so as to be laterally divided when a slight strain or slanted portion is applied to the ceramic substrate 10. It goes without saying that the ceramic substrate may be irradiated with laser light until the laser light penetrates the ceramic substrate 10. The tatami mat may be irradiated with IV-the light until it reaches a depth K that allows it to be easily divided in the subsequent dividing step. After the slit-less multi-piece thick film wiring board 6 is divided, a hybrid integrated circuit is completed through another process. According to this embodiment, a laser scriber device is used, so it is extremely easy. It is possible to create grooves in the ceramic substrate. Also, the diameter of the laser emitted from the laser scriber device is approximately 10/J! E1m! Because it can be made extremely thin,
Even if a multi-chip thick film wiring board with chip components mounted thereon is irradiated with light, the chip components will not get in the way. Furthermore, since almost no mechanical vibration is applied to the board, there is no risk of failure of the mounted chip components.

以上のように、本発明によれば、チップ部品搭載後であ
っても多数個取り厚膜配線基板を分割することができる
ため、多数個取り厚膜配線基板へのチップ部品搭載機の
適用が可能となシ、効率の良いチップ部品搭載工程の自
動化をはかることができる。また1本発明によれば、混
成集積回路の製造工数の低減が図れ、製造コストを下げ
ることができるという大きな効果がある。
As described above, according to the present invention, a multi-chip thick film wiring board can be divided even after chip components are mounted, so that a chip component mounting machine can be applied to a multi-chip thick film wiring board. This makes it possible to automate the chip component mounting process with high efficiency. Further, according to the present invention, the number of man-hours for manufacturing a hybrid integrated circuit can be reduced, and manufacturing costs can be reduced, which is a significant effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の多数個取シ厚膜配線基板の平面図、第2
図はチップ部品を搭載した1個の厚膜配線基板の平面図
、第3図は本発明の一実施例に便用する多数個取シ厚膜
配線基板の平面図、第4図は本発明の一実施例を説明す
るための多数個IILシ厚膜配線基板の平面図、第5図
は第4図の一部の拡大断蘭図である。 31〜3f・・・チップ型ト2ンジスタ、  4a〜4
f、4’・・・チッフ型コンデンサ、  6・・・スリ
ット無し多数個取り厚膜配線基板、  9・・・切断溝
、10・・・セラミック基板。 牙 1 霞 牙 3 図
Figure 1 is a plan view of a conventional multi-chip thick film wiring board;
The figure is a plan view of one thick film wiring board on which chip components are mounted, FIG. 3 is a plan view of a multi-chip thick film wiring board conveniently used in an embodiment of the present invention, and FIG. FIG. 5 is a plan view of a multi-IIL thick film wiring board for explaining one embodiment of the present invention, and FIG. 5 is an enlarged cross-sectional view of a part of FIG. 4. 31~3f...Chip type transistor, 4a~4
f, 4'... Chiff type capacitor, 6... Multi-chip thick film wiring board without slit, 9... Cutting groove, 10... Ceramic board. Fang 1 Kasuga 3 Figure

Claims (1)

【特許請求の範囲】[Claims] (1)−に?(ツク基板上に導体及び抵抗を印刷、焼成
することにより、少なくとも、2個以上に分割すること
のできる多数個取り厚膜配線基板を形成し、続いて該配
線基板上のチップ部品がII載されるべき箇所にチップ
部品を搭滅し、該チップ部品を固定後、前記チップ部品
の取付けられえ多数個象り厚膜配線基板にレーザ光を、
照射することによ〉、該配線基板に切断溝を形成し、誼
配線基板を個々に分割するようにし九ことを特徴とする
混成集積回路の製造方法。
(1) - to? (A multi-chip thick film wiring board that can be divided into at least two parts is formed by printing conductors and resistors on the board and firing them, and then the chip parts on the wiring board are mounted on the II board.) After mounting the chip components at the desired location and fixing the chip components, a laser beam is applied to the thick film wiring board to which a large number of the chip components are attached.
A method for manufacturing a hybrid integrated circuit, comprising: forming cutting grooves in the wiring board by irradiating the wiring board, and dividing the wiring board into individual parts.
JP56107025A 1981-07-10 1981-07-10 Manufacture of hybrid integrated circuit Pending JPS589360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56107025A JPS589360A (en) 1981-07-10 1981-07-10 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56107025A JPS589360A (en) 1981-07-10 1981-07-10 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS589360A true JPS589360A (en) 1983-01-19

Family

ID=14448603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56107025A Pending JPS589360A (en) 1981-07-10 1981-07-10 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS589360A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02250391A (en) * 1989-03-24 1990-10-08 Ngk Insulators Ltd Manufacture of ceramic board for feeding
US5337474A (en) * 1991-05-31 1994-08-16 Fuji Xerox Co., Ltd. Process for fabricating electronic devices and image sensor
WO2001057922A1 (en) * 2000-02-04 2001-08-09 Advanced Systems Automation Ltd. Method and apparatus for singulation of electronic devices
WO2002094528A1 (en) * 2001-05-24 2002-11-28 Kulicke & Soffa Investments, Inc. Dual laser cutting of wafers
KR100574725B1 (en) 2003-12-24 2006-04-28 산요덴키가부시키가이샤 Manufacturing method of hybrid integrated circuit device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02250391A (en) * 1989-03-24 1990-10-08 Ngk Insulators Ltd Manufacture of ceramic board for feeding
US5337474A (en) * 1991-05-31 1994-08-16 Fuji Xerox Co., Ltd. Process for fabricating electronic devices and image sensor
WO2001057922A1 (en) * 2000-02-04 2001-08-09 Advanced Systems Automation Ltd. Method and apparatus for singulation of electronic devices
WO2002094528A1 (en) * 2001-05-24 2002-11-28 Kulicke & Soffa Investments, Inc. Dual laser cutting of wafers
KR100574725B1 (en) 2003-12-24 2006-04-28 산요덴키가부시키가이샤 Manufacturing method of hybrid integrated circuit device

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