JPS5886647A - Dual system - Google Patents

Abstract

PURPOSE:To carry on smooth processing even after switching to another processing system, by providing a common memory accessed from both processing systems, and writing data in the common memory in parallel to access from a processing system in operation. CONSTITUTION:In normal operation, a CPU1 write data read from an IO8 in a main memory 3 and a common memory 10. Once the CPU1 becomes faulty, switching devices 7 and 9 connect auxiliary memories 5 and 6 and the I/O8 to a CPU2, which is started. Consequently, the CPU2 reads data out of the common memory 10 and takes over the processing of the CPU1. This system, therefore, need not restart the data processing from its beginning and performs the processing without interruption. When the CPU1 recovers and switching from the backup system to the main system is performed, said operation is performed similarly and the same effect is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a two-vehicle data processing system with a backup AMA.

A system of this type was shown in Figure 1. IJ1 diagram (1 and 2 are central processing units (hereinafter referred to as cpu)), 3.4 is CPUI, connected to 2
main memory (hereinafter referred to as memory), 5.6 is memo 93
, 4 serves as an auxiliary memory, 1 is a switching @position, and memory 5.6 is selectively connected to CPU 1 or 2. The sword device 9 connects the input/output device 8 to the CPU 1 or 2.
This is a switching device that selectively connects to the

Next, the operation will be explained. First, CPU1. of the sl processing system (acting as the main system here). When there is no abnormality in the memories 3 and 5, that is, when they are normal, switching -Ill is set to -V:
The switches 5 and 6 are connected to the CPU 1, and the switch ii*s connects the input/output 1119 to the CPU 142.

In this connection state, the CPU 1 reads the access data from the input/output ii@a, processes the data, and stores the data to be stored in both the memories 51 and 6. When a failure occurs in either the CPU 1 or the memo 93, the switching @1 occurs.
117, 8tj, memo v5, 6 and Irita force device 8 1
#! CPU2 constitutes the processing system of 2, and constitutes the backup system.
, and then let CPU 2 continue processing the data for 1 reprocessing, that is, pack amplifier. However, in this case, the data in memory 3 is accessed by CPU 3 as well, so it is stored in 7 n. The data cannot be used, and the CPU 2 needs to start the process over again from the beginning.

Conventional dual-system systems have one or more #Is, so even if the active Sl processing system fails and the system switches to the second standby processing system, the first processing Because the system's main memory is accessed by 12 processing systems, Ii'! Processing system 2 needs to handle the process from the beginning, and backup is smooth and rapid. However, there are disadvantages in that there are cases where it is not possible to adapt to the progress of the process.

This invention is a second 1Af'I in order to eliminate the drawbacks of the above-mentioned conventional 1Af'I. The second (or I+) processing system accesses the main memory of the first (or second) processing system and writes data necessary for data processing to the common memory.
It is an object of the present invention to provide a 21-system system that can smoothly continue data processing even when the operation is switched to the other processing system.

Hereinafter, FIG. 112 showing an embodiment of the present invention will be explained. It is shown in the iJ2 diagram, 10tjCPU1.

It is a common memory that is effective from 2nd to 4th time. The other parts of 7 are the same as the parts shown in Figure gIA1 and are indicated by the same symbols.

Next, the operation will be explained. During normal operation, CPU1 performs input/output ii! [By loading the data read from 7 into the memory 3 and 1 into the memory 10, if the processing is over 0ζζ 1 For example, if a failure occurs in the CPU 1, switching between the 7 and 9ti memories 5 and 6 and entering double sword 1ii
Switch the connection of ia to CPU2 and start ζ1. c.
rt, the %CPU2 reads data from the memory 10 and takes over the processing of the CPUI. Therefore, the system can execute data processing without restarting from the beginning and without any intermediate movement.

Hiko, when switching from the processing of I'12, i.e., the pick-up system to the processing system of ill, that is, the main system, due to a failure or recovery, etc., the same procedure as explained in the dormitory example above is used.1゜Similar effect. According to the above 1, this invention has 1t'1, jll and the second
Since it is equipped with a memory that can be accessed arbitrarily from the processing system of
Further, even when switching to the reverse of #i-t, data processing can be switched smoothly and quickly, and the continuity of data processing can be maintained.

[Brief explanation of the drawing]

iJ1 diagram is a block diagram of a conventional dual system system, 182
The figure is a block diagram of a two-cliff system according to an embodiment of the present invention. 1.2-CPU, 3,4,5.6...Memory, 8-.
Input/output 111m, 7, 9'' switchable, 10...
・Common memory. Note that in Figure 1, the same numerals omit the same parts.Order 2 @ Procedural amendment (voluntary) Mr. Commissioner of the Japan Patent Office■, Indication of the case Patent application Sholl-18-OOS No. 2
, Title of the invention Dual system system 3, Relationship with the person making the amendment Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Hitachi Katayama 4 , Agent Address: 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo, Full text of the specification to be amended 6, Amend the full text of the excessive specification in the amendment and contents appendix. 7. A document containing the entire text of the specification after the amendment to the list of attached documents: 1 full text after the amendment 1, title of the invention dual system system 2, scope of claims, respectively central processing unit and main memo 13 Y have m
If a failure occurs in the first processing system while executing data processing by the first processing, the processing system switches to the processing system s2 and continues the data processing. In the dual system system, a common memory that can be accessed from both the first and JI2 processing systems is provided, and when writing to the main memory, double writing is also performed to the common memory in parallel. , a dual-system system characterized by storing data for continuing data processing. 3. Detailed Description of the Invention The present invention relates to a dual data processing system having a backup function. Conventionally, there has been a system of this type as shown in Figure 4g1. In Fig. 1 h, 1.2 is a central processing unit (hereinafter referred to as CPU), 3.4 is a main memory connected to CPUs 1 and 2, and 5.6 is an auxiliary memory of the main memory 3.4. 7 is a switching device which functions as an auxiliary memory 5.
．． 6yt Selectively connects to CPU1 or 2. 8 is an input/output device for inputting and outputting data to and from the plant; 9 is a switching device for selectively connecting the input/output device 8wCPU1 to 2; Next, the operation will be explained. First, CPU1. of the Wll processing system (acting as the main system here). Main memory 3 and 5
When there is no abnormality, that is, when it is normal. The switching device 7 is connected to the auxiliary memo +)5.6y, -CPU1, and the switching device 9 is connected to the input/output device 8vCPU1. In this connected state, the CPU 1 reads process data from the input/output device 8, performs predetermined data processing, and writes data to be stored in both the auxiliary memories 5 and 6. In such an operating state, the CPU 1 and main memory 3
When it is detected that a failure has occurred in either of the auxiliary memory 5.6 and the input/output device 81, the switching devices 7 and 9 switch the auxiliary memory 5.6 and the input/output device 81 to the back-up system t and the CPU 2;
allows the process to continue processing data. In other words, make a backup. However, in this case, since the data in the main memory 3 cannot be accessed by the CPU 2, the data stored therein cannot be used, and the CPU 2#i has to start the process over again from the beginning. Conventional dual-system systems are configured with one or more processing systems, so even if the first processing system in operation fails and the system switches to the standby processing system #g2, the main processing system of the first processing system Since the memory cannot be accessed from the vgz processing system, the second processing system must restart the process from the beginning upon switching, and there is a drawback that backup cannot be done smoothly and quickly, and it is not possible to keep up with the progress of the process. There were also some drawbacks. This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and includes a common memory that can be accessed from both the first and twelfth processing systems, ) By writing data to the common memory required for data processing in parallel with accessing the main memory of the processing system, data processing can be performed smoothly even when the operation is switched to the second (or first) processing system. The purpose is to provide a dual system system that can be continued. Hereinafter, FIG. 2 showing an embodiment of the present invention will be described. In FIG. 2, 10#1CPU1. This is a common memory that can be accessed from both. Other parts #i! The parts are the same as those shown in FIG. 181 and are designated by the same reference numerals. Next, the operation will be explained. During normal operation, the CPU 1 writes data read from the input/output device 8 to the main memory 3 and to the common memory 10, thereby proceeding with process Y. here. For example, when a failure occurs in the CPU 1, the switching device 7.9 switches between the auxiliary memory 5.6 and the input/output device 8.
2 Switch to K and start it. As a result, C.P.
U2 reads the data from the common memory 10 and sends it to the CPU.
Takes over the processing from step 1. Therefore. The system can perform data processing without having to restart from the beginning and without interruption. Note that when switching from the second processing system, that is, the backup system, to the first processing system, that is, the main system due to failure recovery, etc., the same procedure as described in the above embodiment is performed. It has a similar effect. As described above, according to the present invention, since the common memory is provided that can be accessed from the first and second processing systems, it is possible to switch from the first processing system to the second processing system or vice versa. Even when switching, data processing can be switched smoothly and quickly, ensuring continuity of data processing! It has a long-lasting effect. 4. Brief Description of the Drawings @ Figure 1 is a block diagram of a conventional dual system system, and Figure 2 is a block diagram of a dual system system according to an embodiment of the present invention. 1.2-CPU, 3.4... Main memory, 5.6...
Auxiliary memory, 8... input/output device, 7.9... switching device. 10...Common memory. Note that in the figures, the same reference numerals indicate the same parts. Agent Shin Yomuno (1 person)

Claims (1)

[Claims] -trt-t"tt If and 12 processing systems having a central processing unit and a main memory are provided, and when data processing is executed by the processing of m1, the lth lAl1
In a dual-system system that is configured to switch to the second processing system and continue processing the data in the event of a failure in the system, from any one of the first and second processing systems. 2, characterized in that the device is provided with a common memory which can also be accessed, and in parallel with accessing the main memory, the common memory is accessed to store data for continuing data processing; Main system 0