JPS583320A - Codec integrated circuit for single chip - Google Patents

Abstract

PURPOSE:To simply check the characteristics to a DC signal, by providing a switch switching a 2-system signal transmission line into a 1-system signal transmission line and a self characteristic evaluation circuit. CONSTITUTION:When changeover switches SW1-SW4 are switched to the position as shown in figure, a signal transmission line consisting of a transmission side filter TRF and a coder CD and a signal transmission line consisting of a decoder DEC and a reception side filter RVF are formed. When a control signal is applied to a terminal CTS, the switches SW1-SW4 are changed over, the 2-system signal transmission line is changed to the 1 system to be the test mode. When a DC equivalent signal is applied to a test mode terminal TMT, the signal is inputted to a cumulative adder CML being a self characteristic evaluation circuit via the DEC, the RVF, the TRF and the CD. Thus, the characteristics to the DC signal can be checked simply.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a codec integrated circuit in a single-chip configuration that can be read.

A codec is a combination of three signal conversion circuits for analog and digital signals.
It is commonly called a decoder), and is split-acting as shown in Figure 1. In Fig. 1, 80B is a semiconductor chip in which the 1-system signal transmission path formed by the transmitting side filter TE Rν and cop OD and the @g system signal transmission path formed by the decoder DIO and the receiving-side filter RVIF are integrated into the same chip. It is installed. The input of the first signal transmission line 9 is an analog signal, and the output is a digital signal (tOD).

The input of the Shimadai System No. 4II transmission line is the digital signal works.

D, the same output is an analog signal M. Mutual information regarding analog and digital signals! When a conversion section is provided for the conversion process, it is necessary to detect the noise level and DC offset before starting operation, but conventionally this had to be done using a dedicated tester from outside the semiconductor chip SaS. Therefore, codecs are generally smaller and lighter because they are integrated circuits, but testers are larger and heavier.
*Because it was inconvenient to handle, it was complicated to adjust when implementing it.

SUMMARY OF THE INVENTION An object of the present invention is to provide a codec integrated circuit having a structure that allows easy checking of DC signal characteristics during the manufacturing process of a codec that has been integrated into a small size codec. Therefore, the gist of the present invention is to include a plurality of changeover switches for switching the G-system signal transmission path to the I-system, a test mode terminal provided at one end of the 1-system signal transmission path, and a self-characteristic evaluation circuit provided at the other end. The first thing to do is to apply a DC equivalent signal l and perform a check on the inner S-path itself.

The present invention will be described in detail below with reference to the drawings.

The second part is a plotter diagram of an embodiment of the present invention shown in correspondence with FIG.
74 is a change-over switch for switching to the 2-system signal transmission Mi] system, for example, an electronic switch using a complementary MOB type cow conductor transducer! use. OT8 is a signal application terminal for controlling the switching switch, 〒 TE is a test mode terminal provided at the - end of the signal transmission path when switched to one system, and OML is a digital signal cumulative adder. As described later, it is a self-characteristic evaluation circuit. When no signal is applied from control signal application terminal 0-B,
The changeover switches 1ff1 to 8W4 are all IIK as shown in the figure, so it is more than 40 mm.

The two signal transmission lines from M to OD each operate in the same way as in Figure 91. When the 0th order terminal 078 K control signal is applied, the changeover switches sW1 to 8Y4tX all switch to the opposite direction as shown in the figure, so the signal transmission The road! M〒-e11W4
-eDlo-+RV7-+IW14〒RF→on→8W
It becomes an l-system signal transmission path that goes around 2→OWL→ony. A test mode terminal installed at one end of the 4II transmission line of the l system! Guy! Apply all “0” digital signals of DC +δV@mushi to. The cumulative adder CML is the third rI! Assume that J includes a register RB as shown in T, stores the calculation result, and connects the test mode terminal ? M? When a K digital signal is applied, all signals are reset to "0".For example, the Korg OD is output from the 8-bit gamma biratra adder (DI), and an 8-bit shift register SR is conveniently used. .The register 18 outputs 8Kk41 after all "0".The lower bit of the output of Korg OD and the 8Kk41 in the register
The bits are added and the result is stored in register RBK again. Note that the most significant 1 bit of the 8 bits of the Korg OD output represents a positive/negative sign and is therefore ignored in the calculation.

That is, it takes the absolute value. The value in register RB and then Korg O
Add the signal output from D and again '/, (/!L
Store IK. This kind of addition will be cumulatively added to the SO times and the Korg OD output vao times - During the cumulative addition, the addition of the value in register R8 and the Korg OD output may carry over to the 9th bit. If there is, immediately set the value in the register to all ""l" (11111111), input +5v (all a) to the input of decoder D1eO.
It is conceivable that the DC voltage is being applied to the DC potential, and noises from the decoder DRCj, the receiving filter RVν, and the transmitting filter RF are superimposed on the DC potential and applied to the input section of the Korg CD.

Korg CD also has its own noise. Regarding Figures 1p and 2, if the codec is operating normally, these noises will be generated by the first bit (plus/minus sign) of the 8-bit code at 8kHz.
We take the values W of °0''' and 11'' evenly, and at most the code (11,
10,OX,00), this digital output is oo
oooooo Digitally normally distributed around v.

If it is a single-chip codec that operates normally, the maximum value of the lower bits "11" is added to 5 X B Ole = 150 - Decimal representation 11X (50) 10010110 - 12 Since this is an illegal expression, the output will be 8 bits. The operating state is not normal (2. For example, the DC offset of the transmitting filter T Rν is +l)
When omV is also present, the digital output is “10001000”
” is the center value.

If you ignore the most significant bit ``l''l and add it 50 times, it will carry over to the 9th bit and the register output will be all ``l'', so you need to detect it on the output side. Defects in the operating state can be known from K.

The same applies when the noise is abnormally large.

About this action! Figure 4 shows a flowchart.

In this way, according to the present invention, it is possible to check the status with only a single chip using switches, evaluation circuits, etc. constructed from elements that can be easily integrated into an integrated circuit, so testing can be easily performed during snowmaking mounting. It is easy to treat as a compost ivy.

[Brief explanation of the drawing]

Figure 1 is a schematic configuration diagram of a conventional single-chip integrated circuit; Figure 2 is a diagram showing the configuration of an embodiment of the present invention;
In the figure, the numbered figures showing the configuration of the cumulative adder show the operation flowcharts of figures 1p and 2. θC8--Semiconductor chip CD...Corp DK
O...Decoder T RP-Transmission filter RTI
F... Reception filter 81F1 to 11W4... Changeover switch CTE8... Changeover switch control signal terminal TMT-... Test mode O
ML--cumulative adder R8---Register III
)・-Adder patent applicant Fujitsu Limited Representative Eisuke Tsuchi Suzuki C5 ■---W Figure 1 Figure 2

Claims (1)

[Scope of Claims] 1. Two signal transmission lines, including a transmitter filter for analog signals, a converter for converting digital signals to digital signals, a converter for converting digital signals to analog signals, and a receiver filter, are mounted on the same semiconductor chip. In the single-chip copier integrated circuit, a plurality of changeover switches for switching to the three-system signal transmission path yx system signal transmission path, a test mode terminal provided with -jlK of the l-system signal transmission path, and a test mode terminal provided for the same l-system signal transmission path are provided. The self-characteristic evaluation circuit is equipped with a self-characteristic evaluation circuit provided at the other end of the line, and the self-characteristic is evaluated by the signal output from the l-system signal transmission line, which is switched to the test mode by applying a time-invariant signal to the test mode terminal. It's not worth evaluating the codec integration in a single chip. 2 A digital signal of a DC reference electric phase signal is applied to the test mode terminal, and a signal accumulation adder is applied to 111 in addition to the l system signal transmission line! Claim 1 characterized in that the noise output level of the l-system transmission line can be evaluated by providing
Single-chip σλ codec integrated circuit as described in Section 1.