JPS58215813A - Digital signal processing device - Google Patents

Abstract

PURPOSE:To process video data in real time at longer procesing time between two circuits, by separating a circuit operating logical sum of input digital signals of a prescribed number and another circuit calculating addresses. CONSTITUTION:Input data and coefficients are stored in a data memory 7, the address of the memory 7 is formed by an address processor 8, which is operated with a prescribed program of a controller 9. Further, the data read out from the memory 7 is applied to a product sum processor 10 for attaining product sum operation. A controller 11 is provided to the processor 10, which is operated with a prescribed microprogram of the controller 11 to output data yi. Further, the processor 8 performs the calculation of the address and data readout control, the processor 10 performs the product sum operation at the same time to speed up the data processing, thereby processing video data in real time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be explained by taking as an example a simple digital filter related to a digital signal processing device applied to a video image processing device. Let the difference equation of the digital filter be. Here, yl is the output signal, amG is the tap coefficient of the t filter (there are M+/), and xl-mG is the input signal. It takes digital filter winter i.

Of course, this can be realized by a device using a wired logic method (a method of creating logic using hardware), but from the viewpoint of flexibility of the device, it is preferable to use a processor controlled by a microprogram. Processing 74- in this case is shown in FIG.

In this processing step 4, A is set to 0. The initial setting of m as -l, the step of setting m+/l-m, the step of calculating (1-m), the step of reading the input X1-m from the memory, and the step of reading the coefficient am from the memory are performed using the address This is the process of calculating . On the other hand, e (
amXXi-m) step* (A + amX
The step of calculating x 1-m) and setting this as A, and the step of setting A as the value obtained by this product-sum operation, are 1
This is the process that performs the original calculation. Conventionally, like this, address calculation and original operations like multiply-accumulate operations.

Processes with different properties are performed by the same processor, which has the disadvantage that data processing calculation time becomes long.

Figure 2 shows the configuration of a two-dimensional digital filter (j x 3), and this filter processing is performed using a computer.
It takes seconds of video images.

It was recognized that it took several tens of minutes. Figure 3 shows N
It shows a TSC type digital color decoder,
In the figure, reference numeral 1 denotes a Y/c separation circuit which is composed of a two-dimensional digitized signal (a) L', and separates a luminance signal, a signal Y, and a luminance signal C from a composite color video signal.

The digital demodulation circuits 2 and 3 convert the
．． The signal is divided into two color difference signals (I signal and Q signal) and supplied to the matrix circuit 6 via four-pass filters 4 and 5 of the digital filter, respectively. The R-Y signal and the B-Y signal are taken out from the output of this matrix circuit 6.

The processing by such a digital color decoder can be expressed as follows.

......(riyIJ= :+ctj-yolJ river...(2). However, xlj): Input composite video signal and luminance signal (yR-") e (y",-"): R-y signal and B
-Yij 1j Signal (amn)'Coefficient of (MXN) two-dimensional filter of y/c separation circuit 1 # (M?N is an odd number) (b111/dimensional filter coefficient (Ll is an odd number) Filter coefficient (L2 is an odd number) (in dkl): 2×2 matrix coefficient Processing of equations (1) to (4) above requires several tens of product-sum operations.Color video signal When digitizing, the sampling period is generally about 70
nsec is used. Therefore, in order to perform the above processing in real time, one calculation takes 2 to 3 nsec.
You must run the following: However, in reality, it is difficult to perform such high-speed processing. In this invention, the processor that performs address calculation, data read processing, etc. and the processor that performs the multiply-accumulate operation are completely separated. By adopting such a configuration, it is intended to realize high-speed data processing. In other words, while the conventional configuration requires the sum of these two processing times, the present invention requires the larger of the two processing times. Therefore, according to the present invention, it is possible to realize video image processing in which video data processing can be performed in real time using a 1.2-dimensional filter (FIG. 2) or a digital color decoder (FIG. 3).

FIG. 3 shows the configuration of an embodiment in which the present invention is applied to the simple digital filter described at the beginning.

In FIG. 7, 7 indicates a data memory in which input data and coefficients are stored, and the address of this data memory 7 is formed by an address processor 8. A control unit 9 is also provided, and an address processor 8 operates according to a predetermined microprogram. The data read from the data memory 7 is supplied to the sum-of-products processor 10, where a sum-of-products calculation operation is performed. Control unit 1 for this product-sum processor 10
1 is provided, and the product-sum processor 10 is made to operate according to a predetermined microprogram. Then, output data y1 is generated from the product-sum processor 10.

By doing so, the address processor 8 can perform address calculation and data reading control, and the product-sum processor 10 can simultaneously perform the product-sum operation, thereby speeding up data processing. can.

FIG. 5 shows the overall configuration of another embodiment in which the present invention is applied to a video image processing device.

In the figure, 12 is e”10 control rule L=7
), ITVl 3. VTR14'! The analog video signal inputted from p is quantized by g bits at a sampling period of 70 rxtet and transferred to the memory unit 16. Further, the processed data is sent from the memory unit 16 to the D/A converter of the control unit 12, converted into an analog signal again, and supplied to the v'rR 14 and the monitor receiver 15. Analog input/output signals are composite signals or component signals (YUV, YIQ
, R()B).

Memory unit 16 typically consists of several banks, one for input data, one for output data.

01 banks for storing temporary data consist of (76tXJj&') pixels and correspond to 7 fields of the video signal. This memory unit 16 can be freely expanded in bank units.

□ Further, 18 is n array memories M1.

A group of array memories consisting of My, . . . Mn-1 and Mn is shown. Data transfer between memory unit 16 and array memory group 18 and array memories M, ~M
In order to control data transfer within each of n, a delay calculation unit 17 is provided which calculates a predetermined address and generates a control signal. This delay calculation unit) 17 also has advanced calculation functions in order to enable complex position conversion.019 indicates a product-sum calculation unit. This unit 19 includes n product-sum processors P1 to Pn coupled to each of the array memories M1 to Mn, and the product-sum processors P, .
By providing a dedicated control unit 01-Cn for each of the zero-product-sum processors P1-Pn, which are made up of control units 01-Cn for each of Pn, decentralized control can be performed. Output data from each of the product-sum processors P, .about.Pn of the product-sum calculation unit 19 is written into the memory unit 16.

Reference numeral 20 indicates a main control unit that manages the entire video image processing device. This main controller unit 20 initializes the product-sum processors P and ``Pn of the am calculation unit 17 and the product-sum calculation unit 19, and also performs the microprograms necessary for these.
A coefficient table is supplied from the main control unit 20. As described above, this microprogram controls the entire video image processing apparatus, the delay calculation unit) 17°[] the product-sum processors P, to Pn of the calculation unit 19. However, overall it has t operating modes of first order.

(a) Outer motor main control unit) 20
17. A microprogram is installed in the control units C1 to Cn of the product-sum calculation unit 19.
There is a remote to transfer the coefficient table.

(b) Internal mode: Main control unit) 20° delay calculation unit 17. This is a mode in which the control units C8 to Cn of the product-sum calculation unit 19 control themselves using their own microprograms.

(C) Debug mode: This is a mode for depacking each microprogram.

(d) Interwoven mode: A mode in which everything is under the control of the main control unit 20, changing from internal to external mode.

FIG. 6 shows the memory unit 16 and array memory group 1.
B and sum-of-products processor P! In principle, the necessary data is read out once per pixel from the 0 memory unit 16, which represents the interconnection network between 7 and 7.
0nsI! This input data bus 21 is connected to a group of array memories 18.
Input data is supplied to each of the array memories M1 to Mn in seven parallels.

Array memories M, ~Mn include product-sum processors P! ~
The input data required by Pn is taken in, and each of the product-sum processors Pt to pn performs predetermined arithmetic processing using this input data.The data processed by the product-sum processors P, to Pn is Each data is sequentially output to the output data bus 22 every 7 nsec, and is also written from the bus 22 to the memory unit 16. In FIG.

The array memories M1 to Mn and the sum-of-products processors P1 to Pn, which are illustrated in a ring shape, are considered to be rotating in the clockwise direction indicated by the arrow. The time required for this one rotation is (70Xn) seconds, and the sum of products processors P1 to P
n completes the processing within the time of these seven rotations and outputs the processed data to the output side data bus 22.

The delay calculation unit 17 includes a memory unit 16, a group of array memories 18. The above-described operations are performed by controlling the input data bus 21 and the output data bus 22.

Through this interconnection network shown in FIG.

This prevents memory contention from occurring.

Each array memory M1 of the array memory group 18
Each of Mn can freely change its array structure, and can take the optimum array structure depending on the processing purpose, contributing to faster processing and more efficient data transfer.

- As an example, Fig. 7 shows an array memory in which a plurality of registers are connected through tri-state gates, and the tri-state is controlled by a delay operation unit (17), so that two different array structures can be formed. show.

In FIG. 7, R1 indicates an l-bit shift register with parallel input and parallel output, and each output control terminal is set to a low level and is in a state where an output can be generated. A shift register R51yRs2sR33t R34e RR5 is connected in parallel to 21. This shift register R31-R3
Shift pulse 'r, e Tt e for each of 5
By controlling the supply of Tj p T, t'r,
Input data is taken in only to a desired shift register, and input data is output synchronously from a plurality of these shift registers.

Further, a shift pulse T. is commonly supplied to each of the shift registers R1 to R, .

5 shift registers R for shift register R3,
1 to R5 are connected in cascade, and shift register R is connected to shift register R6 via tristate G1. A shift register 1Rst is connected to this shift register R through a tristate G. Also, between shift registers R1 and R8, between R32 and R8,
Tri-state GB t 04 e G5 e ()s is inserted between R9 and R10, and between R8 and RIO, respectively. Similarly, shift registers RID and 1Rtt
Between eR1m and R11+RI4 and Rlm,
Tri-state GT I GS s GS r G heavy Oe between R83 and R1l+, between R8 and Rls
Gll is inserted respectively. Furthermore, similarly, shift register R1! and between R16, between R34 and R1, and R1
Between 1 and R1° 9 Between R33 and R11, Rt6
and between l'ttt.

eRm4 between RSS and R2, between R2 and R11
and tristate GlltG heavy S between and Ro.

G14 + ()ts l G16 e Gl'FW
018 e GII is inserted respectively.

The respective outputs of shift registers R1 to R17 are as follows.

The signal is supplied to a corresponding one of the product-sum processors P1 to Pn via a tristate (not shown). Shift registers R8 to R2Y # Shift pulses and output control signals for each of Rst to R35 and tristate G, to each of ()to) o
The -role signal is generated in the delay calculation unit 17.

The array memory shown in FIG. 7 can have the array structure shown in each of FIGS. 1A to 1E. First, a shift click TI is given to the shift register R111 to take in input data, and the tristate Gl e G
S e Gl e G7 e G, l G1t+G1
4*G16 e By setting the control signal for G111 to a low level, making them active, and setting the other tristates to a high impedance state, the shift register R is set as shown in Figure A.
1 to R2? An array structure is formed in which all of the above are cascaded. - As an example, this array structure is used when simulating one-dimensional digital filling. Shift the input data to registers R31 and 1Rsi
The input data is sequentially captured in the tri-state G1, and the input data is output from each in synchronization.

03 s G5 v GY + G11 e Gat
l G14 y G18 *By setting aSS to the active state and setting the other tri-states to the high impedance state, as shown in Fig. An array structure is formed consisting of a first row and a second row of 73 shift registers from shift registers RIS to Rty.

In addition, shift register Rs+s Rst*Rss
The input data is taken into each of the tri-states G1゜G3*G6y Gta GSe Gl! p G
By setting ls+G16eaIm to the active state and setting the other tristates to the high impedance state, the array structure (JX9) is realized as shown in FIG.

Also, shift register Rnt @ Rste R3*
Input data is taken into each of eRs4, and tristate Gl t G'4 # Gl e G'
l * G10 + Gl! +G14 m G1
6 e By setting Gl@e to the active state and setting the other tri-states to the high impedance state, the first to third rows become 7 as shown in the diagram.
An array structure is realized in which the fourth row is composed of six shift registers and the fourth row is composed of six shift registers.

Furthermore, shift register Rs+ e Rst i Rss
The input data is taken into each of eR and 4e Rss, and the tristate Gt * GS e Gl
e G8 #Gll + Gta T 014 m G
ty l Gil+ is in the active state, and as shown in Figure E, the first row to the first row is composed of three shift registers, and the fourth row is composed of seven shift registers. is realized.

The array structures shown in Figures B, C1, and E described above are applied when simulating a two-dimensional digital filter, for example. In other words, the video image processing device according to this embodiment includes a digital filter,
Special effects equipment such as image conversion, Ocolor encoder, color decoder.

Various simulator WNs, such as fast Fourier transforms, can be used.

As understood from the above description, this invention has the following features.

Since the circuit that performs product-sum operations on a predetermined number of input digital signals and the circuit that calculates addresses are separated, the processing time is the greater of either, making it possible to perform these processes at high speed. can. Therefore, it is possible to realize a video image processing device that can simulate video data processing such as a digital filter in real time.

[Brief explanation of the drawing]

FIG. 1 is a 7tff-chart used to explain data processing of a digital filter to which this invention can be applied, and FIGS. 2 and 3 are configurations of a two-dimensional digital filter and color decoder to which this invention can be applied. Fig. 4 is a block diagram of one embodiment of the present invention, Fig. J is a splitter diagram of another embodiment in which the invention is applied to a video image processing device, and Fig. 4 is a block diagram of an embodiment of the present invention. A route map used to explain the interconnection network in other embodiments, FIG. It is. T...Data memory, 8...Address processor, 9.11...Controller, 1
0... Product sum processor, 12... Engineering 1
0 control unit, 16... memory unit, 17... delay calculation unit, 1B...
...A group of array memories. 19...product-sum calculation unit, 20...
Main control unit, 21...Input side data path. 22...Output side data bus. Agent Masatomo Sugiura

Claims (1)

[Claims] When digitally calculating an input digital signal. A process circuit that calculates a predetermined number of input digital signals to form an output digital signal, and a circuit that determines address information corresponding to the output digital signal based on address information corresponding to the predetermined number of input digital signals. A digital signal processing device characterized in that it is provided separately.