JPS58115569A - Multiprocessor method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved processor allocation method (secondarily, a multiprocessor method with improved processing capacity).

Multiprocessor system consisting of multiple processors
In the system, a mask processor method is adopted as a means for resolving conflicts between processors regarding assignment of tasks (a set of processes with a specific purpose).

In this method, any one of the multiple processors is used as a mask processor, and each of the remaining processors that are subordinate to this processor performs a mask process when a request to execute a task that involves assignment to another processor occurs. Processor (−
The mask processor that receives this notification assigns the appropriate processor to the task requested to be executed depending on the priority of the task, system operating status, etc.

Conventionally, processor allocation in this basic master processor method is carried out by having a task management table for managing the status of all tasks and a Broyssa storage table for managing the status of all processors in the mask processor (== each processor A software (2) method is adopted in which the mask processor selects the processor to be allocated according to the procedure C1 shown below.In other words, when an activation request for a certain task is notified, Then, the master processor checks the processor location table to find an empty processor that is not executing any tasks.

If a stalled processor is found, that processor is assigned to the task for which activation was requested. On the other hand, if no free processor is found, the task management table is checked to find a processor that is executing a task with a lower priority than the task for which the startup request was made. If such a processor is found, the task being executed by that processor is interrupted, and the task with the highest priority that was requested to be activated is executed. On the other hand, if no processor is found running such a low priority task.

The activation request is put on hold. The results of the processor allocation work described above are recorded in the task management table and processor management table. In particular, for a processor to which a new task has been assigned, the processor management table (2) ``task execution state'' is recorded.

In addition, each time each processor finishes the task it was executing, it notifies the mask processor (2) of this fact. Upon receiving this notification, the CPU of the mask processor records the fact in the task management table and processor management table (2). .Particularly (Broyassa who finished a task: In two cases, "free status" is recorded in the processor management table. After that, the CPU of the masked processor checks the task management table, and if the activation request is pending or the task has a low priority) If there is a task whose execution has been interrupted,
Select one of them and assign the processor to the selected task.

However, the above-mentioned mask processor method (processor allocation method in -) has the following drawbacks. In other words, notifications of task start requests and notifications of task completion are processed in the order of arrival (two by one) by the CPU of the mask processor. Therefore, even if a task ends (i.e., a processor becomes vacant as a result) while allocating the task 1 processor for which activation was requested, the notification to that effect will be deferred in the mask processor. Therefore, the mask processor cannot immediately recognize the newly generated free state.For this reason, the mask processor cannot recognize the newly generated free state immediately (2).Therefore, the mask processor cannot recognize the newly generated free state (2) even though the free state processor actually exists (2). In some cases, it may be unreasonable to purposely interrupt a processor that is executing a task with a low level of performance, and then allocate a processor that has requested execution to this processor.

FIG. 1 is a conceptual diagram showing such an example, in which the horizontal axis represents time and the vertical axis represents the classification of processors and the tasks they are executing. In FIG. 1, among the seven processors 21 to 2, Pl is a mask processor,
Each processor Pg -P? is time 1o (
Tasks T1 to T, respectively? is running. The tasks are T1, TJ, T,, T6. In the order of T6 and T7 (one priority is lower).

Time 1. Processor PI is executing task T!
generates a request to start a new task T8. The mask processor P1 that has received this starts processor allocation work according to the procedure described above. During this assignment, at time t, task Ts, which is currently being executed by processor fPs, issues a request to start a new task To, but this request is suspended by mask processor P. Subsequently, time t1
In this step, the task T& executed by the processor P4 is completed and a task end notification is issued, but this is also put on hold in the mask processor PI. Master Broset'f
At time t4, the P-weight selects 1% of the processors that are executing the task T7 with the lowest priority, and assigns it to the task Ts that has been requested to be activated by the processor P. Assume that the priority of task T8 is higher than that of task T8.

When the CPU of the mask processor finishes assigning the processor Pq to the task T8, it starts processing the pending startup request from the processor P3. This processor allocation process is performed in exactly the same manner as described above. In this case, since the completion notification of task T4 from processor P is still pending, the star processor cannot recognize that processor P4 is actually in the vacant state 9. Therefore, the mask At time tl, the processor interrupts the task of the processor fPa that is executing the task T6 with the lowest priority, and transfers it to the task To (two-way assignment; only after this assignment is completed is the task from the processor 8 Processing of the termination notification will begin.

In this way (=, conventional method (-), the task end notification from the processor was processed in the same way as a task activation request (at the second arrival, by the master processor), so the mask processor was in an empty state (-) This has the disadvantage that it takes a long time to recognize the system, and the processing capacity of the entire system cannot be fully utilized.

The present invention has been made in consideration of the above-mentioned drawbacks of the conventional method, and its purpose is to immediately recognize the existence of a vacant prosenna by a mask processor, and to activate it for a task that has been requested to start. (The purpose of processor allocation is to provide a method for improving the processing capacity of the entire system by assigning two components.

The details of the present invention will be explained below with reference to Examples.

FIG. 2 is a block diagram showing an example of the configuration of a free processor selection device used in an embodiment of the present invention. Each of the processors has a status flag register (not shown) that indicates whether the task is in execution or is in an idle state (not shown), and the contents of these registers are input to the corresponding input terminal 11 of the idle processor selection device. .12.13...1nl Two people work together.

These input terminals are connected to corresponding gate circuits 21 and 22, respectively.
．． 25...2n (= are coupled, and the other input terminal of these gate circuits is connected to the inverter 60.
The output terminal of the prosena selection instruction flag register 50 (= is connected to the gate circuit 21.22.2
5...2n are coupled to the input terminals of the corresponding processor status display flag registers 31, 32, 33...3n, and the output terminals of these registers are coupled to the input terminals of the priority encoder 40 has been done.

The output terminal of this priority encoder is coupled to one input terminal of a gate circuit 70, and the other input terminal of this gate circuit is connected to a processor selection instruction flag/
It is directly connected to the output terminal of the register 50. The output terminal of the gate circuit 70 is coupled to the input terminal of a Broyssa scan register 80, and the contents of this register 80 are read out to the CPU of the mask processor via a terminal 81.

Input terminal 1t (i=1 to n)l2 is a flag (-0) of the mask processor indicating that processor 7 has entered the task execution state when the corresponding processor l is assigned to the task. On the other hand, when the corresponding processor 1 completes a task, a flag "1" indicating that the corresponding processor has become free (-) is directly supplied from the processor 1 without going through the CPU of the mask processor. In addition to the free processor selection device configured as described above, the mask processor includes a task management table (not shown) for managing the progress status of all tasks.

When the mask processor receives notification of an activation request for a task from one of the processors, it first sets a flag "1" in the processor selection command flag register 50 to instruct the selection of the browser. As a result, all gate circuits 21-2n are cut off, all processor status display flag registers 51-3n are separated from corresponding input terminals 11-1n, and updating of their contents is prohibited. The priority encoder 40 reads the processor status display flags from the processor status display flag registers 51 to 3n, and if there is only one flag "1" indicating the availability status of the processor (2, it outputs that flag). Outputs the storage position information (processor number) of the register 61 that is in use, and if there are multiple flags "1" that indicate the idle state of the processor, a predetermined priority order (=therefore, one flag is selected from among them) is output. The priority encoder 40 selects the processor and outputs its processor number.On the other hand, if the processor status display flags looked at are all outputting "0" indicating that the task is being executed (= is 1-
0" is output. The idle state output from the priority encoder 40 (2 processor numbers or "0" indicating that all processors are executing tasks)
” is sent to processor number register 80 via gate 70.
Set the oyster.

The CPU of the mask processor receives the updated contents of the block f sign register 80 via the output terminal 81, and
If the number of an idle processor is displayed instead of "10", the processor corresponding to that number is attached to the activation request task (2).On the other hand, the master processor's CPU is The content is “
0" and there are no free processors (the second is,
Based on the contents of the task management table, it searches for a processor that is executing a task with a lower priority than the task 42 that requested activation. If such a processor exists, the task being executed is interrupted and an up-request task is assigned to it; if no such processor exists, the request is suspended. Mask processor C
When the PU is in an empty state (in the idle state) and has assigned a task with a start request, the PU outputs a flag "0" indicating the execution state of the task to the input terminal 111 corresponding to this processor. Subsequently, the processor selection command flag
Set the register 50 to “0”. As a result of this (:), new processor status display flags on input terminals 11 to 1n are set to registers 31 to 3nζ via gates 21 to 2n.

On the other hand, when each processor finishes the task it was executing, I: first outputs a flag "1" indicating the idle state of the processor on the corresponding input terminal 11, and then masks the completion of the task. CPU 42 notification.

The output flag “1” on the input terminal 11) indicates that the CPU
If the master processor is not selected, the master processor's CP
U l: The notified task completion notification is processed immediately or after being put on hold for an appropriate period of time according to the order of arrival of completion notifications or startup requests from other processors,
The contents of the task management table are updated. Subsequently, the CPU of the mask processor reads the task management table.
If there is a task with a pending startup request or a task that has been suspended due to low priority, select one of them according to the appropriate selection criteria and allocate the vacant processor to it. Do the work to attach it.

FIG. 6 is a block diagram showing another example of the configuration of the free processor selection device used in one embodiment of the present invention. This device, like the device shown in the second figure, is located within the master processor. In Fig. 3, the elements with the same reference symbols as in Fig. 2 are the same as those already explained in relation to Fig. In Fig. 3, 91.92...9n are input terminals 101.1 that receive the operable display flag of the corresponding processor, 2...n, from the CPU of the mask processor.
02...10n are operational display flag registers that store flags on these input terminals, 111, 112...
-11n is a gate circuit.

The CPU of the mask processor sets the processor selection command flag register 50 to ``1'' in the task for which the startup request was made (in a misguided task to allocate two processors). A ready display flag determined for each held task is successively outputted, and this flag is reset to ready display flag registers 101-10n+ via input terminals 91-9n.

This operable display flag is set to “1” for a processor that is allowed to operate for the currently requested task.
" is assigned, and the other processors (two of them are assigned -"). The CPU of the mask processor
After setting the operable display flag in the registers 101 to 10n, the processor selection command flag register 50 is set to "1" via the input terminal 51.

After that, the same operation as explained in FIG.
The task for which execution was requested (the processor to be attached to the second side is selected. Therefore, in this configuration 42, the idle state C
Since it is possible to select a processor that has two tasks and is allowed to operate on two tasks, there is no need to select an idle processor and then judge whether or not the task is allowed to operate on it. The selection time can be shortened.

In the processor selection device illustrated in FIGS. 2 and 3, the register 80 may be omitted and the output of the gate circuit 70 may be directly connected to the CPU of the mask processor. Alternatively, priority encoder 4
By configuring one or both of the registers 61 to 3n to be enabled or disabled from the CPU of the mask processor, the register 50 and the gate circuits 21 to 2n and 70 can be omitted. In addition, the mask processor's CP indicates that the processor is in the task execution state (second state).
Although an example has been shown in which the notification is sent from U, it is also possible to have a configuration in which this notification is sent from each processor.

Further, the selection criteria for the priority encoder 40 can be appropriately selected depending on the characteristics of the system.

For example, a configuration in which the rightmost or leftmost processor is selected among multiple processors displaying free status, or a configuration in which the processor is randomly selected (= selected), or a configuration in which these selection criteria can be changed according to the load status. You can also do that.

As described above in detail, the present invention enables the processor status display flag that indicates that the processor is in an idle state when each processor finishes the task it is executing to be executed by the processor without going through the CPU of the mask processor. Since the mask is directly set in a register in the processor, the CPU can immediately recognize the existence of a free processor, and has the advantage that the processing capacity of the entire system can be greatly improved by adding a small amount of hardware.

[Brief explanation of drawings]

Figure 1 is a conceptual diagram to explain the problems of the conventional method, Figure 2, '! ! FIG. IIs is a block diagram illustrating an example of the configuration of a processor selection device used in an embodiment of the present invention. 11-1n...input terminal, 21-2n...gate circuit, 31-3n...processor status display flag register, 40...priority encoder, 50...
...Processor selection instruction flag register, 70...
Gate circuit, 80... Processor number register, 91
~9n...input terminal, 101~10n...operable display flag/register, 111~11n...gate circuit. Figure 1 Figure 3

Claims (1)

[Scope of Claims] In a multiprocessor system consisting of a master processor and a plurality of subordinate processors, a processor that indicates that the processor is in an idle state when each processor completes a task. Receives a status display flag from the processor, and receives a processor status display flag from the CPU of the processor or the master processor to indicate that the processor is in a task execution state when each processor is assigned to a task;
Processor-compatible (
2 registers provided, the contents of the registers provided corresponding to the processors (2) If there are processors in the free state, the predetermined selection criteria (2) Therefore, the free state DI =
If one processor is selected and the processor number is output, and there is no free processor (the second is a selection means for outputting a signal indicating this and a task management table to the mask processor). The mask processor detects the output signal of the selection means when receiving a task activation request from each processor, and if the output signal indicates a processor number (= indicates that the processor having the number is selected from the selection means). Tasks related to startup requests (
If the output No. 8 indicates the absence of a free processor (= indicates that the processor selected according to the task management table in item ij is assigned to the task related to the activation request (characterized by attaching two processors). Multiprocessor method.