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JPS58109943A - Hardware diagnostic system - Google Patents

Hardware diagnostic system

Info

Publication number
JPS58109943A
JPS58109943A JP56207142A JP20714281A JPS58109943A JP S58109943 A JPS58109943 A JP S58109943A JP 56207142 A JP56207142 A JP 56207142A JP 20714281 A JP20714281 A JP 20714281A JP S58109943 A JPS58109943 A JP S58109943A
Authority
JP
Japan
Prior art keywords
diagnosed
test
blocks
status
diagnosis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56207142A
Other languages
Japanese (ja)
Other versions
JPS6346458B2 (en
Inventor
Mikio Hashimoto
橋本 幹男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56207142A priority Critical patent/JPS58109943A/en
Publication of JPS58109943A publication Critical patent/JPS58109943A/en
Publication of JPS6346458B2 publication Critical patent/JPS6346458B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To detect of the presence/absence of status change of each diagnosed section and to attain easy forming of expected data, by storing the initial state of the diagnosed section and, comparing said section with the initial state stored in advance after the execution of the test processing operation. CONSTITUTION:A hardware system 1 to be diagnosed is split into blocks A-C to be diagnosed and the rest blocks D-F to be diagnosed according to the purpose of diagnosis, and the initial standard status of the blocks A-C is stored in a memory 23 in a test device 2 via an interface circuit 11. Through the operation of a keyboard 22 of the test device 2, a command is given to the blocks A-C a specified test signal is applied for the execution of the processing for test. The blocks A-C are split into diagnostic units for the execution of diagnosis and compared with the initial standard status stored in the memory 23, the status changes is detected, and through the result of detection and the comparison between discrimination flags of result of diagnosis of an external storage device 3, the normality of the blocks A-C is discriminated.

Description

【発明の詳細な説明】 (1)  発明の技術分野 本発明は、ハードウェア診断方式に関し、例えばコンビ
ーータあるいは電子交換機等の電子機器のハードウェア
を診断する方式に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a hardware diagnosis method, and for example, to a method for diagnosing the hardware of an electronic device such as a converter or an electronic exchange.

(2)技術の背景 一般に、ディ゛ジタルコンビ為−夕等の電子機器は工場
における組立完了後に、あるいは宇部的な保守点検時に
ハードウェア各部の機能の正常性等の診断が行なわれる
。ところが、このような電子機器はハードウェア量が多
く、構成が複雑であるため、きわめて多種多様かつ多項
目の診断を行なう必要があるため、効率的かつ適確な診
断方式が必要とされる。
(2) Background of the Technology In general, the normality of the functions of each part of the hardware of electronic devices such as digital combination devices is diagnosed after assembly is completed in a factory or during regular maintenance inspections. However, since such electronic devices have a large amount of hardware and a complicated configuration, it is necessary to perform a wide variety of diagnostics on a large number of items, and therefore an efficient and accurate diagnostic method is required.

(3)  従来技術と問題点 従来、ハードウェアシステムのテストは核ノーードウエ
アの、装置全体あるいは個別回路をも含めて、テスト目
的に応じて区分された機能プ四ツクに対しテストデータ
等を用いてアクセスすることによシ、咳ハードウェアか
らの応答結果として得られ九データすなわちステータス
と予め咳ノ1−ドウエアからの応答結果を想定して用意
した期待データとを比較することによって行なわれてい
た。
(3) Prior art and problems Conventionally, testing of hardware systems has been conducted using test data for four functional blocks classified according to the test purpose, including the entire device or individual circuits of the core nodeware. This was done by comparing the data obtained as a response result from the cough hardware, that is, the status, with the expected data prepared in advance assuming the response result from the cough hardware. .

マタ、従来ハードウェアシステムの初期診断テスト等線
基本となる論理回路の1部からテストを開始し、順次そ
のテスト範囲を拡大してゆき一定のレベルのテストに到
るように行なわれていた。
In the past, initial diagnostic tests for hardware systems started with a portion of the basic logic circuit and gradually expanded the test range until a certain level of testing was reached.

しかしながら、前記従来形においては、期待データ、を
想定してこれをテストプログラムの特定データエリア等
に準備”しておく必要があり、咳データ作成に多くの手
間を要し、データエリアが個々のテストととに必要であ
るという不都合があった。
However, in the conventional method, it is necessary to assume expected data and prepare it in a specific data area of the test program, which requires a lot of effort to create cough data, and the data area is divided into individual data areas. There was an inconvenience in that it was necessary for testing and.

さらに、前記従来形においては期待データの設計が煩雑
な丸め設計過誤を生ずる訃それ、およびテスト項目屯れ
を生じるおそれがあった。
Furthermore, in the conventional type, there is a risk that the design of expected data may cause a complicated rounding design error, and that the number of test items may be increased.

14)発明の目的 本発明の目的は、前述の従来形における問題点Kかんが
み、ハードウェア診断方式において、ハードウェア各部
の初期状態とテスト動作後の応答状態との間の状態変化
の有無によって診断を行なうという#想にもとづき、ハ
ードウェアシステムの初期診断時におけるテスト結集の
期待データを設計する工数を削減し、該期待データを記
憶する領域を減少させるとともに、該期待データの設計
過誤およびテスト項目もれをなくすることにある。
14) Purpose of the Invention In view of the above-mentioned problems with the conventional type, the purpose of the present invention is to perform diagnosis based on the presence or absence of state changes between the initial state of each hardware part and the response state after test operation in the hardware diagnosis method. Based on the #idea, we reduce the number of man-hours required to design expected data for test results during the initial diagnosis of a hardware system, reduce the area for storing the expected data, and eliminate design errors and test items for the expected data. The goal is to eliminate leaks.

15)発明の構成 そしてこの目的は本発明によれば、ハードウェアシステ
ムに幹ける各被診断部の初期状態を記憶しておき、テス
ト用処理動作の実行後に各被診断部の応答状態と予め記
憶しておい九咳初期状態とを比較する仁とにより各被診
断部の状態変化の有無を検知し、咳検知0結果得られた
情報と、各被診断部の状態が変化すべきか否かを配憶し
た診断結果判定フラグとにもとづき該ノ・−ドウエアシ
ステムO診断を行なうことを特徴とするハードウェア診
断方式を提供することによって達成される。
15) Structure of the Invention According to the present invention, the initial state of each part to be diagnosed in the main hardware system is memorized, and after execution of the test processing operation, the response state of each part to be diagnosed is stored in advance. Detect the presence or absence of a change in the state of each diagnosed part by comparing it with the initial state of the cough detected in memory, and use the information obtained as a result of cough detection 0 to determine whether the state of each diagnosed part should change or not. This is achieved by providing a hardware diagnosis method characterized in that the hardware system O is diagnosed based on the diagnosis result determination flag that stores the information.

(6)発明の実施例 一 以下図面を用いて本発明の詳細な説明する。(6) Examples of the invention one The present invention will be described in detail below using the drawings.

第1図杜、本発明の方式を実施するためのシステムの構
成の1例を示す、同図において、1は被試験ハードウェ
アシステム、2は被試験/1−ドウエアシステムOコン
ノールまた社別に設は九サービスプロセサ等の試験装置
、Sは必要に応じて峡試験装置2に接続される外部記憶
装置である。被試jllEハードウェアシステム1はテ
スト目的に応じて各々の被診断回路イロツク人、B、C
,i)、g。
FIG. 1 shows an example of the configuration of a system for implementing the method of the present invention. In the figure, 1 is the hardware system under test, 2 is the hardware system under test, and 9 is a test device such as a service processor, and S is an external storage device that is connected to the test device 2 as necessary. The hardware system under test 1 has different circuits under test, B, and C, depending on the test purpose.
,i),g.

F等に分けられ、こ糺らの内斜線で示された人。People are divided into F, etc. and are indicated by diagonal lines inside.

B、Cは診断可能な回路ブロックであり、残少OL)、
g、Fは診断不可能な回路ブロックである。
B and C are diagnosable circuit blocks (remaining OL),
g and F are circuit blocks that cannot be diagnosed.

また、11は各論断可能回路ブロックA、B、Cのステ
ータスを試験装置2に送るためのインタフェース回路で
ある。試験装置2はディスプレイ21、キーボード22
、メモリ2!1等を具備する。
Further, reference numeral 11 is an interface circuit for sending the status of each of the arguable circuit blocks A, B, and C to the test device 2. The test device 2 has a display 21 and a keyboard 22.
, memory 2!1, etc.

外部記憶装置Sは1例えば磁気ディスク装置等が使用さ
れる。!!I試頓°ハードウェアシステム1と試験装置
は被試験ハードウェアシステム1に設けられたバス線あ
るいは試験・用に別に設けた伝送線によって接続されて
いる。
As the external storage device S, for example, a magnetic disk device or the like is used. ! ! The hardware system 1 and the testing device are connected by a bus line provided in the hardware system under test 1 or a transmission line provided separately for testing.

このようなシステム構成において、ハードウェアシステ
ムの診断を行なうには、まず被試験ハードウェアシステ
ムの診断可能回路ブロックA、B。
In such a system configuration, in order to diagnose the hardware system, first the diagnosable circuit blocks A and B of the hardware system under test are checked.

Cのパワーオンリセット又はシステムリセット直後の初
期標準ステータスをインターフェース回路11を介して
試験装置2内のメモ92B又は外部記憶装置5に記憶し
ておく。
The initial standard status immediately after the power-on reset or system reset of C is stored in the memo 92B in the test device 2 or in the external storage device 5 via the interface circuit 11.

次に、被試験ハードウェアシステムの診断対象部すなわ
ち診断可能回路に対して、例えば試験装置2から何らか
のコマンドの発信等を行なうことによつて峡診断対象部
にテスト印加を行ないテスト用処理動作を実行させる。
Next, a test is applied to the diagnostic target part of the hardware system under test, that is, a diagnosable circuit, by sending some kind of command from the test device 2, for example, to perform a test processing operation. Let it run.

このテスト用処理動作の結果得られた各部の応答ステー
タスを試験装置側に読み取シ、先に記憶しておいた初期
状態の標準ステータスと比較することにより対象回踏の
状態変化の有無を検知する。この状態変化の有無O情報
を、各対象回路の状態が変化すべきか否かを記憶し九1
断納果判定フラグの内容と比較し、咳フラグで示される
通シ0状態変化が起っておれば動作線正常とみなされる
The response status of each part obtained as a result of this test processing operation is read into the test equipment side, and by comparing it with the standard status of the initial state stored previously, it is detected whether or not there is a change in the state of the target cycle. . This state change presence/absence O information is stored as whether or not the state of each target circuit should change.
Comparison with the content of the cough flag indicates that the operating line is considered normal if a change in the 0 state indicated by the cough flag has occurred.

第2図は、第1図の被試験ハードウェア内の被診断対象
ブロックA、B、Cをそれぞれ塔らに細かい診断工エッ
ト人1.A2.As、A4.th、B2゜Bi、Ct、
C鵞、Osに分割し、それぞれの診断具エツトの初期ス
テータスm1.i2.ml、*4.bl。
FIG. 2 shows a detailed diagnostic test of blocks A, B, and C to be diagnosed in the hardware under test shown in FIG. 1. A2. As, A4. th, B2゜Bi, Ct,
The initial status of each diagnostic tool m1. i2. ml, *4. bl.

bt、bs、cl、c2.csを示したものである。各
診断工具ット拡例えばバイト単位またはビシト暎位の論
理回路レベルまで分割してもよく、このように細かく分
割することにより自め細かな診断を行なうことも可能で
ある。
bt, bs, cl, c2. This shows the cs. Each diagnostic tool may be expanded to, for example, a byte unit or to the logic circuit level of a bit, and by dividing it into small pieces in this way, it is also possible to perform detailed diagnosis.

第2図の初期ステータスに対し、所定のテスト動作を行
なった後の応答ステータスが第5図(IIOのようにな
シ、かつ咳テスト動作の場合の結果判定フラグが95図
(b)で示されるものとするe@’図(荀の各ステータ
スを第2図の初期ステータスと比較した結果、例えば斜
線で示す診断ユニットのスことか検知された場合は第5
FR(ロ)の結果判定フラグと対照することによって変
化すべき診断瓢ニットのステータスが変化していること
が分るから、各診断対象ブロックの機能は正常であるこ
とが分る。なお、結果判定フラグにおいても、変化すべ
き診断ユニットが斜線で示されて匹る。を九、被診断ハ
ードウェアシステムに他O所定のテストをbsが変化し
九ステータスとなシ、このテストの場合の結果判定フラ
グが第4図(b)のように職1゜実11[Kステータス
が変化し九診断ユニットと、結果判定ブラダで示される
変化すべきステータスが相異す石から、すなわちステー
タス麿4 が変化していないからエラーと判定できる。
The response status after performing a predetermined test operation for the initial status shown in FIG. 2 is shown in FIG. e@' diagram (As a result of comparing each status of Xun with the initial status in Figure 2, if the diagnostic unit shown by diagonal lines is detected, the 5th
By comparing it with the result determination flag of FR (b), it can be seen that the status of the diagnostic gourd unit that should be changed has changed, so it can be seen that the function of each block to be diagnosed is normal. In addition, also in the result determination flag, the diagnostic unit to be changed is indicated by diagonal lines. 9. If another predetermined test is performed on the hardware system to be diagnosed, the BS changes to the 9 status, and the result judgment flag for this test is set to 1゜actual 11[K It can be determined that there is an error because the status has changed and the status to be changed shown in the 9 diagnostic unit and the result judgment bladder are different, that is, the status 4 has not changed.

(7)発明の効果 上述のように、本発明によれば、所定のテストによりて
状態が変化すべきか否かを示す結果判定ブラダを準備す
るだけでよく、結果判定フラグの作成は一般に従来形に
おける期待データの作成に比してかなシ少ない工数で行
なうことができ、かつ必要な記憶エリアもはるかに少な
くすることができる。を九、結果判定フラグの作成は従
来形における期待データの作成よりもはるかKIFJ!
に行なうことができるから、テスト項目もれ等が防止で
きる。
(7) Effects of the Invention As described above, according to the present invention, it is only necessary to prepare a result judgment bladder that indicates whether or not a state should change by a predetermined test, and the creation of a result judgment flag is generally performed using the conventional method. This can be done with significantly less man-hours than the creation of expected data in , and the required storage area can also be much smaller. 9. Creation of result judgment flags is much easier than creating expected data in the conventional format!
This prevents omission of test items.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の1実施例に係る方式を実施する丸め
のシステムの1例を示すブロック回路図、第2図は、第
1図のシステムにおける初期状態を示す説明図、そして 第5図および第4図は、第1図のシステムにおけるテス
ト動作後の応答状態と結果判定フラグを示す説明図であ
る。 1・・・・被診断ハードウェアシステム1.2・・・拳
試験装置、 So・・外部記憶装置、 11・・Φ・インタフ巽−ス回路、 21・・■ディスプレイ装置、 220・・キーボード、 25・−・・メモリ。 特許出願人 富士通株式金社 特許出願代理人 弁理士 青 木   網 弁理士両舘和之 弁理士内田中昇 弁理士 山 口 昭 之 223
FIG. 1 is a block circuit diagram showing an example of a rounding system implementing a method according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an initial state of the system in FIG. 1, and FIG. 4 are explanatory diagrams showing the response state and result determination flag after the test operation in the system of FIG. 1. 1...Hardware system to be diagnosed 1.2...Fist test device, So...External storage device, 11...Φ-Interface circuit, 21...■Display device, 220...Keyboard, 25.--Memory. Patent applicant Fujitsu Kinsha Patent application agent Patent attorney Aoki Ami Patent attorney Kazuyuki Ryodate Patent attorney Noboru Uchitanaka Patent attorney Akira Yamaguchi 223

Claims (1)

【特許請求の範囲】[Claims] ハードウェアシステムにおける各被診断部の初期状嗜を
記憶しておき、テスト用処現動作の実行後に各被診断部
の応答状態と予め記憶しておいた核初期状態とを比較す
ることによ)各被診断部の状嗜変化の有無を検知し、咳
検知の′結果得られた情報と、各被診断部の状態が変化
すべきか否かを記憶した診断結果判定ブラダとKもとづ
き該ハードウェアシステムの診断を行なうことを特徴と
するハードウェア診断方式。
By memorizing the initial state of each part to be diagnosed in the hardware system and comparing the response state of each part to be diagnosed with the pre-stored core initial state after executing the test processing operation, ) A diagnostic result judgment bladder that detects the presence or absence of a change in the condition of each diagnosed part and stores the information obtained from the cough detection results and whether or not the condition of each diagnosed part should change; A hardware diagnostic method characterized by diagnosing a hardware system.
JP56207142A 1981-12-23 1981-12-23 Hardware diagnostic system Granted JPS58109943A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56207142A JPS58109943A (en) 1981-12-23 1981-12-23 Hardware diagnostic system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56207142A JPS58109943A (en) 1981-12-23 1981-12-23 Hardware diagnostic system

Publications (2)

Publication Number Publication Date
JPS58109943A true JPS58109943A (en) 1983-06-30
JPS6346458B2 JPS6346458B2 (en) 1988-09-14

Family

ID=16534894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56207142A Granted JPS58109943A (en) 1981-12-23 1981-12-23 Hardware diagnostic system

Country Status (1)

Country Link
JP (1) JPS58109943A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5668764A (en) * 1995-03-22 1997-09-16 Texas Instruments Incorporated Testability apparatus and method for faster data access and silicon die size reduction

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5668764A (en) * 1995-03-22 1997-09-16 Texas Instruments Incorporated Testability apparatus and method for faster data access and silicon die size reduction

Also Published As

Publication number Publication date
JPS6346458B2 (en) 1988-09-14

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