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JPS55105390A - Fitting device for semiconductor light emission element - Google Patents

Fitting device for semiconductor light emission element

Info

Publication number
JPS55105390A
JPS55105390A JP1358779A JP1358779A JPS55105390A JP S55105390 A JPS55105390 A JP S55105390A JP 1358779 A JP1358779 A JP 1358779A JP 1358779 A JP1358779 A JP 1358779A JP S55105390 A JPS55105390 A JP S55105390A
Authority
JP
Japan
Prior art keywords
light emission
semiconductor light
piece
emission element
fitting device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1358779A
Other languages
Japanese (ja)
Other versions
JPS5933273B2 (en
Inventor
Kiyoshi Shirakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP54013587A priority Critical patent/JPS5933273B2/en
Publication of JPS55105390A publication Critical patent/JPS55105390A/en
Publication of JPS5933273B2 publication Critical patent/JPS5933273B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

PURPOSE:To select the height of fitting of the LED by choosing a cut part of plural connected plates for the projected piece and by using the piece for the stopper according to the condition of installation. CONSTITUTION:The LED1 is joined to the metal supporter 2 with conductive cement such as silver paste and is connected to the other supporter 3 with gold wire 5 by using bonding agent. Here the supporters 2, 3 are combined with each other with plural connecting plates 7-11. When the connecting plates are cut, the remained part of them is selected so that the projected piece 7a or another one 9a is remained according to the condition of installation, accordingly, the projected pieces 7a, 9a can be used as the stopper to select the hegith of fitting the LED1.
JP54013587A 1979-02-08 1979-02-08 Semiconductor light emitting device mounting equipment Expired JPS5933273B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54013587A JPS5933273B2 (en) 1979-02-08 1979-02-08 Semiconductor light emitting device mounting equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54013587A JPS5933273B2 (en) 1979-02-08 1979-02-08 Semiconductor light emitting device mounting equipment

Publications (2)

Publication Number Publication Date
JPS55105390A true JPS55105390A (en) 1980-08-12
JPS5933273B2 JPS5933273B2 (en) 1984-08-14

Family

ID=11837312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54013587A Expired JPS5933273B2 (en) 1979-02-08 1979-02-08 Semiconductor light emitting device mounting equipment

Country Status (1)

Country Link
JP (1) JPS5933273B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5763901A (en) * 1992-12-17 1998-06-09 Kabushiki Kaisha Toshiba Semiconductor light-emitting device and method for manufacturing the device
US6677614B1 (en) 1992-12-17 2004-01-13 Kabushiki Kaisha Toshiba Semiconductor light-emitting device and method for manufacturing the device
US6808950B2 (en) 1992-12-17 2004-10-26 Kabushiki Kaisha Toshiba Semiconductor light-emitting device and method for manufacturing the device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5763901A (en) * 1992-12-17 1998-06-09 Kabushiki Kaisha Toshiba Semiconductor light-emitting device and method for manufacturing the device
US6677614B1 (en) 1992-12-17 2004-01-13 Kabushiki Kaisha Toshiba Semiconductor light-emitting device and method for manufacturing the device
US6808950B2 (en) 1992-12-17 2004-10-26 Kabushiki Kaisha Toshiba Semiconductor light-emitting device and method for manufacturing the device
US7094619B2 (en) 1992-12-17 2006-08-22 Kabushiki Kaisha Toshiba Method of fabricating a light emitting device
US7288795B2 (en) 1992-12-17 2007-10-30 Kabushiki Kaisha Toshiba Semiconductor light-emitting device and method for manufacturing the device
US7297984B2 (en) 1992-12-17 2007-11-20 Kabushiki Kaisha Toshiba Semiconductor light-emitting device and method for manufacturing the device
US7315046B2 (en) 1992-12-17 2008-01-01 Kabushiki Kaisha Toshiba Semiconductor light-emitting device and method for manufacturing the device

Also Published As

Publication number Publication date
JPS5933273B2 (en) 1984-08-14

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