JPH1197391A - Method of electroplating semiconductor wafer wiring - Google Patents
Method of electroplating semiconductor wafer wiringInfo
- Publication number
- JPH1197391A JPH1197391A JP26933797A JP26933797A JPH1197391A JP H1197391 A JPH1197391 A JP H1197391A JP 26933797 A JP26933797 A JP 26933797A JP 26933797 A JP26933797 A JP 26933797A JP H1197391 A JPH1197391 A JP H1197391A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- wiring
- electrolytic plating
- plating
- electroplating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009713 electroplating Methods 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000000243 solution Substances 0.000 claims abstract description 16
- 239000010949 copper Substances 0.000 claims abstract description 15
- 239000007864 aqueous solution Substances 0.000 claims abstract description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052802 copper Inorganic materials 0.000 claims abstract description 3
- 238000007747 plating Methods 0.000 claims description 45
- 239000000654 additive Substances 0.000 claims description 7
- 230000000996 additive effect Effects 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 230000006866 deterioration Effects 0.000 abstract description 3
- 229910003556 H2 SO4 Inorganic materials 0.000 abstract 1
- 239000003795 chemical substances by application Substances 0.000 abstract 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 abstract 1
- 229910000366 copper(II) sulfate Inorganic materials 0.000 abstract 1
- 239000008151 electrolyte solution Substances 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 6
- 239000007788 liquid Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229920000620 organic polymer Polymers 0.000 description 3
- 125000000129 anionic group Chemical group 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- -1 chlorine ions Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
Landscapes
- Electroplating And Plating Baths Therefor (AREA)
- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体ウエハー面に
形成された微細な配線溝や微細な配線穴に埋め込み配線
を電解メッキで形成する半導体ウエハー配線電解メッキ
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for electroplating a semiconductor wafer wiring by forming an embedded wiring in a fine wiring groove or a fine wiring hole formed on the surface of a semiconductor wafer by electrolytic plating.
【０００２】[0002]
【従来の技術】従来、上記のように半導体ウエハー面に
形成された微細な配線溝や微細な配線穴に埋め込み配線
を電解メッキで形成する方法には、直流電解電流を連続
的に供給して連続してメッキを行うＤＣ電解メッキ法、
メッキとエッチングを繰り返しながらメッキを行うＰＲ
（ペリオディック）電解メッキ法が採用されている。2. Description of the Related Art Conventionally, as described above, a method of forming an embedded wiring in a fine wiring groove or a fine wiring hole formed on a semiconductor wafer surface by electrolytic plating involves continuously supplying a DC electrolytic current. DC electroplating method for continuous plating,
PR that performs plating while repeating plating and etching
The (periodic) electrolytic plating method is employed.
【０００３】[0003]
【発明が解決しようとする課題】上記連続してメッキを
行うＤＣ電解メッキ法においては、メッキ槽内のメッキ
反応域（固液界面）で形成される反応種（ここではＣｕ
2+）の拡散層Ｄの厚さ寸法Ｂが、図１（ａ）に示すよう
に、Ｃｕ埋め込み配線サイズ（配線溝Ｇの深さ寸法）Ａ
より大きくなり、埋め込み電解メッキが不可能になると
いう問題があった。In the DC electroplating method of performing continuous plating, a reactive species (here, Cu) formed in a plating reaction zone (solid-liquid interface) in a plating tank is used.
2+ ), the thickness B of the diffusion layer D is, as shown in FIG. 1 (a), the Cu embedded wiring size (the depth dimension of the wiring groove G) A
However, there is a problem that the embedded electrolytic plating becomes impossible.
【０００４】また、メッキとエッチングを繰り返しなが
らメッキを行うＰＲ電解メッキ法においては、メッキと
エッチングを繰り返すので、メッキのレートが下がり、
スリープットが悪いという問題がある。更に、エッチン
グ時に反応環境がアノード化（＋電場化）するので、メ
ッキ液のアニオン種（例えば、ＳＯ4 2-）がメッキ膜に
吸着され、膜物性が劣化するという問題もあった。In the PR electrolytic plating method in which plating is performed while repeating plating and etching, plating and etching are repeated, so that the plating rate is reduced.
There is a problem that sleep is bad. Further, since the reaction environment becomes anodized (+ electric field) at the time of etching, anionic species (for example, SO 4 2− ) of the plating solution are adsorbed on the plating film, and there is a problem that the film properties are deteriorated.
【０００５】更に、上記ＤＣ電解メッキ法やＰＲ電解メ
ッキ法ではメッキ膜の平滑化、微細結晶化のために有機
高分子からる添加剤の併用が必須であり、メッキ膜中に
Ｃ（炭素）元素が取り込まれ配線材としての膜特性が劣
化するという問題があった。Further, in the DC electrolytic plating method and the PR electrolytic plating method, it is essential to use an additive made of an organic polymer in order to smooth and finely crystallize a plating film, and C (carbon) is contained in the plating film. There is a problem that the element is taken in and the film characteristics as a wiring material deteriorate.
【０００６】本発明は上述の点に鑑みてなされたもの
で、反応種の拡散層を薄くでき、微細な配線溝や微細な
配線穴に埋め込みメッキが可能で、且つスループットの
向上、膜物性の劣化及び膜特性の劣化を防止できる半導
体ウエハー配線電解メッキ方法を提供することを目的と
する。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and can reduce the thickness of a diffusion layer of a reactive species, bury plating in a fine wiring groove or a fine wiring hole, improve throughput, and improve film physical properties. It is an object of the present invention to provide a semiconductor wafer wiring electroplating method capable of preventing deterioration and deterioration of film characteristics.
【０００７】[0007]
【課題を解決するための手段】上記課題を解決するため
請求項１に記載の発明は、半導体ウエハー面に形成され
た幅１．０μｍ以下、アスペクトレシオ（ＡＲ）０．１
〜５０の形状からなる配線溝及び又は配線穴にＣｕ
（銅）の埋め込み配線を電解メッキで形成する半導体ウ
エハー配線電解メッキ方法において、電解メッキの電解
電流にパルス電流を用い、該パルス電流はそのピーク電
流密度が０．０１〜８０．０Ａ／ｄｍ2、パルスデュー
ティ比が０．００９〜０．９９９であることを特徴とす
る。According to a first aspect of the present invention, there is provided a semiconductor wafer having a width of 1.0 μm or less and an aspect ratio (AR) of 0.1 formed on a semiconductor wafer surface.
Cu in the wiring groove and / or wiring hole having a shape of ~ 50
In a method of electrolytic plating a semiconductor wafer wiring in which an embedded wiring of (copper) is formed by electrolytic plating, a pulse current is used as an electrolytic current of the electrolytic plating, and the pulse current has a peak current density of 0.01 to 80.0 A / dm 2. , And the pulse duty ratio is 0.009 to 0.999.
【０００８】また、請求項２に記載の発明は、請求項１
に記載の半導体ウエハー配線電解メッキ方法において、
電解メッキに用いる電解メッキ液はＣｕ2+濃度が０．０
００１〜０．８ｍｏｌ／ｌの電解メッキ液であることを
特徴とする。[0008] The invention described in claim 2 is the first invention.
In the semiconductor wafer wiring electroplating method according to the,
The electrolytic plating solution used for electrolytic plating has a Cu 2+ concentration of 0.0
001 to 0.8 mol / l of an electrolytic plating solution.
【０００９】また、請求項３に記載の発明は、請求項１
又は２に記載の半導体ウエハー配線電解メッキ方法にお
いて、電解メッキ液は添加剤を含まない、ＣｕＳＯ4・
５Ｈ2ＯとＨ2ＳＯ4の水溶液であることを特徴とする。[0009] The invention described in claim 3 is the first invention.
Or the semiconductor wafer interconnect electroplating method according to 2, the electrolytic plating solution without additives, CuSO 4 ·
It is an aqueous solution of 5H 2 O and H 2 SO 4 .
【００１０】また、請求項４に記載の発明は、請求項１
乃至３のいずれか１つに記載の半導体ウエハー配線電解
メッキ方法を用いてメッキした後、該メッキされた半導
体ウエハー表面を化学機械研磨することにより、半導体
ウエハー面の微細溝及び／又は微細穴からなる配線部に
形成されたメッキ膜を残して該半導体ウエハー表面のメ
ッキ膜を除去することを特徴とする半導体ウエハー配線
電解メッキ方法にある。[0010] The invention described in claim 4 is the first invention.
After plating using the semiconductor wafer wiring electroplating method according to any one of (1) to (3), the surface of the plated semiconductor wafer is chemically and mechanically polished so that the fine grooves and / or fine holes on the semiconductor wafer surface are removed. A plating film formed on the surface of the semiconductor wafer while removing the plating film formed on the wiring portion.
【００１１】[0011]
【発明の実施の形態】以下、本発明の実施の形態例を説
明する。図２は本発明の半導体ウエハー配線電解メッキ
方法を実施するメッキ装置の概略構成を示す図である。
本メッキ装置１０はメッキ槽１１を具備し、該メッキ槽
１１内に半導体ウエハーＷを保持するウエハーホルダー
１２とアノード電極１３が対向して配置されている。該
ウエハーホルダー１２に半導体ウエハーＷを保持するこ
とにより、該半導体ウエハーＷの上面とアノード電極１
３は対向する。Embodiments of the present invention will be described below. FIG. 2 is a diagram showing a schematic configuration of a plating apparatus for performing the semiconductor wafer wiring electrolytic plating method of the present invention.
The present plating apparatus 10 includes a plating tank 11, in which a wafer holder 12 for holding a semiconductor wafer W and an anode electrode 13 are arranged to face each other. By holding the semiconductor wafer W on the wafer holder 12, the upper surface of the semiconductor wafer W and the anode electrode 1
3 are opposed.
【００１２】１４は正のパルス電流を出力するパルス電
源であり、１５は例えばクーロンメータ等の電気量計で
ある。パルス電源１４の陽極はアノード電極１３に接続
され、陰極はウエハーホルダー１２に保持された半導体
ウエハーＷに接続される。また、メッキ槽１１内には電
解メッキ液Ｑが収容されている。該電解メッキ液Ｑは塩
素イオンや有機高分子等の添加剤を含まない、ＣｕＳＯ
4・５Ｈ2ＯとＨ2ＳＯ4からなる水溶液の電解メッキ液で
ある。Reference numeral 14 denotes a pulse power supply for outputting a positive pulse current, and reference numeral 15 denotes an electricity meter such as a coulomb meter. The anode of the pulse power supply 14 is connected to the anode electrode 13, and the cathode is connected to the semiconductor wafer W held by the wafer holder 12. The plating bath 11 contains an electrolytic plating solution Q. The electrolytic plating solution Q contains no additives such as chlorine ions and organic polymers,
4 is an electrolytic plating solution of the aqueous solution consisting of · 5H 2 O and H 2 SO 4.
【００１３】また、半導体ウエハーＷの上面には幅１．
０μｍ以下、アスペクトレシオ（ＡＲ）０．１〜５０の
形状からなる微細な配線溝や微細な配線穴が形成されて
いる。On the upper surface of the semiconductor wafer W, the width 1.
Fine wiring grooves and fine wiring holes having an aspect ratio (AR) of 0.1 to 50 μm or less are formed.
【００１４】上記構成のメッキ装置において、パルス電
源１４から図３に示すような、正のパルスＰを、アノー
ド電極１３に供給することにより、半導体ウエハーＷの
上面の配線溝や配線穴にＣｕメッキが埋め込み形成され
る。このようにパルスＰをアノード電極１３に供給する
ことにより、アノード電極１３と半導体ウエハーＷの間
に流れる電流は断続電流となり、メッキ反応域（固液界
面）で形成される反応種Ｃｕ2+の拡散層Ｄの厚さ寸法Ｂ
はＤＣ電解メッキ法やＰＲ電解メッキ法の場合に比較し
て小さくなり、パルスＰのデューティ比を適当に制御す
ることにより、図１（ｂ）に示すように、拡散層Ｄの厚
さ寸法Ｂを配線溝や配線穴Ｇの深さ寸法Ａより小さく
（Ｂ＜Ａ）することができる。In the plating apparatus having the above structure, a positive pulse P as shown in FIG. 3 is supplied from the pulse power supply 14 to the anode electrode 13 so that the wiring groove or the wiring hole on the upper surface of the semiconductor wafer W is plated with Cu. Is buried. By supplying the pulse P to the anode electrode 13 as described above, the current flowing between the anode electrode 13 and the semiconductor wafer W becomes an intermittent current, and the reaction species Cu 2+ formed in the plating reaction region (solid-liquid interface) is formed. Thickness B of diffusion layer D
Is smaller than in the case of the DC electrolytic plating method or the PR electrolytic plating method, and by appropriately controlling the duty ratio of the pulse P, as shown in FIG. Can be smaller than the depth dimension A of the wiring groove or the wiring hole G (B <A).
【００１５】なお、図１（ａ）はＤＣ電解メッキ法やＰ
Ｒ電解メッキ法の場合の半導体ウエハーＷの面上に形成
される拡散層Ｄの状態を、図１（ｂ）は電解電流にパル
ス電流を用いた場合の半導体ウエハーＷの面上に形成さ
れる拡散層Ｄの状態をそれぞれ示す。FIG. 1A shows a DC electrolytic plating method and P
FIG. 1B shows the state of the diffusion layer D formed on the surface of the semiconductor wafer W in the case of the R electrolytic plating method, and FIG. 1B shows the state of the diffusion layer D formed on the surface of the semiconductor wafer W when the pulse current is used as the electrolytic current. Each state of the diffusion layer D is shown.
【００１６】図１（ｂ）に示すように、拡散層Ｄの厚さ
寸法Ｂを配線溝や配線穴Ｇの深さ寸法Ａより小さくする
ことができるので、反応種Ｃｕ2+の供給律速が配線溝や
配線穴Ｇの中で発生することがなく、緻密なメッキ膜が
配線溝や配線穴Ｇ内に均一に形成できる。As shown in FIG. 1B, since the thickness B of the diffusion layer D can be made smaller than the depth A of the wiring groove or the wiring hole G, the rate of supply of the reactive species Cu 2+ is limited. The dense plating film can be uniformly formed in the wiring groove or the wiring hole G without being generated in the wiring groove or the wiring hole G.
【００１７】ここで緻密なメッキ膜を形成できる適切な
パルス電解条件を図３を用いて説明すると、パルスＰの
ピーク電流密度Ｉｐは、 Ｉｐ＝０．０１〜８０．０Ａ／ｄｍ2 であり、パルスデューティ比θは、 θ＝Ｔｏｎ／Ｔ＝０．００９〜０．９９９ である。Here, the appropriate pulse electrolysis conditions for forming a dense plating film will be described with reference to FIG. 3. The peak current density Ip of the pulse P is Ip = 0.01 to 80.0 A / dm 2 , The pulse duty ratio θ is θ = Ton / T = 0.09 to 0.999.
【００１８】また、緻密なメッキ膜を形成できる適切な
Ｃｕ2+濃度は、０．０００１〜０．８ｍｏｌ／ｌの範囲
内である。An appropriate Cu 2+ concentration for forming a dense plating film is in the range of 0.0001 to 0.8 mol / l.
【００１９】上記のように、電解メッキにパルス電流を
用いることにより、拡散層Ｄの厚さ寸法Ｂを配線溝や配
線穴Ｇの深さ寸法Ａより小さくできるから、幅が１．０
μｍ以下、アスペクトレシオ（ＡＲ）０．１〜５０の微
細な配線溝や微細な配線穴に埋め込みメッキが可能とな
る。また、ＰＲ電解メッキ法のように、メッキとエッチ
ングを繰り返さないので、メッキレートを下げることな
く電解メッキが可能となり、スループットが向上する。As described above, the thickness B of the diffusion layer D can be made smaller than the depth A of the wiring groove or the wiring hole G by using the pulse current for the electrolytic plating.
Embedding plating can be performed in a fine wiring groove or a fine wiring hole having an aspect ratio (AR) of 0.1 to 50 μm or less. Also, unlike the PR electrolytic plating method, plating and etching are not repeated, so that electrolytic plating can be performed without reducing the plating rate, and the throughput is improved.
【００２０】また、ＰＲ電解メッキ法のようにエッチン
グ時に反応環境がアノード化されることがないので、メ
ッキ液中のＳＯ4 2-等のアニオン種がメッキ膜に吸着さ
れることなく、膜物性が劣化することはない。Further, since the reaction environment is not anodized at the time of etching as in the case of the PR electrolytic plating method, anionic species such as SO 4 2- in the plating solution are not adsorbed on the plating film, and the physical properties of the film are reduced. Does not deteriorate.
【００２１】また、ＤＣ電解メッキ法やＰＲ電解メッキ
法ではメッキ膜の平滑化、微細結晶化のために、電解メ
ッキ液に有機高分子の添加剤が必須となるが、ここでは
電解メッキ液Ｑに添加剤を含まないので、メッキ膜中に
Ｃ元素が取り込まれることなく、配線材としての膜特性
が劣化することがない。In the DC electrolytic plating method and the PR electrolytic plating method, an organic polymer additive is essential to the electrolytic plating solution for smoothing and fine crystallization of the plating film. Since no additive is contained in the plating film, the C element is not taken into the plating film, and the film characteristics as a wiring material do not deteriorate.
【００２２】なお、図２に示すメッキ装置の概略構成は
本発明の半導体ウエハー配線電解メッキ方法を実施する
ための一例であり、本発明に用いるメッキ装置はこの構
成に限定されるものでないことは当然である。The schematic configuration of the plating apparatus shown in FIG. 2 is an example for carrying out the electrolytic plating method for semiconductor wafer wiring of the present invention, and the plating apparatus used in the present invention is not limited to this configuration. Of course.
【００２３】上記電解メッキ方法により、図４（ａ）に
示すように、半導体ウエハー１００の例えばＳｉＯ2絶
縁層１０２の面上に形成された微細溝１０３や微細穴
（コンタクトホール）１０１からなる配線部に同図
（ｂ）に示すように、電解メッキ層（膜）１０７を形成
する。その後化学機械研磨（ＣＭＰ）機を用いて同図
（ｃ）に示すように、配線部に形成された電解メッキ層
１０７を残して該半導体ウエハー１００表面の電解メッ
キ層１０７を除去する。これにより、微細溝１０３や微
細穴１０１からなる配線部にのみ電解メッキ層が形成さ
れることになる。なお、図６において、１０５バリア
層、１０４は導電体層である。By the above-described electrolytic plating method, as shown in FIG. 4A, a wiring comprising fine grooves 103 and fine holes (contact holes) 101 formed on the surface of, for example, an SiO 2 insulating layer 102 of a semiconductor wafer 100. An electrolytic plating layer (film) 107 is formed on the portion as shown in FIG. Thereafter, as shown in FIG. 3C, the electrolytic plating layer 107 on the surface of the semiconductor wafer 100 is removed using a chemical mechanical polishing (CMP) machine, leaving the electrolytic plating layer 107 formed on the wiring portion. As a result, the electrolytic plating layer is formed only on the wiring portion including the fine grooves 103 and the fine holes 101. In FIG. 6, reference numeral 105 denotes a barrier layer and reference numeral 104 denotes a conductor layer.
【００２４】[0024]
【発明の効果】以上説明したように本願各請求項に記載
の発明によれば、電解メッキにパルス電流を用い、該パ
ルス電流のピーク電流密度を０．０１〜８０．０Ａ／ｄ
ｍ2、パルスデューティ比を０．００９〜０．９９９と
するので、幅１．０μｍ以下、深さ１．０μｍ以下の形
状からなる微細な配線溝及び／又は微細な配線穴にＣｕ
の埋め込み配線を高いスループットで形成することがで
きる。As described above, according to the present invention, a pulse current is used for electrolytic plating, and the peak current density of the pulse current is 0.01 to 80.0 A / d.
m 2 , and the pulse duty ratio is 0.009 to 0.999, so that a fine wiring groove and / or a fine wiring hole having a width of 1.0 μm or less and a depth of 1.0 μm or less
Embedded wiring can be formed with high throughput.
【００２５】また、請求項３に記載の発明によれば、電
解メッキ液に添加剤を含まない、ＣｕＳＯ4・５Ｈ2Ｏと
Ｈ2ＳＯ4の水溶液を用いるので、メッキ膜中に不純物の
取り込みが少なく、配線材としての膜特性が向上する。Further, according to the invention described in claim 3, no additive in the electroplating solution, since an aqueous solution of CuSO 4 · 5H 2 O and H 2 SO 4, the impurities in the plating film uptake And the film characteristics as a wiring material are improved.
【図１】電解メッキ槽内のメッキ反応域（固液界面）で
形成される反応種の拡散層の状態を示す図で、同図
（ａ）はＤＣ又はＰＲ電解メッキ法による場合、同図
（ｂ）はパルス電解メッキ法による場合をそれぞれ示
す。FIG. 1 is a view showing a state of a diffusion layer of a reactive species formed in a plating reaction zone (solid-liquid interface) in an electrolytic plating tank. FIG. (B) shows the case of the pulse electrolytic plating method.
【図２】本発明の半導体ウエハー配線電解メッキ方法を
実施するためのメッキ装置の一構成例を示す図である。FIG. 2 is a view showing one configuration example of a plating apparatus for performing a semiconductor wafer wiring electrolytic plating method of the present invention.
【図３】本発明の半導体ウエハー配線電解メッキ方法に
用いるパルス電流の波形を示す図である。FIG. 3 is a diagram showing a waveform of a pulse current used in the electrolytic plating method for semiconductor wafer wiring of the present invention.
【図４】本発明の半導体ウエハー配線電解メッキ方法を
用いて半導体ウエハー面上の配線部に配線メッキを形成
する工程を示す図である。FIG. 4 is a view showing a step of forming wiring plating on a wiring portion on a semiconductor wafer surface using the semiconductor wafer wiring electrolytic plating method of the present invention.
１０ メッキ装置 １１ メッキ槽 １２ ウエハーホルダー １３ アノード電極 １４ パルス電源 １５ 電気量計 DESCRIPTION OF SYMBOLS 10 Plating apparatus 11 Plating tank 12 Wafer holder 13 Anode electrode 14 Pulse power supply 15 Electricity meter
Claims (4)
μｍ以下、アスペクトレシオ（ＡＲ）０．１〜５０の形
状からなる配線溝及び又は配線穴にＣｕ（銅）の埋め込
み配線を電解メッキで形成する半導体ウエハー配線電解
メッキ方法において、 前記電解メッキの電解電流にパルス電流を用い、該パル
ス電流はそのピーク電流密度が０．０１〜８０．０Ａ／
ｄｍ2、パルスデューティ比が０．００９〜０．９９９
であることを特徴とする半導体ウエハー配線電解メッキ
方法。1. A semiconductor device having a width of 1.0 formed on a surface of a semiconductor wafer.
In a semiconductor wafer wiring electrolytic plating method for forming an embedded wiring of Cu (copper) in a wiring groove and / or a wiring hole having a shape of aspect ratio (AR) of 0.1 to 50 or less by electrolytic plating, the electrolytic plating A pulse current is used as the current, and the pulse current has a peak current density of 0.01 to 80.0 A /
dm 2 , pulse duty ratio 0.009 to 0.999
A method for electrolytic plating a wiring on a semiconductor wafer.
Ｃｕ2+濃度が０．０００１〜０．８ｍｏｌ／ｌの電解メ
ッキ液であることを特徴とする請求項１に記載の半導体
ウエハー配線電解メッキ方法。2. The electrolytic plating solution according to claim 1, wherein the electrolytic plating solution used for the electrolytic plating is an electrolytic plating solution having a Cu 2+ concentration of 0.0001 to 0.8 mol / l. Method.
ＣｕＳＯ4・５Ｈ2ＯとＨ2ＳＯ4の水溶液であることを特
徴とする請求項１又は２に記載の半導体ウエハー配線電
解メッキ方法。3. The electroplating solution does not contain an additive.
CuSO 4 · 5H 2 O and the semiconductor wafer interconnect electroplating method according to claim 1 or 2, characterized in that an aqueous solution of H 2 SO 4.
記載の半導体ウエハー配線電解メッキ方法を用いてメッ
キした後、該メッキされた半導体ウエハー表面を化学機
械研磨することにより、前記半導体ウエハー面の微細溝
及び／又は微細穴からなる配線部に形成されたメッキ膜
を残して該半導体ウエハー表面のメッキ膜を除去するこ
とを特徴とする半導体ウエハー配線電解メッキ方法。4. The method according to claim 1, wherein the semiconductor wafer is plated using the method for electrolytic plating of a semiconductor wafer wiring, and then the surface of the plated semiconductor wafer is subjected to chemical mechanical polishing. A method for electroplating a semiconductor wafer wiring, wherein the plating film on the surface of the semiconductor wafer is removed while leaving a plating film formed on a wiring portion formed of fine grooves and / or fine holes on the wafer surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26933797A JPH1197391A (en) | 1997-09-16 | 1997-09-16 | Method of electroplating semiconductor wafer wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26933797A JPH1197391A (en) | 1997-09-16 | 1997-09-16 | Method of electroplating semiconductor wafer wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1197391A true JPH1197391A (en) | 1999-04-09 |
| JPH1197391A5 JPH1197391A5 (en) | 2004-09-30 |
Family
ID=17470971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26933797A Pending JPH1197391A (en) | 1997-09-16 | 1997-09-16 | Method of electroplating semiconductor wafer wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1197391A (en) |
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| JPH11238704A (en) * | 1998-02-23 | 1999-08-31 | Ideya:Kk | Semiconductor substrate wiring groove plating method and plating apparatus |
| JP2000174025A (en) * | 1998-12-02 | 2000-06-23 | Internatl Business Mach Corp <Ibm> | Electro-migration resistant microstructure and method of manufacturing the same |
| JP2000353675A (en) * | 1999-05-03 | 2000-12-19 | Motorola Inc | Method for forming a copper layer on a semiconductor wafer |
| WO2001007687A1 (en) * | 1999-07-26 | 2001-02-01 | Tokyo Electron Limited | Plating method and device, and plating system |
| JP2001152387A (en) * | 1999-09-16 | 2001-06-05 | Ishihara Chem Co Ltd | Void-free copper plating method |
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| US7229916B2 (en) | 2003-07-18 | 2007-06-12 | Nec Electronics Corporation | Method of manufacturing a semiconductor device |
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| JPH11238704A (en) * | 1998-02-23 | 1999-08-31 | Ideya:Kk | Semiconductor substrate wiring groove plating method and plating apparatus |
| JP2000174025A (en) * | 1998-12-02 | 2000-06-23 | Internatl Business Mach Corp <Ibm> | Electro-migration resistant microstructure and method of manufacturing the same |
| JP2000353675A (en) * | 1999-05-03 | 2000-12-19 | Motorola Inc | Method for forming a copper layer on a semiconductor wafer |
| WO2001007687A1 (en) * | 1999-07-26 | 2001-02-01 | Tokyo Electron Limited | Plating method and device, and plating system |
| US6607650B1 (en) | 1999-07-26 | 2003-08-19 | Tokyo Electron Ltd. | Method of forming a plated layer to a predetermined thickness |
| JP2001152387A (en) * | 1999-09-16 | 2001-06-05 | Ishihara Chem Co Ltd | Void-free copper plating method |
| KR20030095005A (en) * | 2002-06-11 | 2003-12-18 | 김재정 | Fabricating Method of Matal Film for Semiconductor Interconnection |
| US7229916B2 (en) | 2003-07-18 | 2007-06-12 | Nec Electronics Corporation | Method of manufacturing a semiconductor device |
| WO2009055989A1 (en) * | 2007-10-30 | 2009-05-07 | Acm Research (Shanghai) Inc. | Method and apparatus to prewet wafer surface for metallization from electrolyte solution |
| KR101487708B1 (en) * | 2007-10-30 | 2015-01-29 | 에이씨엠 리서치 (상하이) 인코포레이티드 | Method and apparatus to prewet wafer surface for metallization from electrolyte solution |
| US9295167B2 (en) | 2007-10-30 | 2016-03-22 | Acm Research (Shanghai) Inc. | Method to prewet wafer surface |
| JP2012132058A (en) * | 2010-12-21 | 2012-07-12 | Ebara Corp | Electroplating method |
| US9376758B2 (en) | 2010-12-21 | 2016-06-28 | Ebara Corporation | Electroplating method |
| JP2013033893A (en) * | 2011-06-28 | 2013-02-14 | Sharp Corp | Optical semiconductor element and manufacturing method of optical semiconductor element |
| US10329683B2 (en) | 2016-11-03 | 2019-06-25 | Lam Research Corporation | Process for optimizing cobalt electrofill using sacrificial oxidants |
| US11078591B2 (en) | 2016-11-03 | 2021-08-03 | Lam Research Corporation | Process for optimizing cobalt electrofill using sacrificial oxidants |
| JP2018093034A (en) * | 2016-12-01 | 2018-06-14 | 株式会社カネカ | Manufacturing method for solar battery and plating device for electrode formation |
| JPWO2019130859A1 (en) * | 2017-12-27 | 2020-12-17 | 株式会社カネカ | Manufacturing method of photoelectric conversion element, plating jig, plating equipment |
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