JPH1194905A - Semiconductor tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor tester which corrects skew in phase between clocks to minimize phase error similar to the error in the correction of the phase of linearity while leaving a block structure unchanged. SOLUTION: This apparatus corrects the phase of linearity of clocks by controlling a fine delay circuit 20 based on a data of a linearizing memory 14. In this case, a phase correction data of the linearity is preserved as offset file by a step of the resolutions of the fine delay circuit 20 and linearization memory 14 is reloaded by a data of an offset file, thereby correcting skew between the clocks.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus capable of accurately correcting a clock skew phase.

[0002]

2. Description of the Related Art An example of the prior art will be described with reference to FIGS. First, an outline of the semiconductor test apparatus will be described. As shown in FIG. 4, an example of the semiconductor test apparatus includes a workstation 70 serving as an interface with an operator, a semiconductor test apparatus main body 80, and a test head 90 serving as an interface with a device under test.

[0005] The semiconductor test apparatus tests a DUT 91 as a device under test mounted on a test head 90.

Next, an example of a block configuration of a semiconductor test apparatus and an outline of its operation will be described. As shown in FIG. 5, a main unit of a conventional semiconductor test apparatus includes a timing generator 10, a pattern generator 30, a waveform shaper 40, a driver 50, and a comparator 51. The control of the semiconductor test apparatus is performed by the workstation 70.
, A memory 71, and a tester processor 60,
Each unit is controlled via the bus interface 61.

Next, the operation of the main unit will be described. The timing generator 10 generates a test rate for the entire apparatus and a clock for timing pulses.

The pattern generator 30 generates a signal of a logical pattern to be given to the DUT 91 and a signal of an expected value pattern to be given to the comparator 51.

The waveform shaper 40 shapes the waveform of the logical pattern signal from the pattern generator 30 by using a clock.
A test signal is applied to the DUT 91 via the driver 50. For example, as shown in FIG.
CLK and the clock BCLK of the phase t2, the waveform is shaped and output.

The comparator 51 logically compares the output signal of the DUT 91 and the expected value signal from the pattern generator 30 with a strobe (clock) timing pulse, detects a match / mismatch, and determines pass / fail. ing.

Next, an outline of calibration of the semiconductor test apparatus will be described. Usually, semiconductor test equipment
Calibration is performed when test conditions and temperatures change to ensure test accuracy. In the calibration, items relating to timing include phase correction of clock linearity and phase correction of skew between clocks.

Generally, the phase of a clock is realized by combining the delay times of the respective delay time elements, but the added delay time may not be a simple sum of the respective delay time elements before the addition. For example, the delay time elements are 2 ns and 4 ns
In the case of, the added delay time does not become 6 ns but 5.9 n
or s. That is, since the set value of the clock delay time and the delay time do not change linearly, it is necessary to correct the clock linearity.

As shown in FIG. 8, a plurality of clocks, for example, ACLK and BCLK are generated in the semiconductor test apparatus. Therefore, when the same phase is set for each clock in the output of the driver 50, the skew between clocks is generated. It is necessary to correct the phase so as to reduce the phase.

Next, phase correction of clock linearity and phase correction of skew between clocks will be described. As shown in FIG. 6, the phase of the clock is changed by the amount of delay passing through the logic delay circuit 11 and the minute delay circuit 20. In the logic delay circuit 11 and the minute delay circuit, data of each delay time is set in the delay amount setting memory 12, the phase correction register 13, and the linearize memory 14.

The logic delay circuit 11 is a delay circuit that causes a counter to delay the phase in units of a reference clock. Further, as shown in FIG. 7, the minute delay circuit is a delay circuit that switches by the multiplexers 21 to 2n using a semiconductor delay to minutely delay by a phase difference.

For example, the logic delay circuit 11 has 16n
Upon receiving the s reference clock, a delay time from 16 ns to the cycle of the test rate can be set. Then, the minute delay circuit 20 has 8 ns, 4 ns, 2 ns,.
, 125 ps,..., 20 ps can be set in combination. Here, the set resolution of the clocks ACLK and BCLK is 125 ps, and the delay time with a smaller resolution is used for the phase correction of the linearity.

The phase of each clock is obtained by feeding back the clock from the driver output to the input to cause loop oscillation, measuring the frequency with a counter, calculating the period from the measured value, and accurately obtaining the phase as a delay time. ing.

Next, referring to the flowchart shown in FIG. 10, a method of correcting the phase of the clock skew and the clock skew will be described in a bulleted manner.

(1) Set the phase correction register 13 to an intermediate value. For example, if the phase correction register 13 is # 0 to #F
, # 8 is set (step 200).

(2) The correction data for each set value of the linearity is obtained by performing a linearization with an error of 20 ps in the resolution of the minute delay circuit, and the linearity correction data a [0], a [1],.・ ・ The file (FIL
E) is stored in the memory 71 (step 210).

(3) Correction data a [0], a [1],... Of the file (FILE) are stored in the linearization memory 14.
Is written (step 211).

(4) As seen from the output of the driver 50, if the skew between clocks is not less than the set resolution of 125 ps, the process proceeds to step 230 (step 220). If the skew between clocks is less than the set resolution of 125 ps as seen from the output of the driver, the process ends.

(5) Steps 220 and 230 are repeated until the skew between clocks is less than the set resolution of 125 ps, and the data in the phase correction register 13 is rewritten (step 230).

As a result, the phase error of the clock linearity can be corrected in the range of 20 ps, which is the minimum resolution of the minute delay circuit. However, the skew between clocks is
Since the clock setting resolution is 125 ps, a maximum of 12
An error of 5 ps occurs.

In this embodiment, the case where the number of clocks is two has been described for the sake of simplicity. However, an actual semiconductor test apparatus has 24 to 68 clocks.

[0024]

As described above, by performing the timing calibration,
Although the phase correction of the linearity of the clock has an error range of 20 ps, the skew between the clocks has an error range of 125 ps, which has a large phase error and is inconvenient for practical use. Therefore, the present invention has been made in view of such a problem, and an object of the present invention is to reduce the skew between clocks to a small phase error similar to the error of the linearity phase correction while keeping the same unit configuration as in the related art. An object of the present invention is to provide a semiconductor test device.

[0025]

That is, a first aspect of the present invention to achieve the above object is to correct a skew between clocks with a correction resolution of clock linearity. The device is the gist.

That is, a second aspect of the present invention, which has been made to achieve the above object, is to provide a semiconductor test apparatus for controlling a phase of a clock linearity by controlling a minute delay circuit by using data of a linearize memory. A gist of the present invention is a semiconductor test apparatus characterized in that phase correction data of linearity is stored as an offset file in a step of a resolution of a circuit, and the linearization memory is rewritten with data of the offset file to correct skew between clocks. .

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following examples.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 1 to 5 and FIG. The block configuration of the semiconductor test apparatus of the present invention is the same as the conventional one as shown in FIG.

However, as shown in FIGS. 1 and 7, the logic delay circuit 11 and the minute delay circuit 20 are the same, but the data file to be written in the linearize memory 14 is different. Then, the logic delay circuit 11 as in the prior art
Sets the delay time from 16 ns to the cycle of the clock rate, and the minute delay circuit has 8 ns, 4 ns, 2 ns,.
, 125 ps,..., 20 ps. As in the conventional case, the resolution of the clock set by the phase correction register 13 is 125 ps, and the resolution of the small delay time of the minute delay circuit 20 by the linearize memory 14 is the phase correction of the linearity.

Next, with reference to the flowchart shown in FIG. 2, a method of correcting the phase of the clock linearity and the clock skew according to the present invention will be described below in a bulleted manner.

(1) Set the phase correction register 13 to an intermediate value. For example, if the phase correction register 13 is # 0 to #F
, # 8 is set (step 100).

(2) The linearity phase correction resolution is
The offset resolution is Δps. For example, the resolution Δps of the offset is set to 2 which is the same as the minimum resolution of the linearity.
It is set to 0 ps, and the initial value of the offset is set to 0 ps (step 110).

(3) Perform linearization at the set offset. Then, the linearity correction result is stored in the memory 71 as a linearization file for the offset (step 120).

(4) If the offset is within 125 ps, the process proceeds to step 140, where the offset is 125 ps.
If it is less than the value, the process proceeds to step 150 (step 13
0). .

(5) The offset is Δps, that is, 20
The delay time of ps is added (step 140). Then, steps 120 and 140 are repeated to create a linearized file for each offset Δps. For example, as shown in FIGS. 1 and 3, a FILE with an offset of 0 ps and a FIL with an offset of 120 ps
Create EM in 20ps steps.

(6) FILE 1 data a [0], a [1],.
Is written (step 141).

(7) If the skew between clocks is larger than 125 ps as viewed from the output of the driver (step 16)
Proceed to 0) (step 150). If the skew between clocks is less than 125 ps as seen from the output of the driver, the process proceeds to step 180.

(8) Rewrite the setting of the phase correction register 13 and return to step 150 (step 160). Steps 150 and 160 are repeated until the skew between clocks is less than 125 ps. (9) If the skew between clocks is less than 125 ps, in order to correct by adding an offset, if the clock to be corrected has a phase earlier than the target point, the data to be corrected remains unchanged and the clock to be corrected is phase shifted from the target point. If the phase is later, the phase correction register 13 is set by rewriting the data of the previous phase to the earlier data (step 161).

(10) If the skew between clocks is less than 125 ps as seen from the output of the driver, the phase correction register 13 is set immediately before the phase correction to add a delay time for phase correction due to offset. . When viewed from the output of the driver 50, the skew between clocks is Δps,
That is, if it is larger than 20 ps, the process proceeds to step 190 (step 180). In addition, the skew between clocks is Δps, that is, 20 ps when viewed from the output of the driver 50.
If it is within, it ends. (11) Rewrite the offset by Δps, that is, the data of the offset file added by 20 ps (step 190). Then, returning to Step 180, Steps 180 and 190 are repeated until the skew between clocks becomes Δps, that is, within 20 ps.

As a result, the phase error of the linearity is
As in the conventional case, the phase can be corrected within the minimum resolution range of 20 ps of the minute delay circuit. On the other hand, the skew between clocks is 125 ps as the clock setting resolution, but by rewriting the data in the offset file, the phase can be corrected within an error range of 20 ps, which is the minimum resolution of the minute delay circuit.

In the flowcharts of FIGS. 2 and 10, the procedure is omitted for the sake of simplicity. In the phase correction of the skew between clocks, the phase error before and after the target phase timing is exceeded is corrected. By setting the correction value having the smaller phase error in the phase correction register, the skew between clocks can be reduced to １ ／ of the clock resolution.
Error. Similarly, in the linearity correction, by writing the file data having the smaller phase error to the linearization memory, the skew between clocks can be reduced to an error of の of the resolution of the linearity correction.

[0042]

The present invention is embodied in the form described above and has the following effects. That is,
With the same unit configuration as in the related art, there is an effect that the skew between clocks can be made a small phase error similar to the error of the phase correction of linearity. In other words, the clock skew has a clock setting resolution of 125 ps, but by rewriting the offset file, a high-precision semiconductor test apparatus having an error range of 20 ps, which is the minimum resolution of the minute delay circuit, can be obtained.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing a phase correction method of a semiconductor test apparatus according to the present invention.

FIG. 2 is a flowchart of phase correction according to the present invention.

FIG. 3 is a diagram showing linearized data for performing phase correction between clocks.

FIG. 4 is an external view of a semiconductor test apparatus.

FIG. 5 is a main block diagram of a semiconductor test apparatus.

FIG. 6 is a main block diagram showing a phase correction method of a conventional semiconductor test apparatus.

FIG. 7 is a circuit diagram illustrating an example of a minute delay circuit;

FIG. 8 is a diagram showing skew between clocks.

FIG. 9 is a diagram showing waveform shaping by a clock.

FIG. 10 is a flowchart of a conventional phase correction.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Timing generator 11 Logic delay circuit 12 Delay amount setting memory 13 Phase correction register 14 Linearization memory 20 Micro delay circuit 30 Pattern generator 40 Waveform shaper 50 Driver 51 Comparator 60 Tester processor 61 Bus interface 70 Workstation 71 Memory 80 Semiconductor Test equipment main body 90 Test head 91 DUT

Claims (2)

[Claims] 1. A semiconductor test apparatus, wherein a skew between clocks is corrected by a correction resolution of clock linearization. 2. A semiconductor test apparatus for controlling a phase of a clock linearity by controlling a micro-delay circuit based on data of a linearization memory, wherein the phase correction data of the linearity is stored as an offset file at a resolution step of the micro-delay circuit. A semiconductor test apparatus, wherein the linearized memory is rewritten with data of an offset file to correct skew between clocks.