JPH1187512A - Wiring structure of semiconductor integrated circuit - Google Patents

Abstract

(57) [Problem] To realize high-speed and low-impedance signal wiring in a space equivalent to that of the related art, and to enable higher-speed operation without being restricted by wiring parasitic effects. A ground wiring having a width is formed as a first metal wiring layer on an upper surface of a semiconductor substrate.
On the ground wiring 12 and the upper surface of the semiconductor substrate 11,
An interlayer insulating film 13 is formed. A signal wiring 14 having a width W is formed as a second metal wiring layer above the central part of the ground wiring 12 on the interlayer insulating film 13. The wiring structure of this semiconductor integrated circuit has a ground wiring 1
2 and the signal wiring 14 are laminated, and a microstrip line is formed by the ground wiring 12 and the signal wiring 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a wiring structure useful for improving a circuit operation speed in a high-speed logic integrated circuit using a compound semiconductor.

[0002]

2. Description of the Related Art In a small-scale logic integrated circuit such as a signal discriminating circuit or a signal multiplexing circuit, a signal line connection between logic circuit cells usually requires a wiring length of about several hundred μm to about 1 mm. Normally, as a high-speed circuit, the signal wiring length is reduced as much as possible as a basic design technique.

In designing a signal wiring, the characteristic impedance is not considered, and so-called impedance matching design is not performed. This is because when the signal wiring length is about 1/10 or less of the wavelength of a signal propagating through the signal wiring, the signal wiring can be modeled as a simple lumped element, and the characteristics of the signal line can be modeled. This is because there is no need to worry about waveform distortion due to multiple reflection caused by mismatch between the impedance and the input / output impedance of the circuit connecting the line.

In the case of an ultra-high-speed logic circuit, a bit rate of about 20 Gbit / s is conventionally the upper limit, but when a signal wiring is laid on any wiring layer on a semiconductor substrate, the bit rate is about 400 μm. The wiring length can be treated as a lumped constant. In this case, when the signal wiring is electrically viewed, the parasitic capacitance component is mainly present, the contribution of the parasitic inductance component is small, and the product of the resistance component of the terminal connected to the line and the capacitance component including the parasitic capacitance of the wiring. Will determine the circuit operating speed.

Therefore, in the prior art, FIG.
Alternatively, the structure shown in FIG. For example, in FIG. 7A, in the wiring structure of the semiconductor integrated circuit, a wiring layer 2 is formed on a semiconductor substrate 1, and an interlayer insulating film 3 is further formed on the wiring layer 2 and the semiconductor substrate 1. . Alternatively, as shown in FIG. 7B, an interlayer insulating film 3 is formed on a semiconductor substrate 1, and
The wiring layer 2 is formed thereon.

As described above, conventionally, the focus has been on suppressing the parasitic capacitance component in the high-frequency signal connection between the cells, and the wiring layer 2 is formed of a first or second layer having a narrow line width. Was used. In this case, 1) the dielectric constant of the semiconductor substrate can be seen, and particularly in the case of a compound semiconductor, the effective dielectric constant is as high as about 7, and the wavelength shortening rate is large (in other words, the propagation speed is low). 2) The characteristic impedance of the line is as high as about 150Ω and does not match the output impedance of a high-speed logic circuit which is as low as 50Ω or less.

However, with the improvement of the circuit operation speed, the signal wiring gradually starts to appear as a distributed constant line.
Above Gbit / s, the circuit operation speed was greatly limited by the parasitic effect of the signal wiring.

[0008]

Due to the nature of the above-mentioned prior art, several tens of G, in particular, where the wiring length becomes equal to the signal wavelength.
In a high-speed operation region of b / s or more, the wiring propagation delay time and the waveform distortion due to multiple reflections have become apparent as factors that limit the circuit operation speed. Hereinafter, this will be described in detail.

In a high-speed logic circuit, an emitter-coupled logic circuit (ECL) is used.
Logic) or a source-coupled FET logic circuit (SC
FL: Source Coupled FET Log
ic). An emitter follower or a source follower having a high load driving power is commonly used as an output of these logic circuits.

The output impedance of these circuits is roughly given by the reciprocal of the transconductance of the transistors constituting them, and is as low as several tens of ohms or less. For example, the emitter follower has a resistance of 10Ω or less, and the source follower has a resistance of about 20 to 60Ω.

On the other hand, the input of the logic circuit is the base or gate electrode of the transistor, and the input impedance thereof is as high as several hundreds Ω or more in the emitter-coupled logic circuit and several kΩ or more in the source-coupled FET logic circuit. Therefore,
As the bit rate increases, the length of the signal wiring connecting them becomes longer than 1/10 of the signal wavelength, and the characteristic impedance of the signal wiring (up to 180Ω) does not match the output impedance of the logic circuit (several tens of Ω or less). Therefore, the output signal is almost totally reflected at the input terminal of the next stage, and the reflected wave reaches the output terminal and is reflected out of phase, and the reflected wave propagates through the signal line. Reach the entry end,
It will be superimposed on the original input signal.

In practice, this multiple reflection is repeated, and at the input end of the next stage, the multiple reflection wave is superimposed at a position shifted by an integral multiple of the round trip propagation delay time of the signal line, resulting in a large signal waveform. It will be distorted.

FIG. 8 is a characteristic diagram showing the distorted signal waveform. FIG. 8 shows an example of a source-coupled FET logic circuit using a high electron mobility transistor (HEMT) integrated on an indium phosphide (InP) substrate. The high electron mobility transistor has a transconductance of 20 mS,
Drain conductance 2ms, current gain cutoff frequency 1
At 90 GHz, the signal wiring is formed in the lowermost wiring layer with a line width of 1.5 μm and a line length of 450 μm.

A pseudo random pulse pattern of 40 Gb / s is used for the input signal, and an eye pattern at the input end of the second logic circuit cell is shown. In this numerical analysis, a circuit simulator HSPICE is used. Also, it can be seen that the eye opening is significantly deteriorated.

As described above, in the prior art, 1) the characteristic impedance of the signal wiring is considerably higher than the output impedance of the circuit, and 2) the propagation speed is low, so that large waveform distortion occurs in a high-speed operation region. Had occurred.

Although the characteristic impedance can be reduced by simply increasing the width of the signal wiring, the width must be increased by a factor of 5 or more in order to reduce the characteristic impedance to several tens of ohms or less. As a result, the area occupied by the wiring portion is increased, which hampers high-density integration of the entire circuit, hinders high-speed operation, and has not been a practical solution.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to realize a high-speed and low-impedance signal wiring in a space equivalent to that of a conventional signal wiring.
An object of the present invention is to provide a wiring structure of a semiconductor integrated circuit that can operate at higher speed without being restricted by wiring parasitic effects.

[0018]

That is, the present invention provides a semiconductor integrated circuit having at least two metal wiring layers on a semiconductor substrate using a dielectric material as an interlayer insulating film and connecting a plurality of logic circuit cells. Wherein the signal output of the first logic circuit cell and the signal input of the second logic circuit cell are connected, and are formed in parallel with the metal wiring layer except for the lowermost layer of the metal wiring layer. A pseudo-microstrip line structure having at least one signal wiring and a ground wiring formed in a metal wiring layer below the signal wiring.

According to the present invention, the ground wiring is formed in the lower wiring layer close to the semiconductor substrate, thereby electrically shielding the high dielectric constant of the semiconductor substrate with respect to the signal line located thereabove, and The effective permittivity of the wiring is reduced to be equal to that of the interlayer insulating film. This increases the propagation speed of the signal line and at the same time reduces the characteristic impedance of the signal line. By the former effect, the upper limit of the frequency at which the signal wiring can be regarded as a lumped constant can be increased, and by the latter effect, the degree of matching between the characteristic impedance of the signal line and the output impedance of the logic circuit connecting it can be improved. it can. Therefore, even in a high-frequency region in which signal wiring must be regarded as a distributed constant, signal waveform distortion due to multiple reflections caused by impedance mismatch is suppressed, and integration capable of higher-speed operation is not restricted by wiring parasitic effects. A circuit can be realized.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a configuration example of a wiring structure of a semiconductor integrated circuit according to a first embodiment of the present invention. In the first embodiment, the case where the signal wiring has a single-line structure is shown as the simplest configuration.

In FIG. 1, a ground wiring 12 having a width L is formed as a first metal wiring layer on the upper surface of a semiconductor substrate 11. And this ground wiring 12
On the upper surface of the semiconductor substrate 11, an interlayer insulating film 13 is formed. Further, a signal wiring 14 having a width W is formed as a second metal wiring layer above the central part of the ground wiring 12 on the interlayer insulating film 13.

As described above, the wiring structure of the semiconductor integrated circuit according to the first embodiment has a structure in which the ground wiring 12 and the signal wiring 14 are stacked. The upper part of the signal wiring 14 is filled with air. And
In this wiring structure, a so-called microstrip line is formed by the ground wiring 12 and the signal wiring 14.

The wiring structure according to the first embodiment is a semiconductor substrate made of InP and having a thickness of 600 μm, a metal wiring layer, a ground wiring 12 and a signal wiring 14, assuming a normal compound semiconductor integrated circuit processing technique. Is formed of gold (Au). The line width W of the signal wiring 14 is 2 μm which is close to the minimum allowable width.
m, and the thickness is 1.5 μm. On the other hand, the ground wiring 12
Is formed in a sufficiently large area as compared with the signal wiring 14, and given as a wiring having a width L parallel to the signal wiring 14 for simplicity, the line width L is 20 μm and the thickness is 0 μm. 0.7 μm.

The interlayer insulating film 13 is made of silicon nitride (S
iN), and the insulating film thickness of the wiring portion, that is, the interlayer distance H is assumed to be 1.5 μm. By electromagnetic field analysis,
The frequency response of the signal wiring 14 and the effective dielectric constant and characteristic impedance felt by the signal wiring 14 can be calculated. In the case of the first embodiment, the effective permittivity is about 4.3, which is smaller than the relative permittivity (6.9) of silicon nitride, and the characteristic impedance is 42Ω.

The signal waveform when such signal wiring 14 is used for actual connection between logic circuit cells will be described in comparison with the case of FIG. 8 introduced in the prior art. FIG. 2 is a diagram showing a configuration example of a signal wiring to which the wiring structure of FIG. 1 is applied, a first logic circuit cell for transmitting a signal, and a second logic circuit cell for receiving a signal.

The conditions such as the configuration of the logic circuit cell to be connected and the transistor performance are the same as those of the above-described conventional example. In other words, a source-coupled FET logic (SCFL) circuit using an HEMT (high electron mobility transistor) integrated on an InP (indium phosphorus) substrate is taken as an example.
HEMT has a transconductance of 20 ms, a drain conductance of 2 ms, and a current gain cutoff frequency of 190 GHz.
z, and the line length of the signal wiring is 450 μm.

In FIG. 2, the signal wiring 14 is connected between a first logic circuit cell 16 and a second logic circuit cell 17. The first logic circuit cell 16 and the second logic circuit cell 16 have the same configuration, and a source follower 19 is cascaded to a differential logic circuit 18.

As described above, the second logic circuit cell 17
Has a very high input impedance of several kΩ, the signal reaching the input end is almost totally reflected. Therefore, what is important in the waveform response is the output impedance Zo of the first logic circuit cell 16 and the signal line 14.
This is the degree of matching of the characteristic impedances. The output impedance Zo of the first logic circuit cell 16 is determined by the transconductance (G
m) and the drain conductance (Gds) are approximately given as follows. Zo = 1 / (Gm + Gds) = 45 (Ω) Therefore, the voltage reflection coefficient at the input end is as small as 0.03.

As in FIG. 8, the circuit simulator HSPL1
Using the CE, the eye pattern at the input end of the second logic circuit cell 17 for a pseudo random pulse pattern of 40 Gb / s was calculated.

FIG. 3 is a characteristic diagram showing the result of the eye pattern. FIG. 3 shows that an extremely good eye opening with almost no multiple reflections is obtained.
In the conventional example shown in FIGS. 7 and 8, the characteristic impedance of the signal line was 180Ω, but the voltage reflection coefficient at the input end was as large as −0.6, and the impedance mismatch caused waveform distortion. You can see that it is bringing. still,
In conventional skin surgery without ground wiring on the bottom wiring layer,
The effective permittivity is as high as about 6.1. The propagation speed of the conventional wiring is 20% lower than that of the signal wiring (effective dielectric constant: 4.3) according to the present embodiment.

When a signal multiplexing circuit in the form of an emitter-coupled logic circuit is designed by using the above transistors, the HSPIC
In the simulation by E, when the wiring structure according to the present invention is used as compared with the wiring structure according to the prior art, 20
% Of the circuit operation speed can be improved. As the speed performance of the transistor improves, the effect of this improvement will further increase. This is because even if the speed of the transistor element is increased, the wiring length required for the connection between circuits hardly changes because the resistance element and the electrode size are not reduced even if the transistor element speeds up. This is because the frequency at which the delay time becomes about 1/4 of the signal wavelength becomes the upper limit of the response band.

Next, a second embodiment of the present invention will be described. FIG. 4 is a sectional view showing a configuration example of a wiring structure of a semiconductor integrated circuit according to a second embodiment of the present invention.

In a high-speed logic circuit, a fully differential configuration using a complementary signal connection is often used for connection between logic circuit cells. The second embodiment shows an application example of the present invention in that case, and shows a case where two signal wirings are formed in parallel with each other.

In FIG. 4, a ground wiring 12 having a width L is formed on a top surface of a semiconductor substrate 11 as a first metal wiring layer. And this ground wiring 12
On the upper surface of the semiconductor substrate 11, an interlayer insulating film 13 is formed. Further, on the interlayer insulating film 13, above the central portion of the ground wiring 12, two second metal wiring layers having a line width W, that is, signal wirings 14 a and 14 b are arranged in parallel at an interval S. Are located.

That is, the semiconductor substrate is made of InP and has a thickness of 600 assuming a normal compound semiconductor integrated circuit processing technique.
μm, the ground wiring 12 and the signal wirings 14a and 14b are formed of gold (Au). Then, the signal wirings 14a, 1
The line width W of 4b is 2 μm, which is close to the minimum allowable width, and the thickness is 1.5.
μm. The line width L of the ground wiring 12 is 10
μm and the thickness is 0.7 μm. Further, the interlayer insulating film 1
Reference numeral 3 is formed of silicon nitride (SiN), and it is assumed that the insulating film thickness of the wiring portion, that is, the interlayer distance H is 1.5 μm.

In the complementary signal wiring as in this example, the interval S is reduced to about the same as the signal wiring width in order to make the signal wiring equal in length and to enhance the effect of removing common-mode noise components. It is usual to arrange them in parallel. Therefore, also in the second embodiment, the distance S between the signal wirings 14a and 14b is set.
Is 2 μm, which is equal to the line width W of each signal wiring 14a, 14b.
It is said.

The signal lines 14a, 14
It is possible to calculate the frequency response of b and the effective permittivity and characteristic impedance felt by the signal wires 14a and 14b. In the case of the second embodiment, the effective permittivity is about 3.4, which is smaller than the relative permittivity (6.9) of silicon nitride, and the characteristic impedance is 33Ω.
Incidentally, the characteristic impedance is lower than that of the first embodiment shown in FIG. 1 because the capacitance component increases due to coupling with the adjacent signal wiring. FIG. 5 shows an example of a circuit configuration including logic circuit cells connected by such wirings.

In FIG. 5, the signal lines 14a and 14b
Are a first logic circuit cell 21 and a second logic circuit cell 22
Connected between The first logic circuit cell 21 and the second logic circuit cell 22 have the same configuration, and the source followers 24 a and 24 b are cascaded to the differential logic circuit 23.

The basic configuration of the logic circuit cells connected to the signal wirings 14a and 14b and the conditions such as transistor performance are the same as those in FIG. In the circuit configuration of FIG. 5, the source followers 24a and 24b are connected to both of the differential output signals, and their outputs are connected to the signal lines 14a and 14b.
Only in that it is connected to the differential input of the second logic circuit cell 22 via the.

That is, the HE integrated on the InP substrate
Source coupling F by MT (high electron mobility transistor)
The ET logic circuit is taken as an example, and the HEMT has a transconductance of 20 ms, a drain conductance of 2 ms,
The current gain cutoff frequency is 190 GHz, and the signal wiring 14
The line lengths of a and 14b are 450 μm.

As described above, the second logic circuit cell 22
Has a very high input impedance of several kilohms, so that the signal reaching the input end is almost totally reflected. Therefore, what is important in the waveform response is the degree of matching between the output impedance Zo of the first logic circuit cell 21 and the characteristic impedance of the signal line S.

As described above, the output impedance Zo of the first logic circuit cell 21 is approximately given by the transconductance (Gm) and the drain conductance (Gds) of the transistor constituting the source follower as follows. Zo = 1 / (Gm + Gds) = 45 (Q) Therefore, the voltage reflection coefficient at the input end is 0.15, and the degree of matching is slightly lower than that of the first embodiment described above. 1/4 of the conventional example (0.6)
It becomes smaller as follows.

In the second embodiment, the characteristic impedance tends to decrease. In such a case, the impedance matching can be further improved. That is, the output impedance of the source follower is almost inversely proportional to Gm of the transistor constituting the source follower, and Gm is proportional to the transistor size. Therefore, if a large transistor is used, the output impedance of the logic circuit cell can be further reduced. it can.

For example, if a transistor 1.5 times larger in size is used, Gm and Gds become 30 ms and 3 ms, respectively.
Thus, the output impedance Zo can be reduced to 30Ω. In this case, the voltage reflection coefficient can be made sufficiently small as 0.05. Therefore, a waveform response characteristic equivalent to that shown in FIG. 3 can be obtained.

As described above, according to the second embodiment,
Due to the effect of the ground wiring formed in the lower metal wiring layer, the characteristic impedance of the signal wiring can be set as low as several tens of ohms. Therefore, the output impedance of the logic circuit cell is almost completely adjusted by adjusting the transistor size of the circuit. It is possible to achieve excellent impedance matching.

In addition, the effective permittivity can be reduced by the shielding effect of the ground wiring formed in the lower metal wiring layer as compared with the prior art, so that the propagation speed can be improved and the signal multiple reflection does not pose a problem. It is possible to improve the upper limit of the frequency at which the wiring can be considered as the lumped constant.

With these effects, it is possible to realize a higher-speed circuit operation. Next, the third of the present invention
An embodiment will be described. The third embodiment shows a case where the interlayer insulating film 12 shown in the first and second embodiments is replaced with a material having a lower relative dielectric constant. Therefore, the wiring structure is the same as in the above-described first and second embodiments, and the description is omitted.

At present, various materials such as polyimide (relative dielectric constant of 3.9 or less) and BCB (relative dielectric constant of 2.8 or less) are used for the interlayer insulating film. At the same time, the effective permittivity of the signal wiring naturally decreases, and the characteristic impedance increases. For example,
Table 1 below shows a comparison between the first embodiment and the second embodiment in the case of BCB (relative permittivity of 2.8 or less).

[0049]

[Table 1]

As a result, if an interlayer insulating film having a relative dielectric constant as low as 2.8 or less is used, the propagation speed can be improved by about 40 to 50%, and signal multiple reflection does not pose a problem. In other words, it is possible to further improve the upper limit of the frequency at which the signal wiring can be considered as the lumped constant.

Although the characteristic impedance in this case increases to the same degree as the propagation speed, it still remains at a low value of 60Ω or less, so that the impedance matching is not greatly impaired, and the output impedance of the logic circuit cell is reduced by the circuit. By adjusting the transistor size, almost perfect impedance matching can be achieved.

Of course, the characteristic impedance can also be reduced by increasing the line width of the wiring. For example, in the case of the above-described first embodiment, the signal line width is set to 4 μm
, The characteristic impedance can be reduced to 44Ω, and the signal line width can be reduced to 34Ω by expanding the signal line width to three times 6 μm. Therefore, it can be said that the effect of the present invention is further increased by introducing a low dielectric material.

Next, a fourth embodiment of the present invention will be described. Here, the effect of the ground line 12 will be described using the ratio of the line width L of the ground line 12 to the line width W of the signal line 14 as a parameter.

The wiring structure of the fourth embodiment is the same as that of the first embodiment, and shows both SiN and BCB as the interlayer insulating film 13. Signal wiring 14
FIG. 6 is a characteristic diagram showing how the characteristic impedance and the propagation speed change with respect to the line width L of the ground wiring 12 when the line width W is fixed to 2 μm.

As shown in FIG. 6, when the line width L of the ground wiring 12 starts to be slightly present, the characteristic impedance starts to decrease sharply. When the width of the signal wiring 14 becomes substantially equal to the line width W, the resistance is reduced to 50Ω which is 30% or less of the initial value when the ground wiring 12 is not present. After this,
45Ω at L = 2W, 43Ω at L = 3W, 4 at L = 10W
It shows a saturation tendency of 2Ω.

This indicates that a small wiring width equivalent to the signal line width as the ground wiring has a sufficient impedance reducing effect. In addition, the propagation speed also increases with an increase in the width of the ground wiring, and in particular, the B
When CB is used as an interlayer insulating film, a remarkable speed improvement can be obtained with a small ground wiring width.

As described above, a sufficient effect can be obtained when the width of the ground wiring is 1 to 10 times the width of the signal line. Therefore, the effect of the present invention can be obtained without requiring extra signal wiring space.

In the first to fourth embodiments, the case where the number of metal wiring layers is two has been described. However, it is needless to say that the present invention can be applied to the case where three or more metal wiring layers are provided. That is, the ground wiring may be formed directly below the signal wiring in the lower metal wiring layer closer to the semiconductor substrate. For example, the same effect can be obtained by forming a ground wiring in the first wiring layer and forming a third metal wiring layer.

[0059]

As described above, according to the present invention, high-speed and low-impedance signal wiring can be realized in the same space as that of the conventional signal wiring, so that higher-speed operation can be performed without being restricted by wiring parasitic effects. A wiring structure of a semiconductor integrated circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration example of a wiring structure of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a signal wiring to which the wiring structure of FIG. 1 is applied, a first logic circuit cell for transmitting a signal, and a second logic circuit cell for receiving a signal;

FIG. 3 is a characteristic diagram showing an example of signal waveform distortion when the wiring structure according to the first embodiment of the present invention is used.

FIG. 4 is a cross-sectional view showing a configuration example of a wiring structure of a semiconductor integrated circuit according to a second embodiment of the present invention.

5 is a diagram illustrating a configuration example of a signal wiring to which the wiring structure of FIG. 4 is applied, a first logic circuit cell for transmitting a signal, and a second logic circuit cell for receiving a signal;

FIG. 6 is a characteristic diagram showing the dependence of the effective relative permittivity and characteristic impedance of a signal wiring on the ground wiring width L in the wiring structure of the semiconductor integrated circuit of FIG. 1;

FIG. 7 is a cross-sectional view showing an example of a wiring structure of a conventional semiconductor integrated circuit.

FIG. 8 is a characteristic diagram showing an example of signal waveform distortion when a conventional wiring structure of a semiconductor integrated circuit is applied.

[Explanation of symbols]

 Reference Signs List 11 semiconductor substrate, 12 ground wiring, 13 interlayer insulating film, 14, 14a, 14b signal wiring, 16, 21 first logic circuit cell, 17, 22 second logic circuit cell, 18, 23 differential logic circuit, 19 , 24a, 24b Source follower.

Claims (3)

[Claims] In a semiconductor integrated circuit having at least two metal wiring layers on a semiconductor substrate using a dielectric material as an interlayer insulating film and connecting a plurality of logic circuit cells, a first logic circuit is provided. Connecting at least one signal wiring formed in parallel with the metal wiring layer except for the lowermost layer of the metal wiring layer, the signal wiring connecting the signal output of the cell and the signal input of the second logic circuit cell; A wiring structure of a semiconductor integrated circuit, comprising a pseudo microstrip line structure having a ground wiring formed in a metal wiring layer below the signal wiring. 2. The wiring structure of a semiconductor integrated circuit according to claim 1, wherein the ground wiring has a wiring width L and is formed in parallel with the signal wiring. A wiring structure of a semiconductor integrated circuit, wherein a ratio (L / W) of a wiring width L of the ground wiring is 1 to 10. 3. The wiring structure of a semiconductor integrated circuit according to claim 1, wherein said signal wiring is composed of two signal wirings arranged at a predetermined interval and parallel to each other. Wiring structure of semiconductor integrated circuit.