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JPH118457A - Manufacturing method of thin film circuit board - Google Patents

Manufacturing method of thin film circuit board

Info

Publication number
JPH118457A
JPH118457A JP9158934A JP15893497A JPH118457A JP H118457 A JPH118457 A JP H118457A JP 9158934 A JP9158934 A JP 9158934A JP 15893497 A JP15893497 A JP 15893497A JP H118457 A JPH118457 A JP H118457A
Authority
JP
Japan
Prior art keywords
thin film
film circuit
external electrode
forming
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9158934A
Other languages
Japanese (ja)
Other versions
JP3686219B2 (en
Inventor
Takeo Nakajima
建夫 中島
Shigeki Hatanaka
茂樹 畠中
Masato Hirano
正人 平野
Kazuo Arisue
一夫 有末
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15893497A priority Critical patent/JP3686219B2/en
Publication of JPH118457A publication Critical patent/JPH118457A/en
Application granted granted Critical
Publication of JP3686219B2 publication Critical patent/JP3686219B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

(57)【要約】 【課題】 基板上にエッチングにより形成された外部電
極に接続して薄膜回路を形成する際に接続界面に形成す
る薄膜に亀裂や破断が生じにくくする。 【解決手段】 外部電極4a、4bをエッチングにより
形成するマスクパターンの接続界面位置に凹部9を列設
形成することにより、凹部9の内方に向かうほどエッチ
ングの進行速度に遅れが生じるため、外部電極4a、4
bの部分以外が除去されたときにも凹部9内は傾斜面と
なって残される。従って、接続界面に形成された複数の
傾斜面を利用して薄膜を形成すると、大きな段差がない
ため形成される薄膜に括れが生じず、それに起因する亀
裂や破断のない薄膜回路形成を行うことができる。
(57) Abstract: A thin film formed at a connection interface when connected to an external electrode formed on a substrate by etching to form a thin film circuit is less likely to crack or break. SOLUTION: By forming a row of concave portions 9 at connection interface positions of a mask pattern for forming external electrodes 4a and 4b by etching, the etching progresses more inward toward the concave portions 9; Electrodes 4a, 4
Even when the portion other than the portion b is removed, the inside of the concave portion 9 remains as an inclined surface. Therefore, when a thin film is formed using a plurality of inclined surfaces formed at the connection interface, there is no large step, so that the formed thin film is not constricted, and a thin film circuit without cracks or breakage caused by the thin film is formed. Can be.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、エッチングにより
外部電極が形成された基板上に外部電極に接続して薄膜
形成により薄膜回路を形成する薄膜回路基板の製造方法
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film circuit board for forming a thin film circuit by forming a thin film by connecting the external electrodes on a substrate having external electrodes formed by etching.

【0002】[0002]

【従来の技術】図6は、薄膜回路形成により基板上に電
子部品を形成した従来例を示すもので、同図(a)は、
外部接続のための第1、第2の各外部電極21a、21
bをエッチングにより形成した基板20上に、第1の外
部電極21aと第2の外部電極21bとの間を接続して
電子部品22を薄膜形成により形成した状態を示してお
り、薄膜形成による電子部品22はシート状のキャパシ
タとして形成されている。
2. Description of the Related Art FIG. 6 shows a conventional example in which an electronic component is formed on a substrate by forming a thin film circuit.
First and second external electrodes 21a, 21 for external connection
This shows a state in which the first external electrode 21a and the second external electrode 21b are connected to each other and the electronic component 22 is formed on the substrate 20 formed by etching the thin film to form the electronic component 22. The component 22 is formed as a sheet-like capacitor.

【0003】この電子部品22を形成するための薄膜形
成の方法は、同図(b)にB−B線矢視断面として示す
ように、蒸着またはスパッタリングにより第1の外部電
極21aに一部が重なるように第1の内部電極23aを
形成し、この第1の内部電極23aの上に誘電体材料2
4を形成する。次いで、誘電体材料24と第2の外部電
極21bとを接続するように第2の内部電極23bを形
成する。
A method of forming a thin film for forming the electronic component 22 is such that a part of the first external electrode 21a is formed on the first external electrode 21a by vapor deposition or sputtering, as shown in FIG. A first internal electrode 23a is formed so as to overlap, and a dielectric material 2 is formed on the first internal electrode 23a.
4 is formed. Next, a second internal electrode 23b is formed so as to connect the dielectric material 24 and the second external electrode 21b.

【0004】上記薄膜形成の手順により、第1の外部電
極21aと第2の外部電極21bとの間をつなぐ第1内
部電極23aと第2の内部電極23bとの間に誘電体材
料24を挟んだ電子部品(キャパシタ)22を形成する
ことができる。
[0004] By the above-described thin film forming procedure, the dielectric material 24 is sandwiched between the first internal electrode 23a and the second internal electrode 23b connecting the first external electrode 21a and the second external electrode 21b. The electronic component (capacitor) 22 can be formed.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、薄膜形
成により形成される第1、第2の各内部電極23a、2
3bの膜厚は約0.1μmt、エッチングにより形成さ
れた第1、第2の各外部電極21a、21bの膜厚は約
10μmtで、その膜厚比は約1:100になるため、
各内部電極23a、23bそれぞれの各外部電極21
a、21bとの接続界面には図示する以上に大きな段差
があり、その垂直面での薄膜形成厚が小さくなることか
らくびれが生じやすく、それに起因する亀裂や破断によ
る不良発生率が多くなる問題点があった。
However, the first and second internal electrodes 23a, 2a, 2a, 2b, 2a, 2b, 2a, 2b, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2a, 2b, 2c, which are formed by forming a thin film.
3b has a thickness of about 0.1 μmt, and the first and second external electrodes 21a and 21b formed by etching have a thickness of about 10 μmt and a thickness ratio of about 1: 100.
Each external electrode 21 of each internal electrode 23a, 23b
At the connection interface with a and 21b, there is a step larger than that shown in the figure, and the thin film formation thickness on the vertical surface is small, so that constriction is apt to occur, and the defect generation rate due to cracks and breakage increases. There was a point.

【0006】本発明の目的とするところは、膜厚差の大
きな接続界面に接続不良を生じさせることなく薄膜形成
を行うことができる薄膜回路基板の製造方法を提供する
ことにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a thin film circuit board capable of forming a thin film without causing a connection failure at a connection interface having a large thickness difference.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
の本願の第1発明は、エッチングにより外部電極が形成
された基板上に前記外部電極に接続して薄膜回路を形成
する薄膜回路基板の製造方法において、前記基板上に外
部電極を所定形状にエッチング処理するマスクパターン
を、その前記薄膜回路との接続界面となる位置に、端辺
から内方に向かう複数の凹部を有するように形成した
後、エッチング処理し、形成された外部電極に接続して
薄膜回路を形成することを特徴とする。
According to a first aspect of the present invention, there is provided a thin film circuit board for forming a thin film circuit by connecting to an external electrode on a substrate on which an external electrode is formed by etching. In the manufacturing method, a mask pattern for etching an external electrode into a predetermined shape on the substrate is formed at a position serving as a connection interface with the thin-film circuit so as to have a plurality of concave portions inward from an edge. Thereafter, the thin film circuit is formed by performing an etching process and connecting to the formed external electrode.

【0008】上記製造方法によれば、基板上に外部電極
をエッチング処理により形成するためのマスクパターン
の端辺に内方に向かう小面積の凹部を形成してエッチン
グ処理を行うと、大きな面積部分がエッチングされる進
行速度と、小さな面積部分がエッチングされる進行速度
とに速度差が生じて、大きな面積部分の腐食が完了した
ときにも凹部内は内方に向かうほど腐食が遅れ、その結
果、端辺から凹部内に向かう傾斜面が形成されることに
なる。このようにして薄膜回路接続側の端辺に傾斜面が
形成された外部電極上に薄膜を形成すると、外部電極の
接続界面となる端辺に大きな段差を作ることなく外部電
極上に薄膜が形成され、接続界面に亀裂や破断を生じさ
せることがなく、信頼性の高い薄膜回路を形成すること
ができる。
According to the above-described manufacturing method, when an inward small area concave portion is formed at an edge of a mask pattern for forming an external electrode on a substrate by etching, and etching is performed, a large area portion is formed. There is a speed difference between the progress rate at which a small area is etched and the progress rate at which a small area is etched, and even when the corrosion of a large area is completed, the corrosion is delayed inward in the concave part as a result. Thus, an inclined surface extending from the end side toward the inside of the concave portion is formed. When a thin film is formed on an external electrode having an inclined surface formed on the edge on the thin film circuit connection side in this manner, the thin film is formed on the external electrode without forming a large step at the edge serving as a connection interface of the external electrode. Thus, a highly reliable thin film circuit can be formed without causing cracks or breaks at the connection interface.

【0009】上記凹部は、複数の凹部を列設して外部電
極の接続界面の形状を鋸歯状もしくは櫛歯状に形成する
ことにより、薄膜回路接続側の端辺に複数の傾斜面が形
成され、接続界面の接続安定性を高めることができる。
In the recess, a plurality of recesses are arranged in a row, and the connection interface of the external electrodes is formed in a saw-tooth shape or a comb-tooth shape. In addition, the connection stability of the connection interface can be improved.

【0010】また、凹部の形状を曲線で形成することに
より、傾斜面と外部電極表面との境界面をより滑らかに
形成することができ、薄膜形成による接続が安定してな
される。
Further, by forming the shape of the concave portion with a curved line, the boundary surface between the inclined surface and the surface of the external electrode can be formed more smoothly, and the connection by forming a thin film can be stably performed.

【0011】更に、本願の第2発明は、外部電極が形成
された基板上に前記外部電極に接続する薄膜回路を形成
する薄膜回路基板の製造方法において、前記外部電極の
薄膜回路が接続形成される接続界面に、基板表面から外
部電極表面に至る傾斜面を形成する傾斜面形成材を施し
た後、前記薄膜回路形成の処理を実施することを特徴と
する。
Further, a second invention of the present application relates to a method of manufacturing a thin film circuit board for forming a thin film circuit connected to the external electrode on a substrate on which the external electrode is formed, wherein the thin film circuit of the external electrode is connected and formed. A method of forming a thin film circuit is performed after a slope forming material for forming a slope from the substrate surface to the external electrode surface is applied to the connection interface.

【0012】第2発明に係る製造方法では、外部電極の
薄膜回路接続側に、外部電極端部に傾斜面を形成する傾
斜面形成材を施した後に薄膜形成を行うので、傾斜面形
成材により外部電極と薄膜との厚さ比による段差が傾斜
面でなだらかになり、その傾斜面上に形成した薄膜に亀
裂や破断が生じにくくなり、信頼性の高い薄膜回路を形
成することができる。
In the manufacturing method according to the second aspect of the present invention, the thin film is formed after the slope forming material for forming the slope at the end of the external electrode is formed on the thin film circuit connecting side of the external electrode. The step due to the thickness ratio between the external electrode and the thin film becomes gentle on the inclined surface, and the thin film formed on the inclined surface is less likely to crack or break, and a highly reliable thin film circuit can be formed.

【0013】[0013]

【発明の実施の形態】以下、添付図面を参照して本発明
の一実施形態について説明し、本発明の理解に供する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings to provide an understanding of the present invention.

【0014】図1(a)は、本発明の第1の実施形態に
係る薄膜回路基板の製造方法により基板5上にキャパシ
タを形成した状態を示す平面図である。図示するように
基板5上にエッチングにより形成された第1の外部電極
4aと第2の外部電極4bとの間に、蒸着、スパッタリ
ング等により第1の内部電極3a、第2の内部電極3b
及び誘電体材料6を形成することにより、第1の外部電
極4aと第2の外部電極4bとの間にキャパシタ1が形
成される。
FIG. 1A is a plan view showing a state in which a capacitor is formed on a substrate 5 by the method for manufacturing a thin film circuit board according to the first embodiment of the present invention. As shown in the figure, a first internal electrode 3a and a second internal electrode 3b are formed between a first external electrode 4a and a second external electrode 4b formed on a substrate 5 by etching or the like.
By forming the dielectric material 6, the capacitor 1 is formed between the first external electrode 4a and the second external electrode 4b.

【0015】図1(b)に示す断面図は、図1(a)の
A−A線矢視断面で、第1、第2の各外部電極4a、4
bそれぞれの第1、第2の各内部電極3a、3bとの接
続界面は傾斜面に形成されているため、第1、第2の各
内部電極3a、3bを薄膜形成するときに接続界面にく
びれが生じないため、それに起因する亀裂や破断が生じ
ず、信頼性の高い接続構造に形成することができる。
FIG. 1B is a cross-sectional view taken along line AA of FIG. 1A, and shows first and second external electrodes 4a, 4a.
b Since the connection interface with each of the first and second internal electrodes 3a and 3b is formed on an inclined surface, the connection interface is formed when the first and second internal electrodes 3a and 3b are formed as a thin film. Since constriction does not occur, a crack or breakage due to the constriction does not occur, and a highly reliable connection structure can be formed.

【0016】前記第1、第2の各外部電極4a、4bの
接続界面に傾斜面を形成する方法について、図2〜4を
参照して説明する。
A method for forming an inclined surface at the connection interface between the first and second external electrodes 4a and 4b will be described with reference to FIGS.

【0017】第1、第2の各外部電極4a、4bの形成
は、第1、第2の各外部電極4a、4bを形成するため
の材料膜(銅箔等)が貼着された基板材料8をエッチン
グ処理することにより形成される。図2(a)に示すよ
うに、第1、第2の各外部電極4a、4bそれぞれを形
成するための各マスクパターン7a、7bは、第1、第
2の各内部電極3a、3bとの接続界面側に複数の凹部
9を鋸歯状に設けたパターンに塗布される。このような
マスクパターン7a、7bが施された基板材料8をエッ
チング処理すると、エッチングの進行速度は凹部9の小
さな面積部分が遅くなるため、凹部9を除く他の部分の
エッチングが完了したときにも、凹部9の内方側に向か
うほどエッチングに遅れが生じて、結果的には図2
(b)に示すように、凹部9内にエッチングしきれなか
った面がエッチング速度に対応する傾斜面として残るこ
とになる。従って、基板材料8からエッチング処理によ
り第1、第2の各外部電極4a、4bとして残す部分以
外をエッチングにより除去すると、接続界面側の端辺に
複数に形成した凹部9の位置にそれぞれ傾斜面が形成さ
れ、図2(c)の断面図に示すような傾斜面が接続界面
側に複数に形成された第1、第2の各外部電極4a、4
bが基板5上に形成される。
The first and second external electrodes 4a and 4b are formed by a substrate material on which a material film (copper foil or the like) for forming the first and second external electrodes 4a and 4b is adhered. 8 is formed by etching. As shown in FIG. 2A, each of the mask patterns 7a and 7b for forming the first and second external electrodes 4a and 4b is formed with the first and second internal electrodes 3a and 3b. It is applied in a pattern in which a plurality of concave portions 9 are provided in a sawtooth shape on the connection interface side. When the substrate material 8 provided with such mask patterns 7a and 7b is subjected to etching, the etching proceeds at a small area of the concave portion 9 at a low speed. Also, the etching is delayed more toward the inner side of the concave portion 9, and as a result, as shown in FIG.
As shown in (b), the surface that has not been completely etched in the recess 9 remains as an inclined surface corresponding to the etching rate. Therefore, when the portions other than the portions left as the first and second external electrodes 4a and 4b are removed by etching from the substrate material 8 by etching, the inclined surfaces are respectively formed at the positions of the plurality of concave portions 9 formed at the end sides on the connection interface side. Are formed, and the first and second external electrodes 4a, 4a and 4b are formed on the connection interface side with a plurality of inclined surfaces as shown in the cross-sectional view of FIG.
b is formed on the substrate 5.

【0018】このように第1、第2の各外部電極4a、
4bが形成された基板5上に、図1(b)に示すよう
に、第1、第2の各外部電極4a、4bに接続して第
1、第2の各内部電極3a、3bを薄膜形成すると、各
外部電極4a、4bとの接続界面は傾斜面で接続される
ので、厚さ比による大きな段差がなくなるため形成され
る薄膜にくびれが生じず、亀裂や破断のない薄膜形成を
行うことができる。
As described above, the first and second external electrodes 4a,
As shown in FIG. 1B, the first and second internal electrodes 3a and 3b are connected to the first and second external electrodes 4a and 4b on the substrate 5 on which the 4b is formed. When formed, the connection interface with each of the external electrodes 4a and 4b is connected by an inclined surface, so that there is no large step due to the thickness ratio, so that the formed thin film does not become constricted, and a thin film without cracks or breakage is formed. be able to.

【0019】上記各マスクパターン7a、7bによる凹
部9の形成は、図3に示すように矩形の凹部9aを列設
した櫛歯状に形成したマスクパターン7c、7dでマス
キングしてエッチング処理することもでき、この場合に
も凹部9aの内方ほどエッチングの進行速度が遅くなる
ため、凹部9a内に傾斜面が形成され、これが列設され
ているので、複数の傾斜面を接続界面として利用するこ
とができる。また、図4(a)(b)に示すように、凹
部9b、9cの角部を曲線に形成したマスクパターン7
e、7fを用いてエッチング処理することにより、接続
界面の角や傾斜面を滑らかに形成することができ、接続
界面を角部の少ない形状に形成でき、各内部電極3a、
3bとの接続をより安定させることができる。
The recesses 9 are formed by the mask patterns 7a and 7b by masking and etching using comb-shaped mask patterns 7c and 7d in which rectangular recesses 9a are arranged in a row as shown in FIG. Also in this case, since the etching proceeds at a lower rate toward the inner side of the concave portion 9a, an inclined surface is formed in the concave portion 9a, and a plurality of the inclined surfaces are used as connection interfaces. be able to. Further, as shown in FIGS. 4A and 4B, a mask pattern 7 in which the corners of the concave portions 9b and 9c are formed in a curved line.
By performing etching using e and 7f, the corners and inclined surfaces of the connection interface can be formed smoothly, and the connection interface can be formed in a shape with less corners.
The connection with 3b can be further stabilized.

【0020】次に、本発明の第2の実施形態に係る薄膜
回路の製造方法について説明する。
Next, a method of manufacturing a thin film circuit according to a second embodiment of the present invention will be described.

【0021】図5は、本実施形態の薄膜回路基板の製造
方法により基板15上にキャパシタ2を形成した状態を
示す断面図である。
FIG. 5 is a cross-sectional view showing a state in which the capacitor 2 is formed on the substrate 15 by the method of manufacturing a thin film circuit board according to the present embodiment.

【0022】この薄膜形成によるキャパシタ2の製造手
順は、まず、第1、第2の各外部電極10a、10bが
形成された基板15に対し、各外部電極10a、10b
それぞれの接続界面位置にポリイミド等の樹脂による傾
斜面形成材11a、11bを塗布することにより、その
表面張力により図示するように傾斜面が形成される。
The procedure for manufacturing the capacitor 2 by forming a thin film is as follows. First, the external electrodes 10a, 10b are formed on the substrate 15 on which the first and second external electrodes 10a, 10b are formed.
By applying the inclined surface forming materials 11a and 11b made of a resin such as polyimide to the respective connection interface positions, the inclined surfaces are formed by the surface tension as shown in the figure.

【0023】次に、第1の外部電極10aから傾斜面形
成材11a、基板15にわたって第1の内部電極12a
をスパッタリング、蒸着等の薄膜形成手段により形成す
る。この内部電極12aの基板15上の位置に誘電体材
料13を薄膜形成し、この誘電体材料13から基板1
5、傾斜面形成材11b、第2の外部電極10bにいた
る表面に第2の内部電極12bを薄膜形成する。この薄
膜形成により、第1内部電極12aと第2の内部電極1
2bとの間に誘電体材料13を挟んでキャパシタ2が形
成され、各内部電極12a、12bがそれぞれ各外部電
極10a、10bに接続されることにより、基板15上
に薄膜形成によりキャパシタ2を形成することができ
る。
Next, the first internal electrode 12a extends from the first external electrode 10a to the inclined surface forming material 11a and the substrate 15.
Is formed by a thin film forming means such as sputtering or vapor deposition. A dielectric material 13 is formed in a thin film at a position on the substrate 15 of the internal electrode 12a.
5. A thin film of the second internal electrode 12b is formed on the surface up to the inclined surface forming material 11b and the second external electrode 10b. By forming this thin film, the first internal electrode 12a and the second internal electrode 1
The capacitor 2 is formed with the dielectric material 13 interposed therebetween and the internal electrodes 12a and 12b are connected to the external electrodes 10a and 10b, respectively, whereby the capacitor 2 is formed on the substrate 15 by forming a thin film. can do.

【0024】上記構成によっても、第1、第2の各内部
電極12a、12bと第1、第2の各外部電極10a、
10bとのそれぞれの接続界面は各傾斜面形成材11
a、11bにより傾斜面が形成されているので、厚さ比
による急激な段差がなくなり、薄膜形成の括れが生じに
くいので、それに起因する亀裂や破断のない薄膜形成を
行うことができる。
According to the above configuration, the first and second internal electrodes 12a and 12b and the first and second external electrodes 10a and
10b is connected to each inclined surface forming material 11
Since the inclined surfaces are formed by a and 11b, a sharp step due to the thickness ratio is eliminated, and the formation of the thin film is less likely to be clogged.

【0025】以上説明した各実施形態では、薄膜形成に
より基板上にキャパシタ回路を形成する方法について説
明したが、半田付けにより外部接続するための外部電極
が形成されている基板上に薄膜回路を形成するような場
合に同様の方法を用いて薄膜回路基板を製造することが
できる。
In each of the embodiments described above, a method of forming a capacitor circuit on a substrate by forming a thin film has been described. However, a thin film circuit is formed on a substrate on which external electrodes for external connection are formed by soldering. In such a case, a thin film circuit board can be manufactured using the same method.

【0026】[0026]

【発明の効果】以上の説明の通り本願の第1発明によれ
ば、基板上に形成された外部電極の薄膜回路接続の接続
界面に傾斜面が形成されているので、外部電極の接続界
面に大きな段差を作ることなく外部電極に接続して薄膜
回路が形成できるため、形成される薄膜に亀裂や破断を
生じさせることがなく、信頼性の高い薄膜回路を形成す
ることができる。
As described above, according to the first aspect of the present invention, since the inclined surface is formed at the connection interface of the thin film circuit of the external electrode formed on the substrate, the inclined surface is formed at the connection interface of the external electrode. Since a thin film circuit can be formed by connecting to an external electrode without forming a large step, a highly reliable thin film circuit can be formed without causing a crack or break in a formed thin film.

【0027】また、本願の第2発明によれば、基板上に
形成された外部電極の薄膜回路接続の接続界面に傾斜面
形成材により傾斜面を形成した後に薄膜形成を行うの
で、傾斜面形成材により外部電極と薄膜との厚さ比によ
る段差が傾斜面でなだらかになり、その傾斜面上に形成
した薄膜に亀裂や破断が生じにくくなり、信頼性の高い
薄膜回路を形成することができる。
According to the second aspect of the present invention, the thin film is formed after the inclined surface is formed by the inclined surface forming material on the connection interface of the thin film circuit connection of the external electrode formed on the substrate. Due to the material, the step due to the thickness ratio between the external electrode and the thin film becomes gentle on the inclined surface, the thin film formed on the inclined surface is less likely to crack or break, and a highly reliable thin film circuit can be formed .

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施形態に係る製造方法により
製造された薄膜回路の例(a)とそのA−A線矢視断面
の薄膜形成状態(b)を示す断面図。
FIG. 1 is a cross-sectional view showing an example (a) of a thin-film circuit manufactured by a manufacturing method according to a first embodiment of the present invention and a thin-film formation state (b) of a cross section taken along line AA of FIG.

【図2】外部電極をエッチング処理するマスクパターン
(a)の例とエッチング処理後の凹部形状(b)の斜視
図と断面状態(c)を示す断面図。
2A and 2B are a perspective view and a cross-sectional view illustrating an example of a mask pattern (a) for etching an external electrode and a concave shape (b) after the etching process.

【図3】接続界面に傾斜面を形成する別マスクパターン
(a)を示す平面図と形成された凹部形状(b)を示す
斜視図。
FIG. 3 is a plan view showing another mask pattern (a) forming an inclined surface at a connection interface, and a perspective view showing a formed concave shape (b).

【図4】接続界面に傾斜面を形成する別マスクパターン
例(a)(b)を示す平面図。
FIG. 4 is a plan view showing another mask pattern example (a) and (b) for forming an inclined surface at a connection interface.

【図5】本発明の第2の実施形態に係る製造方法により
製造された薄膜回路の形成状態を示す断面図。
FIG. 5 is a sectional view showing a state of forming a thin film circuit manufactured by a manufacturing method according to a second embodiment of the present invention.

【図6】従来の製造方法により形成された薄膜回路を示
す平面図(a)とその断面(b)を示す断面図。
6A is a plan view showing a thin film circuit formed by a conventional manufacturing method, and FIG. 6B is a cross-sectional view showing a cross section thereof.

【符号の説明】[Explanation of symbols]

1、2 キャパシタ(薄膜回路) 3a、3b、12a、12b 内部電極 4a、4b、10a、10b 外部電極 5、15 基板 7a、7b、7c、7d、7e、7f マスクパターン 9、9a、9b、9c 凹部 11a、11b 傾斜面形成材 1, 2 Capacitor (thin film circuit) 3a, 3b, 12a, 12b Internal electrode 4a, 4b, 10a, 10b External electrode 5, 15 Substrate 7a, 7b, 7c, 7d, 7e, 7f Mask pattern 9, 9a, 9b, 9c Recesses 11a, 11b Inclined surface forming material

───────────────────────────────────────────────────── フロントページの続き (72)発明者 有末 一夫 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuo Arisue 1006 Kazuma Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 エッチングにより外部電極が形成された
基板上に前記外部電極に接続して薄膜回路を形成する薄
膜回路基板の製造方法において、 前記基板上に外部電極を所定形状にエッチング処理する
マスクパターンを、その前記薄膜回路との接続界面とな
る位置に、端辺から内方に向かう複数の凹部を有するよ
うに形成した後、エッチング処理し、形成された外部電
極に接続して薄膜回路を形成することを特徴とする薄膜
回路基板の製造方法。
1. A method of manufacturing a thin-film circuit board, wherein a thin-film circuit is formed by connecting to an external electrode on a substrate on which an external electrode is formed by etching, wherein a mask for etching the external electrode into a predetermined shape on the substrate is provided. A pattern is formed at a position serving as a connection interface with the thin film circuit so as to have a plurality of concave portions directed inward from an edge, and then subjected to an etching process and connected to the formed external electrodes to form a thin film circuit. A method for manufacturing a thin film circuit board, comprising:
【請求項2】 複数の凹部の列設により外部電極の接続
界面の形状を鋸歯状もしくは櫛歯状に形成した請求項1
記載の薄膜回路基板の製造方法。
2. The connection interface between external electrodes is formed in a saw-tooth shape or a comb-tooth shape by arranging a plurality of recesses.
A method for manufacturing the thin film circuit board according to the above.
【請求項3】 凹部の形状を曲線で形成した請求項1ま
たは2記載の薄膜回路基板の製造方法。
3. The method for manufacturing a thin film circuit board according to claim 1, wherein the shape of the concave portion is formed by a curve.
【請求項4】 外部電極が形成された基板上に前記外部
電極に接続する薄膜回路を形成する薄膜回路基板の製造
方法において、 前記外部電極の薄膜回路が接続形成される接続界面に、
基板表面から外部電極表面に至る傾斜面を形成する傾斜
面形成材を施した後、前記薄膜回路を形成することを特
徴とする薄膜回路基板の製造方法。
4. A method for manufacturing a thin-film circuit board, wherein a thin-film circuit connected to the external electrode is formed on a substrate on which an external electrode is formed.
A method for manufacturing a thin film circuit board, comprising: forming a thin film circuit after applying a slope forming material for forming a slope from a substrate surface to an external electrode surface.
JP15893497A 1997-06-16 1997-06-16 Thin film circuit board manufacturing method Expired - Fee Related JP3686219B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15893497A JP3686219B2 (en) 1997-06-16 1997-06-16 Thin film circuit board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15893497A JP3686219B2 (en) 1997-06-16 1997-06-16 Thin film circuit board manufacturing method

Publications (2)

Publication Number Publication Date
JPH118457A true JPH118457A (en) 1999-01-12
JP3686219B2 JP3686219B2 (en) 2005-08-24

Family

ID=15682541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15893497A Expired - Fee Related JP3686219B2 (en) 1997-06-16 1997-06-16 Thin film circuit board manufacturing method

Country Status (1)

Country Link
JP (1) JP3686219B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7084512B2 (en) 2001-11-21 2006-08-01 Matsushita Electric Industrial Co., Ltd. Circuit substrate and its manufacturing method
JP2006324238A (en) * 2005-04-26 2006-11-30 Osram Opto Semiconductors Gmbh Laser process for high reliability and low resistance electrical contact
WO2014162451A1 (en) * 2013-04-01 2014-10-09 パイオニア株式会社 Joined structure and light-emitting device
JP2014203525A (en) * 2013-04-01 2014-10-27 パイオニア株式会社 Joining structure and light-emitting device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7084512B2 (en) 2001-11-21 2006-08-01 Matsushita Electric Industrial Co., Ltd. Circuit substrate and its manufacturing method
JP2006324238A (en) * 2005-04-26 2006-11-30 Osram Opto Semiconductors Gmbh Laser process for high reliability and low resistance electrical contact
WO2014162451A1 (en) * 2013-04-01 2014-10-09 パイオニア株式会社 Joined structure and light-emitting device
JP2014203525A (en) * 2013-04-01 2014-10-27 パイオニア株式会社 Joining structure and light-emitting device

Also Published As

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