JPH118234A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH118234A JPH118234A JP9159589A JP15958997A JPH118234A JP H118234 A JPH118234 A JP H118234A JP 9159589 A JP9159589 A JP 9159589A JP 15958997 A JP15958997 A JP 15958997A JP H118234 A JPH118234 A JP H118234A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- semiconductor substrate
- silicon
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
(57)【要約】
【課題】 半導体基板との界面や絶縁膜中の水素の量を
減らして、特性の劣化を生じない信頼性の高い半導体装
置を提供する。
【解決手段】 回路素子が形成される半導体基板1と、
該半導体基板上に設けられる絶縁膜と、該絶縁膜上に設
けられるメタル配線9と、メタル配線上に設けられる保
護用の絶縁膜とを有する半導体装置であって、前記半導
体基板上に設けられる絶縁膜が少なくとも3層の絶縁膜
を有し、前記半導体基板に近い側の第1層の絶縁膜6が
水素濃度が1at%以下のシリコン酸化物からなり、第
2層の絶縁膜7がシリコン過剰のシリコン酸化膜、シリ
コンチッ化膜またはシリコン酸化チッ化膜からなり、第
3層の絶縁膜8がシリコン濃度が50at%未満のシリ
コンチッ化膜からなっている。
(57) [Problem] To provide a highly reliable semiconductor device in which characteristics are not deteriorated by reducing the amount of hydrogen in an interface with a semiconductor substrate and in an insulating film. SOLUTION: A semiconductor substrate 1 on which a circuit element is formed,
A semiconductor device comprising: an insulating film provided on the semiconductor substrate; a metal wiring 9 provided on the insulating film; and a protective insulating film provided on the metal wiring, provided on the semiconductor substrate. The insulating film has at least three insulating films, the first insulating film 6 near the semiconductor substrate is made of silicon oxide having a hydrogen concentration of 1 at% or less, and the second insulating film 7 is made of silicon. The third insulating film 8 is made of an excessive silicon oxide film, a silicon nitride film or a silicon oxide nitride film, and the silicon nitride film having a silicon concentration of less than 50 at%.
Description
【0001】[0001]
【発明の属する技術分野】本発明は集積回路が形成され
る半導体装置に関する。さらに詳しくは、シリコン界面
や絶縁膜中のトラップ準位の発生を防止し、高電界の印
加に対しても素子特性の劣化を生じない半導体装置に関
する。[0001] The present invention relates to a semiconductor device on which an integrated circuit is formed. More specifically, the present invention relates to a semiconductor device which prevents generation of trap levels in a silicon interface or an insulating film and does not cause deterioration of element characteristics even when a high electric field is applied.
【0002】[0002]
【従来の技術】従来の集積回路が形成された半導体装置
は、たとえば1個のMOSFET部分が図4に示される
ように、たとえばp形の半導体基板1の表面に素子分離
用の熱酸化膜2が形成され、その間の半導体基板1の表
面に薄いゲート酸化膜3およびポリシリコンからなるゲ
ート電極4が形成され、ゲート電極4の両側の半導体基
板1にソース、ドレインのn+ 形拡散領域5a、5bが
形成されることによりMOSFETが形成され、半導体
基板1およびゲート電極4の上にシリコン酸化物(以
下、SiOという)などからなる層間絶縁膜11が設け
られ、その上にメタル配線9が設けられ、図示しないコ
ンタクトホールを介してゲート電極4などと接続されて
いる。さらにその上にシリコンチッ化物(以下、SiN
という)などからなる保護用の絶縁膜12が設けられて
いる。2. Description of the Related Art In a conventional semiconductor device on which an integrated circuit is formed, a thermal oxide film 2 for element isolation is formed on a surface of, for example, a p-type semiconductor substrate 1 as shown in FIG. Are formed, a thin gate oxide film 3 and a gate electrode 4 made of polysilicon are formed on the surface of the semiconductor substrate 1 therebetween, and n + type diffusion regions 5a of source and drain are formed on the semiconductor substrate 1 on both sides of the gate electrode 4. By forming 5b, a MOSFET is formed, an interlayer insulating film 11 made of silicon oxide (hereinafter, referred to as SiO) is provided on semiconductor substrate 1 and gate electrode 4, and metal wiring 9 is provided thereon. And is connected to the gate electrode 4 and the like via a contact hole (not shown). Further, a silicon nitride (hereinafter referred to as SiN)
) Is provided.
【0003】層間絶縁膜や保護用の絶縁膜などの絶縁膜
は、プラズマCVD法などのCVD法により設けられ、
代表的にはポリシリコン上の層間膜にはSiO(SiO
にリンがドープされたホスホシリケートガラス(PS
G)やSiOにボロンとリンがドープされたボロンホス
ホシリケートガラス(BPSG)を含む)などが用いら
れ、メタル配線が複数層に設けられる場合、その間の層
間絶縁膜にはSiOやSiNなどが用いられている。An insulating film such as an interlayer insulating film or a protective insulating film is provided by a CVD method such as a plasma CVD method.
Typically, the interlayer film on polysilicon is made of SiO (SiO
Phosphosilicate glass (PS) doped with phosphorus
G) or boron phosphosilicate glass (BPSG) in which boron and phosphorus are doped into SiO), and when metal wiring is provided in a plurality of layers, SiO or SiN is used as an interlayer insulating film between them. Have been.
【0004】[0004]
【発明が解決しようとする課題】前述のCVD法により
成膜される絶縁膜には水素(H)が含まれており、図4
に波線で示されるように、このHが半導体基板1側に進
み、高電界により発生するホットキャリアと相互に影響
し、シリコン(Si)界面や、各絶縁膜中にトラップ準
位(図4のA参照)やトラップ電荷(図4のB参照)を
発生させる。とくに、プラズマCVD法により成膜され
るSiN膜は通常水素濃度が20at%程度あり、熱C
VD法によるSiOより1桁ほど多く、最大の水素供給
源となっている。しかし、前述の半導体装置の製造にお
いては、メタル配線のAlなどが熱に弱いこともあり、
プラズマCVD法によるSiN膜が層間絶縁膜として用
いられている。そのため、素子が形成されて高電圧が印
加される半導体基板1に近い方でトラップ準位やトラッ
プ電荷が発生しやすい。これらの準位や電荷により素子
特性が経時劣化を起すという問題がある。The insulating film formed by the above-mentioned CVD method contains hydrogen (H).
As shown by the dashed line in FIG. 4, this H advances to the semiconductor substrate 1 side and interacts with hot carriers generated by a high electric field, and trap levels appear at the silicon (Si) interface and in each insulating film (FIG. 4). A) and trap charges (see FIG. 4B). In particular, a SiN film formed by a plasma CVD method usually has a hydrogen concentration of about 20 at%,
It is about one digit larger than SiO by the VD method, and is the largest hydrogen supply source. However, in the manufacture of the above-described semiconductor device, Al or the like of metal wiring may be weak to heat.
An SiN film formed by a plasma CVD method is used as an interlayer insulating film. Therefore, trap levels and trap charges are likely to be generated in a portion closer to the semiconductor substrate 1 where the element is formed and high voltage is applied. There is a problem that the element characteristics are deteriorated with time due to these levels and charges.
【0005】本発明は、このような問題を解決するため
になされたもので、半導体基板との界面や絶縁膜中の水
素の量を減らして、特性の劣化を生じない信頼性の高い
半導体装置を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is an object of the present invention to reduce the amount of hydrogen in an interface with a semiconductor substrate and in an insulating film so that a highly reliable semiconductor device which does not cause deterioration in characteristics can be obtained. The purpose is to provide.
【0006】[0006]
【課題を解決するための手段】本発明による半導体装置
は、回路素子が形成される半導体基板と、該半導体基板
上に設けられる絶縁膜と、該絶縁膜上に設けられるメタ
ル配線と、メタル配線上に設けられる保護用の絶縁膜と
を有する半導体装置であって、前記半導体基板上に設け
られる絶縁膜が少なくとも3層の絶縁膜を有し、前記半
導体基板に近い側の第1層の絶縁膜は水素濃度が1at
%以下のシリコン酸化物からなり、第2層の絶縁膜はシ
リコン過剰のシリコン酸化膜またはシリコンチッ化膜ま
たはシリコン酸化チッ化膜からなり、第3層の絶縁膜は
シリコン濃度が50at(原子)%未満のシリコンチッ
化膜からなっている。A semiconductor device according to the present invention comprises a semiconductor substrate on which circuit elements are formed, an insulating film provided on the semiconductor substrate, a metal wiring provided on the insulating film, and a metal wiring. A semiconductor device having a protective insulating film provided thereon, wherein the insulating film provided on the semiconductor substrate has at least three layers of insulating films, and an insulating layer of a first layer close to the semiconductor substrate is provided. The film has a hydrogen concentration of 1 at
% Of silicon oxide, the second-layer insulating film is made of silicon-excess silicon oxide film or silicon nitride film or silicon oxide nitride film, and the third-layer insulating film has a silicon concentration of 50 at (atoms). % Of the silicon nitride film.
【0007】ここにシリコン酸化膜、シリコンチッ化膜
またはシリコン酸化チッ化膜とは、シリコンと酸素およ
び/またはチッ素との化合物のほか、これらにリンやボ
ロンなどがドープされたものや水素など他の元素が混入
しているものも含む意味である。Here, the silicon oxide film, silicon nitride film or silicon oxide nitride film refers to a compound of silicon and oxygen and / or nitrogen, or a material obtained by doping phosphorus, boron or the like, hydrogen, or the like. It is meant to include those in which other elements are mixed.
【0008】前記第1層と第2層の絶縁膜の間に、およ
び/または第2層と第3層の絶縁膜の間にさらに第1層
もしくは第2層の絶縁膜と同種の絶縁膜が設けられてい
てもよい。メタル配線層が多く絶縁膜がさらに設けられ
る場合でも、その絶縁膜にこのような絶縁膜が設けられ
ることにより、半導体基板側への水素の侵入を防止する
ことができる。An insulating film of the same type as the first or second insulating film is further provided between the first and second insulating films and / or between the second and third insulating films. May be provided. Even when an insulating film is further provided with a large number of metal wiring layers, entry of hydrogen into the semiconductor substrate can be prevented by providing such an insulating film in the insulating film.
【0009】[0009]
【発明の実施の形態】つぎに、図面を参照しながら本発
明の半導体装置について説明をする。なお、各図は説明
図として示されており、絶縁膜部分が半導体基板の部分
より拡大して厚く書かれている。Next, a semiconductor device according to the present invention will be described with reference to the drawings. In addition, each drawing is shown as an explanatory diagram, and the insulating film portion is illustrated as being enlarged and thicker than the semiconductor substrate portion.
【0010】本発明の半導体装置は、その一実施形態の
断面説明図が図1に示されるように、たとえばp形のS
iからなる半導体基板1にトランジスタなどの回路素子
が形成され、その上に形成される絶縁膜が少なくとも3
層からなり、その3層のうち、半導体基板に一番近い第
1層の絶縁膜6は水素濃度が1at%以下のシリコン酸
化物(SiO)からなっており、前記3層のうちの真ん
中の第2層の絶縁膜7はSi量が化学量論組成比より多
いSi過剰のシリコン酸化物(SiO)またはシリコン
チッ化物(SiN)またはシリコン酸化チッ化物(Si
ON)からなっている。たとえばSiN膜の場合、Si
濃度が50at%以上である。そして一番表面側の第3
層の絶縁膜8はSi濃度が50%未満のSiN膜からな
っている。なお、図示されていないが、第3層の絶縁膜
8の表面にさらにジャンクションコート用樹脂(JC
R)またはポリイミドのような保護膜が設けられる場合
もある。A semiconductor device according to the present invention has, for example, a p-type S type as shown in FIG.
A circuit element such as a transistor is formed on a semiconductor substrate 1 made of i, and at least three insulating films are formed thereon.
Out of the three layers, the first insulating film 6 closest to the semiconductor substrate is made of silicon oxide (SiO) having a hydrogen concentration of 1 at% or less. The second insulating film 7 is made of silicon-excess silicon oxide (SiO) or silicon nitride (SiN) or silicon oxide nitride (Si) in which the amount of Si is greater than the stoichiometric composition ratio.
ON). For example, in the case of a SiN film, Si
The concentration is 50 at% or more. And the third on the most front side
The insulating film 8 is a SiN film having a Si concentration of less than 50%. Although not shown, the surface of the third insulating film 8 is further provided with a junction coat resin (JC
R) or a protective film such as polyimide may be provided.
【0011】図1において、半導体基板1には、その表
面に素子分離用の熱酸化膜2が設けられ、その間にゲー
ト絶縁膜3を介してポリシリコンなどによりゲート電極
4が設けられている。そして、たとえばゲート電極4の
両側の半導体基板1にはn+形領域からなるソース、ド
レイン領域5a、5bが形成されることにより、MOS
FETが形成されている。In FIG. 1, a semiconductor substrate 1 is provided with a thermal oxide film 2 for element isolation on the surface thereof, and a gate electrode 4 made of polysilicon or the like with a gate insulating film 3 interposed therebetween. For example, source and drain regions 5a and 5b formed of n + -type regions are formed on the semiconductor substrate 1 on both sides of the gate electrode 4, so that the MOS
An FET is formed.
【0012】ポリシリコンからなるゲート電極4上に、
前述の第1層の絶縁膜6が0.5〜2μm程度の厚さに
設けられている。この第1層の絶縁膜6は、水素濃度が
1at%以下になるように形成されたSiOからなって
いる。すなわち、SiNでは水素濃度が高くなりやすい
ので、SiOにしているが、リンがドープされたPSG
や、ボロンおよびリンがドープされたBPSGでもベー
スはSiOであり、水素濃度を低くすることができる。
この場合、ソースガスとしてモノシラン(SiH4 )を
ベースとしてプラズマCVD法により成膜すると、水素
濃度を1at%以下にすることが難しく、SiH4 を使
用する場合には常圧CVD法(熱CVD法)で成膜する
か、プラズマCVD法で行う場合には、TEOS(テト
ラエチルオルソシリケート)をソースガスのベースとす
ることが好ましい。On the gate electrode 4 made of polysilicon,
The above-mentioned first insulating film 6 is provided with a thickness of about 0.5 to 2 μm. The first insulating film 6 is made of SiO formed so that the hydrogen concentration becomes 1 at% or less. That is, since SiN tends to have a high hydrogen concentration, it is made of SiO.
Also, even in BPSG doped with boron and phosphorus, the base is SiO, and the hydrogen concentration can be reduced.
In this case, when a film is formed by plasma CVD using monosilane (SiH 4 ) as a source gas as a base, it is difficult to reduce the hydrogen concentration to 1 at% or less. When SiH 4 is used, normal pressure CVD (thermal CVD) is used. ), Or when the film is formed by a plasma CVD method, TEOS (tetraethyl orthosilicate) is preferably used as a base of the source gas.
【0013】第1層の絶縁膜6には図示しないコンタク
トホールが形成され、Alなどのメタルが成膜されてパ
ターニングされることにより、下層のゲート電極4や図
示しない配線などと接続してメタル配線9が形成されて
いる。そしてその上に第2層の絶縁膜7が設けられてい
る。A contact hole (not shown) is formed in the first insulating film 6, and a metal such as Al is formed and patterned to connect to the lower gate electrode 4 and a wiring (not shown). The wiring 9 is formed. Then, a second-layer insulating film 7 is provided thereon.
【0014】第2層の絶縁膜7は、Si量が化学量論組
成比より多いSi過剰のSiO、SiNまたはSiON
からなり、0.2〜1μm程度の厚さに形成されてい
る。たとえばSiNの場合、Si濃度を50at%以上
にすることが、ゲッタリング効率や導伝率の点から好ま
しい。このようなSi過剰の絶縁膜7を形成するには、
CVD法などにより成膜する際に、Siの原料ガスとし
てのSiH4 などの流量を多くして、プラズマCVD法
または熱CVD法などにより成膜することにより、容易
に形成される。The second insulating film 7 is made of a Si-excess SiO, SiN or SiON in which the Si content is larger than the stoichiometric composition ratio.
And is formed to a thickness of about 0.2 to 1 μm. For example, in the case of SiN, it is preferable to set the Si concentration to 50 at% or more from the viewpoint of gettering efficiency and conductivity. To form such an Si-excessive insulating film 7,
When the film is formed by the CVD method or the like, the film is easily formed by increasing the flow rate of SiH 4 or the like as the Si source gas and forming the film by the plasma CVD method or the thermal CVD method.
【0015】第3層の絶縁膜8は、Si濃度が50at
%未満のSiNからなり、0.2〜1μm程度の厚さに
形成されている。これは、通常の方法により形成される
SiN膜で、プラズマCVD法などにより形成される。
このSiN膜は、成膜時にある程度の水素を含有する
が、緻密な膜で外気からの水分などに基づく水素などの
不純物の侵入を防止する。The third insulating film 8 has an Si concentration of 50 at.
% Of SiN, and is formed to a thickness of about 0.2 to 1 μm. This is a SiN film formed by an ordinary method, and is formed by a plasma CVD method or the like.
This SiN film contains a certain amount of hydrogen at the time of film formation, but is a dense film and prevents intrusion of impurities such as hydrogen based on moisture and the like from outside air.
【0016】本発明によれば、半導体基板上に形成され
る絶縁膜が少なくとも3層の絶縁膜からなっており、そ
の3層により半導体基板側に水素が溜るのを防止してい
る。そのため、高電界によってもトラップ準位が発生し
て電気特性が劣化することがない。According to the present invention, the insulating film formed on the semiconductor substrate comprises at least three layers of insulating films, and the three layers prevent accumulation of hydrogen on the semiconductor substrate side. Therefore, even when a high electric field is generated, a trap level does not occur and electric characteristics are not deteriorated.
【0017】すなわち、基板に近い側の第1層の絶縁膜
は水素濃度の小さいSiOからなっているため、成膜時
の水素の侵入が少なく、イニシャルでの半導体基板との
界面や半導体基板に近い絶縁膜中での水素濃度を低くす
ることができる。そのため、高電界発生時においてもト
ラップ準位の形成やトラップ電荷の発生を防止すること
ができる。また、第2層の絶縁膜は、Si過剰のSi
O、SiNやSiONからなっているため、ダングリン
グボンド(表面に露出する非結合軌道)を多くもってお
り、同時に半導電性となる。そのため、化学的に極めて
活性であり、表面における反応が大きくゲッタリング作
用に優れている。その結果、第3層の絶縁膜など上の層
から拡散してくる水素を捕獲して第1層の絶縁膜の方へ
の侵入を阻止することができる。さらに、Si界面や第
1層の絶縁膜などに高電界により発生したトラップ電荷
を逃したり、電気的にキャンセルしたりする働きをす
る。また、第3層の絶縁膜は、SiNの緻密な絶縁膜か
らなり、外部からの水分などに起因する水素などの侵入
を防止する。一方、SiNはその成膜時に水素を含みや
すいが、その水素は前述の第2層の絶縁膜によりゲッタ
リングされるため、第1層側へは侵入しない。その結
果、回路素子に近い半導体基板側に水素が存在する可能
性が非常に小さくなり、高電界が印加されてもトラップ
準位などの発生がない。そのため、電気特性が劣化しな
い信頼性の高い半導体装置が得られる。That is, since the insulating film of the first layer on the side close to the substrate is made of SiO having a low hydrogen concentration, the penetration of hydrogen during film formation is small, and the interface with the semiconductor substrate and the semiconductor substrate at the initial stage are not formed. The hydrogen concentration in a close insulating film can be reduced. Therefore, formation of trap levels and generation of trap charges can be prevented even when a high electric field is generated. Further, the insulating film of the second layer is made of Si excess Si.
Since it is made of O, SiN, or SiON, it has many dangling bonds (non-bonding orbitals exposed on the surface) and at the same time becomes semiconductive. Therefore, it is chemically very active, has a large reaction on the surface, and has excellent gettering action. As a result, it is possible to capture hydrogen diffused from an upper layer such as the third insulating film and to prevent entry into the first insulating film. Further, it functions to escape trapped charges generated by a high electric field at the Si interface, the first layer insulating film, and the like, and to electrically cancel the trapped charges. The third layer insulating film is formed of a dense insulating film of SiN, and prevents entry of hydrogen or the like due to moisture or the like from the outside. On the other hand, SiN tends to contain hydrogen at the time of film formation, but the hydrogen does not enter the first layer side because the hydrogen is gettered by the insulating film of the second layer. As a result, the possibility that hydrogen is present on the semiconductor substrate side close to the circuit element is greatly reduced, and no trap level is generated even when a high electric field is applied. Therefore, a highly reliable semiconductor device in which electric characteristics are not deteriorated can be obtained.
【0018】この構造の絶縁膜を有するNMOSの半導
体装置を製造して数十Vから数百V程度の逆バイアスの
印加および温度が150℃で、相対湿度が85%の雰囲
気のストレス下に長時間おく、高温、高湿、逆バイアス
の加速試験を行った場合に、同じ回路素子が形成された
半導体装置で従来の絶縁膜で形成したものを同じ条件で
加速試験を行った結果と対比して図2に示す。図2から
明らかなように、従来の絶縁膜を使用したものCは、2
00時間程度のストレスで殆ど100%が不良品になっ
ていたものが、本発明の構造にしたものDは、200時
間以上経過しても不良率は殆ど0であった。An NMOS semiconductor device having an insulating film of this structure is manufactured, and a reverse bias of several tens of volts to several hundred volts is applied, and the temperature is increased to 150 ° C. and the relative humidity is increased to 85% under the stress of an atmosphere. When the accelerated test of high temperature, high humidity, and reverse bias is performed for a long time, the result is compared with the result of the accelerated test under the same conditions of the semiconductor device with the same circuit element formed with the conventional insulating film. FIG. As is clear from FIG. 2, the case C using the conventional insulating film is 2
Almost 100% of the products were rejected under the stress of about 00 hours, but the product D of the structure of the present invention had a rejection rate of almost 0 even after 200 hours or more.
【0019】図3(a)〜(c)は、図1の構造の変形
例で、メタル配線9a、9bが2層に設けられる場合の
例が示されている。図3(a)に示される例は、第1の
メタル配線9aが第1層の絶縁膜6上に設けられ、第2
のメタル配線9bが第2層の絶縁膜7上に設けられ、そ
の上に第3層の絶縁膜8が設けられている。第1層から
第3層の絶縁膜6〜8の構造は図1に示される例と同じ
で、このようにメタル配線が2層である場合でも同様に
水素の侵入を防止することができる。FIGS. 3A to 3C show a modification of the structure of FIG. 1, in which metal wirings 9a and 9b are provided in two layers. In the example shown in FIG. 3A, the first metal wiring 9a is provided on the insulating film 6 of the first layer,
Is provided on the second-layer insulating film 7, and a third-layer insulating film 8 is provided thereon. The structures of the first to third insulating films 6 to 8 are the same as those in the example shown in FIG. 1. Even when the metal wiring has two layers, intrusion of hydrogen can be similarly prevented.
【0020】図3(b)に示される例は、メタル配線の
増加に合せて絶縁膜の数も増やした例で、第1層の絶縁
膜6と第2層の絶縁膜7との間に第4の絶縁膜10が設
けられ、第1層の絶縁膜6の上に第1のメタル配線9a
が設けられ、第4の絶縁膜10の上に第2のメタル配線
9bが設けられている。この第4の絶縁膜10は、前述
と同様に水素の侵入を防ぐ必要があり、第1層の絶縁膜
6と同様に水素濃度が1at%以下と少ないSiO膜で
形成するか、または第2層と同様にSiが過剰のSi
O、SiNまたはSiON膜を形成することにより水素
の侵入を防ぐことができる。The example shown in FIG. 3B is an example in which the number of insulating films is increased in accordance with the increase in the number of metal wirings, and between the insulating film 6 of the first layer and the insulating film 7 of the second layer. A fourth insulating film 10 is provided, and a first metal wiring 9 a is formed on the first insulating film 6.
Is provided, and a second metal wiring 9 b is provided on the fourth insulating film 10. The fourth insulating film 10 needs to prevent the intrusion of hydrogen in the same manner as described above. Like the first insulating film 6, the fourth insulating film 10 may be formed of a SiO film having a hydrogen concentration as low as 1 at% or less, or Excess Si as well as layer
By forming an O, SiN, or SiON film, entry of hydrogen can be prevented.
【0021】図3(c)に示される例は、メタル配線の
増加に伴う絶縁膜の増加を、第2層の絶縁膜7と第3層
の絶縁膜8との間に、第4の絶縁膜10として設けられ
ているものである。この例でも、図3(b)の例と同様
に、第4の絶縁膜10は、第1層の絶縁膜または第2層
の絶縁膜と同様の材料の絶縁膜が用いられることによ
り、水素の基板側への侵入を充分に防止することができ
る。In the example shown in FIG. 3C, the increase in the thickness of the insulating film due to the increase in the number of metal wirings is caused by the fourth insulating film 8 between the second insulating film 7 and the third insulating film 8. It is provided as a film 10. Also in this example, as in the example of FIG. 3B, the fourth insulating film 10 is formed by using an insulating film of the same material as the first insulating film or the second insulating film, so that hydrogen is used. Can be sufficiently prevented from entering the substrate side.
【0022】[0022]
【発明の効果】本発明の構造によれば、半導体基板側の
水素の量が非常に少なく、またその後に水素が基板側に
拡散することもないため、トラップ準位やトラップ電荷
による素子特性の経時劣化が生じない。その結果、安定
した電気特性を維持することができ、信頼性の高い半導
体装置が得られる。According to the structure of the present invention, the amount of hydrogen on the semiconductor substrate side is very small, and hydrogen does not diffuse to the substrate side thereafter. No aging degradation occurs. As a result, stable electric characteristics can be maintained, and a highly reliable semiconductor device can be obtained.
【図1】本発明の半導体装置の一実施形態の絶縁膜部分
の構造を示す図である。FIG. 1 is a diagram showing a structure of an insulating film portion of an embodiment of a semiconductor device of the present invention.
【図2】図1の構造の半導体装置にストレスを加えて加
速試験を行ったときの不良率を従来の構造のものの不良
率と対比して示す図である。FIG. 2 is a diagram showing a defect rate when an accelerated test is performed by applying stress to the semiconductor device having the structure of FIG. 1 in comparison with a defect rate of a conventional structure.
【図3】本発明の半導体装置の他の実施形態の絶縁膜部
分の構造を示す図である。FIG. 3 is a diagram showing a structure of an insulating film portion of another embodiment of the semiconductor device of the present invention.
【図4】従来の半導体装置の絶縁膜部分の構造を示す図
である。FIG. 4 is a diagram showing a structure of an insulating film portion of a conventional semiconductor device.
1 半導体基板 6 第1層の絶縁膜 7 第2層の絶縁膜 8 第3層の絶縁膜 9 メタル配線 10 第4の絶縁膜 Reference Signs List 1 semiconductor substrate 6 first-layer insulating film 7 second-layer insulating film 8 third-layer insulating film 9 metal wiring 10 fourth insulating film
Claims (3)
半導体基板上に設けられる絶縁膜と、該絶縁膜上に設け
られるメタル配線と、メタル配線上に設けられる保護用
の絶縁膜とを有する半導体装置であって、前記半導体基
板上に設けられる絶縁膜が少なくとも3層の絶縁膜を有
し、前記半導体基板に近い側の第1層の絶縁膜は水素濃
度が1at%以下のシリコン酸化物からなり、第2層の
絶縁膜はシリコン濃度がシリコン過剰のシリコン酸化膜
またはシリコンチッ化膜またはシリコン酸化チッ化膜か
らなり、第3層の絶縁膜はシリコン濃度が50at%未
満のシリコンチッ化膜からなる半導体装置。1. A semiconductor substrate on which a circuit element is formed, an insulating film provided on the semiconductor substrate, a metal wiring provided on the insulating film, and a protective insulating film provided on the metal wiring. Wherein the insulating film provided on the semiconductor substrate has at least three insulating films, and the first insulating film on the side closer to the semiconductor substrate has a hydrogen concentration of 1 at% or less. The second layer insulating film is made of a silicon oxide film or a silicon nitride film having a silicon concentration of excess silicon, and the third layer insulating film is made of a silicon chip having a silicon concentration of less than 50 at%. Semiconductor device consisting of an oxide film.
に第1層もしくは第2層の絶縁膜と同種の絶縁膜が設け
られてなる請求項1記載の半導体装置。2. The semiconductor device according to claim 1, further comprising an insulating film of the same type as the first or second insulating film, between the first and second insulating films.
に第1層もしくは第2層の絶縁膜と同種の絶縁膜が設け
られてなる請求項1または2記載の半導体装置。3. The semiconductor device according to claim 1, wherein an insulating film of the same kind as the first or second layer is further provided between the second and third insulating films.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9159589A JPH118234A (en) | 1997-06-17 | 1997-06-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9159589A JPH118234A (en) | 1997-06-17 | 1997-06-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH118234A true JPH118234A (en) | 1999-01-12 |
Family
ID=15697016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9159589A Pending JPH118234A (en) | 1997-06-17 | 1997-06-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH118234A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002353444A (en) * | 2001-05-28 | 2002-12-06 | Fuji Electric Co Ltd | Semiconductor device |
| KR100401504B1 (en) * | 2001-01-16 | 2003-10-17 | 주식회사 하이닉스반도체 | Method of forming a passivation layer in a semiconductor device |
| JP2007088018A (en) * | 2005-09-20 | 2007-04-05 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
| JP2008159806A (en) * | 2006-12-22 | 2008-07-10 | Sharp Corp | Semiconductor light emitting device and manufacturing method thereof |
| JP2014033053A (en) * | 2012-08-02 | 2014-02-20 | Toyota Motor Corp | Semiconductor device and method for manufacturing the same |
| JP2014049695A (en) * | 2012-09-03 | 2014-03-17 | Toyota Motor Corp | Semiconductor device and method of manufacturing the same |
-
1997
- 1997-06-17 JP JP9159589A patent/JPH118234A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100401504B1 (en) * | 2001-01-16 | 2003-10-17 | 주식회사 하이닉스반도체 | Method of forming a passivation layer in a semiconductor device |
| JP2002353444A (en) * | 2001-05-28 | 2002-12-06 | Fuji Electric Co Ltd | Semiconductor device |
| JP2007088018A (en) * | 2005-09-20 | 2007-04-05 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
| JP2008159806A (en) * | 2006-12-22 | 2008-07-10 | Sharp Corp | Semiconductor light emitting device and manufacturing method thereof |
| JP2014033053A (en) * | 2012-08-02 | 2014-02-20 | Toyota Motor Corp | Semiconductor device and method for manufacturing the same |
| US9082778B2 (en) | 2012-08-02 | 2015-07-14 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and manufacturing method of same |
| JP2014049695A (en) * | 2012-09-03 | 2014-03-17 | Toyota Motor Corp | Semiconductor device and method of manufacturing the same |
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