JPH117440A - Processor, compiler, product-sum operation method, and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce hardware costs by executing alternately a set of a load instruction(MOV) and a multiplication instruction(MULA) and a set of the load instruction and an cumulative addition instruction (ADDA). SOLUTION: An instruction execution circuit 604 executes a load instruction(MOV) and a multiplication instruction(MULA) through a parallel operation of a computing element 21 and a multiplier 28, and carries out the load instruction(MOV) and a cumulative addition instruction(ADDA) through a parallel operation of the element 21 and the multiplier 28. Then, a processor which is provided with an instruction reading circuit that simultaneously reads two instructions, an instruction decoding circuit that detects instructions which are parallelly carried out and controls the circuit 604 and the circuit 604 performs processing for a product-sum operation of one time in two cycles. That is, the loading of data to 1st and 2nd registers is not performed at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor, a compiler, a product-sum operation method, and a recording medium, and more particularly to a processor for performing a product-sum operation, and a compiler for translating a high-level language program including a product-sum operation code into a machine instruction program. The present invention relates to a product-sum operation method for performing a product-sum operation on a value previously stored in a storage area, and a recording medium on which the high-level language program or the machine instruction program is recorded.

[0002]

2. Description of the Related Art With the development of electronic technology in recent years, high-performance processors have become widespread and used in all fields.
Particularly in application fields such as multimedia, image processing and audio processing techniques are key, and a product-sum operation is essential for such processing. Since the image processing and the audio processing are required to be performed in real time, the product-sum operation must be performed as fast as possible. The product-sum operation refers to an operation of taking out data one by one from the two data arrays, performing multiplication, and cumulatively adding the products.

Further, programs for realizing image processing and audio processing are continually increasing in scale with the advancement of processing, and from the viewpoint of improving the productivity of program development, etc.
Written in a high-level language. Therefore, in order to execute a program for performing the product-sum operation, techniques relating to a processor and a compiler are required. Here, the compiler translates a program described in a high-level language into a machine instruction program executable by a processor.

(First Prior Art) A first prior art for processing a product-sum operation is a technology for performing a product-sum operation by a general-purpose processor alone. Here, the general-purpose processor refers to a processor having no special circuit for the product-sum operation. FIG. 4 is a diagram showing a C-language program for performing the product-sum operation.

FIG. 13 is a program list as a result of translating a C language program into a machine instruction program. Hereinafter, the first related art will be described with reference to FIGS. 4 and 13.
In order to perform a product-sum operation on a general-purpose processor, the compiler converts a fragment of the C language program shown in FIG. 4 into a machine instruction program shown in FIG. In FIG. 4, for
The statement represents a loop, and the variable sum is obtained by cumulatively adding the product of the array variable x [i] and the array variable y [i] for the array number i. FIG.
Reference numeral 3 indicates that six instructions are required for one process of product and sum (corresponding to a loop by a for statement in FIG. 4).
Instructions 1 and 2 are instructions for reading data from storage areas corresponding to two array variables, instruction 3 is a multiplication instruction (product is obtained by dividing into upper and lower parts), and instruction 4 is accumulation of lower part of the product. Addition instruction, instruction 5 is an instruction to transfer the higher order of the product,
The instruction 6 is an addition instruction for accumulating the higher order of the product together with the carry obtained by the instruction 4. By repeatedly executing the machine instruction program shown in FIG. 13 on a general-purpose processor, a product-sum operation is realized.

(Second Prior Art) A second prior art for performing a product-sum operation is a technology for performing a product-sum operation by adding a dedicated product-sum operation circuit to a general-purpose processor. FIG. 14 is a block diagram showing a configuration of the dedicated product-sum operation circuit. Hereinafter, the second related art will be described with reference to FIG. The dedicated product-sum operation circuit reads the two data from the storage areas A and B (1203, 1207) at the same time and supplies the data to the multiplier 1209, so that the address calculation units A and B ( 1201,
1205), two storage area access units A and B (1202 and 1206) for accessing the storage area and two data transfer units A and B (1204 and 1208) for transferring the obtained data.
Have a system. Further, the dedicated product-sum operation circuit includes a multiplier 1209 for obtaining a product of two data, an adder 1210 for accumulating the product, and an accumulation result register 1211 for storing the accumulated result.

Therefore, in the second prior art, the dedicated product-sum operation circuit added to the general-purpose processor has a function of performing the product-sum operation at high speed. According to this technique, one process of the product-sum operation is realized in one instruction and one cycle.

[0008]

However, according to the first prior art, the general-purpose processor uses the instruction 1 shown in FIG.
However, even if all of the instructions 6 to 6 can be executed in one cycle, it takes six cycles to perform one multiply-accumulate operation, and a required processing performance cannot be obtained. In addition, many general-purpose processors without a multiplier require a larger number of cycles because a product is obtained by repeating addition by an adder.

In the second prior art, a dedicated product-sum operation circuit has two systems each of a means for obtaining an address for accessing a storage area, a means for accessing a storage area, and a means for transferring obtained data. There is a problem that the cost of hardware increases at the required point. In view of the above, it is an object of the present invention to provide a processor that keeps the cost of hardware low and that performs a product-sum operation at high speed.

[0010]

In order to solve the above problems, a processor according to the present invention comprises a first memory located in a storage area.
A processor for obtaining the product of the array element of the array data and the array element of the second array data for each array element and accumulatively adding the product, comprising: an instruction reading means for reading an instruction from a program memory; Instruction decoding means for decoding the read first and second extended instructions, first to fourth registers, and array elements of the first and second array data, Data loading means for loading the first and second registers, multiplication means for obtaining the product of the contents of the first and second registers and storing the result in the third register; Adding means for obtaining the sum of the contents of the fourth register and storing the sum again in the fourth register; and causing the multiplying means to execute when the first extended instruction is decoded by the instruction decoding means. A first execution control means for loading a new said sequence elements of the first array data in the data loading unit in parallel, the second by the instruction decoding means
And a second execution control means for executing the addition means in parallel with loading the array elements of the second array data into the data loading means when the extended instruction is decoded. It is characterized by having.

Thus, the processor according to the present invention is characterized in that the execution of the data load means for loading data into the first register and the execution of the data load means to load data into the second register include: Since the first execution control means and the second execution control means are separately controlled and the data loading to the first and second registers is not performed simultaneously, the data loading means includes Since only one system is required for obtaining the address for accessing the area and for accessing the storage area, the hardware cost is reduced as compared with the case of using the dedicated product-sum operation circuit shown in the second prior art. Can be kept low.

Also, in the processor according to the present invention, the first execution control means makes the data load means and the multiplication means parallel, and the second execution control means makes the data load means and the addition means Are performed in parallel, so that the product-sum operation can be performed at a higher speed than in the case of using the general-purpose processor described in the first related art.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. (Compiler) FIG. 1 is a block diagram showing the configuration of the compiler. The compiler 102 uses the C
Translates the language program 101 into the machine instruction program 1
10 is output.

The compiler 102 is a C language program 1
01 into the read buffer 104, and a syntax analyzer 10 that analyzes the syntax and meaning of the C language program read into the read buffer 104, generates intermediate code, and writes the intermediate code into the intermediate code buffer 106.
5, a machine instruction generation unit 107 that receives the intermediate code stored in the intermediate code buffer 106 to generate a machine instruction program and writes the generated machine instruction program to the output buffer 108, and stores the machine instruction program stored in the output buffer 108 as a file. And a file output unit 109 for outputting to

FIG. 2 is a flowchart showing a processing flow of the syntax analysis unit 105. FIG. 3 is a flowchart showing a processing flow of the machine instruction generation unit 107. FIG. 4 is a program list showing a part of a C language program. In FIG. 4, a for statement represents a loop, and is described with the intention of obtaining a variable sum by accumulating the product of an array variable x [i] and an array variable y [i] for an array number i. .

FIG. 5 is a list showing a machine instruction program generated by a compiler when the C language program shown in FIG. 4 is given as an input. The machine instruction program is originally a bit string of 0s and 1s, but is represented by a mnemonic in FIG. less than,
The operation of the compiler having the above configuration when the program list of FIG. 4 is input will be described with reference to FIGS. 1, 2, 3, 4, and 5.

The file reading unit 103 reads a C language program described by a user, and reads a C buffer program.
To be stored. The syntax analysis unit 105 reads the read buffer 10
4 is retrieved and analyzed (step 202). "Sum = su" of the program shown in FIG.
For “m + x [i] * y [i];”, “the product of the first array variable and the second array variable is obtained for each array element and cumulatively added”
(Step 203)
An intermediate code indicating a product-sum operation is output to the intermediate code buffer 106 (step 204).

The machine instruction generation unit 107 extracts the intermediate code stored in the intermediate code buffer 106 (step 302), determines that the intermediate code is a product-sum operation (step 303), and performs a product-sum operation. A machine instruction group for processing (repetition of MOV, MULA, MOV, ADDA) is output to the output buffer 108 (step 304). The file output unit 109 outputs the machine instruction stored in the output buffer 108 to a file.

The machine instruction program output to this file is as shown in the list of FIG. Hereinafter, the meanings of the instructions 1 to 14 shown in FIG. 5 will be described. Instruction 14
Hereinafter, this is repeated in units of four instructions, but the description is omitted here. Instruction 1: MOV @ (A0), D0 Loads 16-bit data at the address indicated by the value of address register A0 into data register D0.

Instruction 2: MOV @ (A1), D1 Loads 16-bit data at the address indicated by the value of address register A1 into data register D1. Instruction 3: MOV @ (2, A0), D0 Loads 16-bit data at an address obtained by adding a 2-byte deviation to the value of address register A0 to data register D0.

Instruction 4: MULA D0, D1 A 32-bit product is obtained by multiplying the value of data register D0 by the value of data register D1. The product is stored in a predetermined register that is not visible to the program. Instruction 5: MOV @ (2, A1), D1 Loads 16-bit data at the address obtained by adding a 2-byte deviation to the value of the address register A1 to the data register D1.

Instruction 6: ADDA Adds the value of a 32-bit register obtained by connecting the product-sum lower-order register ACCL and the product-sum upper-order register ACCH to the 32-bit product generated by the most recent MULA instruction. Is stored again in the product-sum lower-order register ACCL and the product-sum upper-order register ACCH. If a carry occurs during the addition, the contents of the product-sum carry accumulation register ACCC are incremented by one.

Instruction 7: MOV @ (4, A0), D0 Loads 16-bit data at the address obtained by adding a 4-byte deviation to the value of the address register A0 to the data register D0. Instruction 8: MULA D0, D1 (same as instruction 4) Instruction 9: MOV @ (4, A1), D1 16-bit data at the address obtained by adding the 4-byte deviation to the value of the address register A1 is the data register D1. To load.

Instruction 10: ADDA (same as instruction 6) Instruction 11: MOV @ (6, A0), D0 16-bit data at the address obtained by adding the displacement of the address register A0 by 6 bytes to the data register D0. To load.

Instruction 12: MULA D0, D1 (same as instruction 4) Instruction 13: MOV @ (6, A1), D1 16-bit data at the address obtained by adding the displacement of 6 bytes to the value of the address register A1. Load data register D1.

Instruction 14: ADDA (same as instruction 6) However, the load instructions of instructions 1, 2, 3, 5, 7, 9, 11, and 13 employ a so-called delayed load method, and the immediately following instruction Cannot use the load result in

By the above operation, the compiler 102
The multiply-accumulate operation in the C language program 101 described by the user is repeated by repeating the above-described instruction sequence including a load instruction (MOV), a multiplication instruction (MULA), a load instruction (MOV), and an accumulative addition instruction (ADDA). A machine instruction program 110 for translating the machine instructions in order to maximize the product-sum operation speed of the processor according to the present invention is generated. (Processor) FIG. 6 is a schematic configuration diagram of the processor.

The processor 601 includes an instruction reading circuit 602 for reading a machine instruction (hereinafter, abbreviated as an instruction) from the program memory 607, and an instruction decoding circuit 603 for decoding the read instruction and controlling the instruction execution circuit 604. And an instruction execution circuit 604 for accessing the data memory 608 as necessary and executing the instruction. The program memory 607 is a program memory for storing a machine instruction program, and the data memory 608 is a data memory for mainly storing operand data. The size of one instruction of the program stored in the program memory 607 is 16 bits.

The instruction bus 605 is connected to the program memory 60
7 and a data bus 606 for supplying an instruction to the processor 601, a data memory 608 and the processor 6
This is a data bus for transferring data to and from the data bus 01.
The bus width of the instruction bus 605 is 32 bits. The instruction reading circuit 602, the instruction decoding circuit 603, and the instruction execution circuit 604 perform pipeline processing.

The instruction reading circuit 602 has an instruction buffer having a size of four instructions (16 bits). The instruction readout circuit 602 reads out two consecutive instructions at the same time from the program memory 607 via the instruction bus 605 and stores them in the instruction buffer. However, if there is no free space in the instruction buffer for two instructions, the instruction decoding circuit 603 decodes the instruction and waits for a free space.

The instruction decoding circuit 603 includes an instruction reading circuit 6
If the two instructions read in 02 are MOV and MULA, the two instructions are taken out of the instruction buffer and the instruction is given to the instruction execution circuit 604 to execute MOV and MULA simultaneously. The instruction decoding circuit 603 includes an instruction reading circuit 60.
If the two instructions read in step 2 are MOV and ADDA, two instructions are fetched from the instruction buffer and an instruction is given to the instruction execution circuit 604 to execute MOV and ADDA simultaneously.

However, the instruction decoding circuit 603 determines that the two instructions read by the instruction reading circuit 602 are “MOV and MULA”.
Otherwise, if it is other than “MOV and ADDA”, one instruction is fetched from the instruction buffer and an instruction is given to the instruction execution circuit 604 to execute the instruction. Instruction execution circuit 604
Is a circuit that includes an arithmetic unit, a multiplier, and an adder, and executes an operation corresponding to an instruction. The detailed configuration of the instruction execution circuit 604 will be described later.

FIG. 7 is a processing timing chart showing the processing timing of the instruction reading circuit 602, the instruction decoding circuit 603, and the instruction execution circuit 604. The instruction numbers in FIG. 7 correspond to the program list in FIG. 5 described above. The outline of the operation of the processor will be described below with reference to FIGS. First, the instruction reading circuit 602 reads instruction 1 and instruction 2 from the program memory 607 (cycle 1). The instruction decoding circuit 603 decodes the instruction 1 and the instruction 2 (cycle 2), and causes the instruction execution circuit 604 to execute only the instruction 1 (cycle 3).

Since there is still room for two instructions, the instruction reading circuit 602 reads the next instruction 3 and instruction 4 (cycle 2). The instruction decoding circuit 603 decodes the instruction 2 and the instruction 3 (cycle 3) and causes the instruction execution circuit 604 to execute only the instruction 2 (cycle 4). Since there is only one free instruction, the instruction reading circuit 602 does not read the instruction (cycle 3). The instruction decoding circuit 603 decodes the instructions 3 and 4 (cycle 4) and causes the instruction execution circuit 604 to execute the instructions 3 and 4 in parallel (cycle 5).

Since there is room for two instructions, the instruction reading circuit 602 reads instructions 5 and 6 (cycle 4). The instruction decoding circuit 603 decodes the instruction 5 and the instruction 6 (cycle 5) and converts the instruction 5 and the instruction 6 into the instruction execution circuit 60.
4 is executed in parallel (cycle 6). Instruction reading circuit 6
02 reads out the instructions 7 and 8 (cycle 5). The instruction decoding circuit 603 decodes the instructions 7 and 8 (cycle 6) and causes the instruction execution circuit 604 to execute the instructions 7 and 8 in parallel (cycle 7).

The instruction reading circuit 602 is provided with instructions 9 and 1
0 is read (cycle 6). The instruction decoding circuit 603 decodes the instructions 9 and 10 (cycle 7) and causes the instruction execution circuit 604 to execute the instructions 9 and 10 in parallel (cycle 8). The instruction reading circuit 602 includes the instruction 11, the instruction 12,
Is read (cycle 7). The instruction decoding circuit 603 decodes the instructions 11 and 12 (cycle 8) and causes the instruction execution circuit 604 to execute the instructions 11 and 12 in parallel (cycle 9).

The instruction reading circuit 602 reads the instructions 13 and 14 (cycle 8). The instruction decoding circuit 603 decodes the instructions 13 and 14 (cycle 9), and
And the instruction 14 is executed in parallel by the instruction execution circuit 604 (cycle 10). As mentioned above, the combination of MOV and MULA, and MO
The set of V and ADDA is executed alternately. The set of MOV and MULA and the set of MOV and ADDA are each executed in one machine cycle, which will be described in detail below.

FIG. 8 is a block diagram showing a detailed configuration of the instruction execution circuit 604. The instruction execution circuit 604 includes an A bus (ABUS) 14, a B1 bus (B1BUS) 15, and a B2 bus (B2BUS) 1.
6, address register file (ARF) 17, data register file (DRF) 18, selector (SAR) 19, selector
(SDR) 20, an arithmetic unit (ALU) 21 for performing an arithmetic and logic operation on two data inputs A and B, a selector (SAA) 22 for selecting the A input of the arithmetic unit 21, and a B input of the arithmetic unit 21 (SAB) 23, an arithmetic unit output buffer (ALOB) 24 for holding the output of the arithmetic unit 21, an operand address buffer (OAB) 25, a store buffer (STB) 26, a load buffer (LDB) 27, and A Multiplies two data inputs with B, sum output S and carry output C for the lower L output of the product with a data width twice the input data width and the upper product.
(MPY) 28, an adder (CPA) 29 for carrying and carrying and adding the sum output S and the carry output C of the multiplier 28 as an A input and a B input, and the A input of the adder 29, respectively. (SMA) 30, a selector (SMB) 31 for selecting the B input of the adder 29, a latch (PRL) 32 for holding the L output of the multiplier 28, and the output of the adder 29 which is the upper part of the product. (PRH1) 33 for holding the data, a latch (PRH2) 34 for adjusting the timing to supply the contents of the latch 33 to the adder 29 again, and selectively holding the contents of the arithmetic unit output buffer 24 to perform cumulative addition. An accumulator lower-order digit register (ACCL) 35 for storing the lower part of the product, an accumulator upper-order digit register (ACCH) 36 for selectively holding the contents of the latch 33 and storing the upper part of the accumulated product, When the contents of the output buffer 24 are selectively held and the product is cumulatively added. Configured to increase in 蓄Ru product sum carry accumulation register (ACCC) 37.

A bus (ABUS) 14 and B1 bus (B1BUS) 15 and B2
The bus (B2BUS) 16 is a bus for transferring data to be operated and data of the operation result. The address register file (ARF) 17 is composed of four address registers A0 to A3, and the data register file (DRF) 18
Is composed of four data registers D0 to D3.

The selector (SAR) 19 is a selector for selecting an input of the address register file 17, and the selector (SDR) 20 is a selector for selecting an input of the data register file 18. Multiplier 28 comprises a plurality of carry save adders combined in a tree to add partial products, and from the last stage of the tree, sum output and carry output of individual bit carry save adders. Is output as it is.

The carry input at the time of addition of the arithmetic unit 21 is the carry output of the adder 29, and the carry input of the adder 29 is connected to the carry output of the arithmetic unit 21. 29 operate in conjunction. Note that everything from the address register file 17 to the product-sum carry accumulation register 37 is 16 bits wide.

The symbols T1, T2, and TA shown in FIG. 8 indicate clock timings at which writing to a register or a latch is performed. FIG. 9 is an explanatory diagram of the contents of the data memory 608 storing data accessed by the machine instruction program of FIG. Data x'1111 at address x'1000, data x'2222 at address x'1002, data x'3333 at address x'1004, x '
Data x'4444 at address 2000, data x'5555 at address x'2002
However, data x'6666 is stored at address x'2004. Here, the address is assigned for each byte (8 bits), and the data is accessed by the address of the least significant byte.
x 'represents a hexadecimal number.

FIGS. 10 to 12 show operation timing charts of the instruction execution circuit 604 in the processor 601. FIG. 10 to 12 show the clock T2 and the clock
T1, clock TA, address register A0 and address register A1 in address register file ARF17, data register D in data register file DRF18
0 and data register D1, multiply-accumulate lower digit register ACCL3
5. Product-sum upper digit register ACCH36, product-sum carry accumulation register ACCC37, A bus ABUS14, B1 bus B1BUS15, B2 bus B2BUS16, output of arithmetic unit ALU21, output of multiplier MPY28, output of adder CPA29, operand address buffer The values of the OAB 25 and the load buffer LDB 27 are shown for each timing called a machine cycle.

The cycle t1 to cycle t4 is shown in FIG. 10, the cycle t5 to cycle t8 is shown in FIG. 11, the cycle t9 and the cycle t10 are shown in FIG. ), The latter half period in which the clock T1 becomes H is indicated by (1). Here, for the MOV instruction, the operand address buffer OAB25 is connected to the data bus 6
Cycle output to 06, multiplier for MULA instruction
When the cycle in which the MPY 28 operates and the cycle in which the arithmetic unit ALU 21 and the adder CPA 29 operate with respect to the ADDA instruction are considered as instruction execution cycles, respectively, the cycle t2 in FIG. 10 is the machine cycle 3 in FIG. 7, and the cycle t3 in FIG. This corresponds to machine cycle 4 in FIG. 7 (the same applies hereinafter).

The initial value x'10 is stored in the address register A0.
00, the initial value x'2000 is stored in the address register A1, and the initial value x'0000 is stored in the product-sum lower digit register 35, the product-sum upper digit register 36, and the product-sum carry accumulation register 37. I do. The operation of the instruction execution circuit 604 when executing the machine instruction program shown in FIG. 5 will be described below with reference to FIGS. 8, 9, 10, 11, and 12. (Instruction 1) Instruction 1 is a cycle t1 (1) to a cycle t3 (2).
And executed by the instruction execution circuit 604.

In cycle t1 (1), the value x'1000 of the address register A0 and the value x'0000 due to the deviation being 0 are passed through the B1 bus 15 and the B2 bus 16, the selector 23 and the selector 22, respectively. Then, the arithmetic unit 21 adds the values. In cycle t2 (2), the value x'1000 of the result of the addition is stored in the operand address register 25 via the arithmetic unit output buffer 24 and output to the data bus 606 as an address, and the data is read from the address x'1000 in the data memory 608. Read.

The read value x'1111 is held in the load buffer 27 in cycle t2 (1), and stored in the data register D0 via the selector 20 in cycle t3 (2). (Instruction 2) Instruction 2 is a cycle t2 (1) to a cycle t4 (2).
And executed by the instruction execution circuit 604.

In the cycle t2 (1), the value x'2000 of the address register A1 and the value x'0000 due to the deviation being 0 pass through the B1 bus 15 and the B2 bus 16, and the selector 23 and the selector 22, respectively. Then, the arithmetic unit 21 adds the values. In the cycle t3 (2), the value x'2000 of the addition result is stored in the operand address register 25 via the arithmetic unit output buffer 24 and output to the data bus 606 as an address, and the data is read from the address x'2000 in the data memory 608. Read.

The read value x'4444 is held in the load buffer 27 at cycle t3 (1), and stored in the data register D1 via the selector 20 at cycle t4 (2). (Instruction 3) Instruction 3 is from cycle t3 (1) to cycle t5 (2)
And executed by the instruction execution circuit 604.

In cycle t3 (1), the value x'1000 of the address register A0 and the deviation value x'0002 are respectively
5 and the B2 bus 16, the selector 23, and the selector 22 via the selector 22. In the cycle t4 (2), the value x'1002 of the result of the addition is stored in the operand address register 25 via the arithmetic unit output buffer 24 and output to the data bus 606 as an address.
Data is read from the address x'1002 of No. 8.

The read value x'2222 is held in the load buffer 27 at cycle t4 (1), and is stored in the data register D0 via the selector 20 at cycle t5 (2). (Instruction 4) The instruction 4 is the instruction decoding circuit 60 at the same time as the instruction 3.
3 and are executed by the instruction execution circuit 604 in parallel. Strictly speaking, instruction 4 starts at cycle t4 (2) and ends at cycle t4 (2).
4 (1) is executed by the instruction execution circuit 604.

In cycle t4 (2), data register D
The multiplier 28 multiplies the value x'1111 of 0 and the value x'4444 of the data register D1 via the A bus 14 and the B2 bus 16, respectively. The value x'0c84, the lower 16 bits of the product, is the cycle
The data is stored in the latch 32 at t4 (1). The sum output and carry output of the upper 16 bits of the product are added by the adder 29 via the selector 30 and the selector 31, respectively, and the value x'048d of the addition result is stored in the latch 33 at cycle t4 (1). Is done. (Instruction 5) The instruction 5 is a cycle t4 (1) to a cycle t6 (2).
And executed by the instruction execution circuit 604.

In cycle t4 (1), the value x'2000 of the address register A1 and the value x'0002 of the deviation are respectively transferred to the B1 bus 1
5 and the B2 bus 16, the selector 23, and the selector 22 via the selector 22. In the cycle t5 (2), the value x'2002 of the addition result is stored in the operand address register 25 via the arithmetic unit output buffer 24 and output to the data bus 606 as an address.
The data is read from the address 8'x'2002.

The read value x'5555 is held in the load buffer 27 at cycle t5 (1), and is stored in the data register D1 via the selector 20 at cycle t6 (2). (Instruction 6) The instruction 6 is the instruction decoding circuit 60 at the same time as the instruction 5.
3 and are executed by the instruction execution circuit 604 in parallel. Strictly speaking, instruction 6 starts at cycle t5 (2) and ends at cycle t5 (2).
The processing is executed by the instruction execution circuit 604 up to 6 (1).

In cycle t5 (2), the value x'0000 of the product-sum lower-order register 35 and the value x'0c84 of the latch 32 are transferred via the A bus 14 and the B2 bus 16 and the selectors 22 and 23, respectively. The addition is performed by the adder 21. Cycle t5
In (1), the value x'0c84 of the addition result is stored in the arithmetic unit output buffer 24.
, Is again stored in the product-sum lower-order register 35, and the value x′048d of the latch 33 is transferred to the latch 34. Further, in cycle t5 (1), the value x'048d held in the latch 34 and the value x'0000 of the product-sum upper-order register 36 are added to the adder 2 via the selector 31 and the selector 30, respectively.
9 is added. At this time, the carry output from the most significant bit of the arithmetic unit 21 is added as a carry input to the least significant bit of the adder 29, and the value of the carry input is 0.

At cycle t6 (2), the value x'048d of the addition result is stored again in the product-sum upper-order register 36 via the latch 33. Next, in cycle t6 (2), the value x'0000 of the product-sum carry accumulation register 37 selected by the selector 23 and the value x'0000 output by the selector 22 without selecting anything are
The arithmetic unit 21 adds the carry output from the most significant bit of the adder 29 as the carry input to the least significant bit. The value of the carry input is 0, and the value of the addition result x'00
00 is stored in the multiply-accumulate carry accumulation register 37 again at cycle t6 (1) via the arithmetic unit output buffer 24.

As described above, the products are cumulatively added by the three addition operations, and the product-sum processing up to the first time is completed. (Instruction 7) The instruction 7 starts from cycle t5 (1) to cycle t7 (2).
And executed by the instruction execution circuit 604.

In cycle t5 (1), the value x'1000 of the address register A0 and the deviation value x'0004 are respectively
5 and the B2 bus 16, the selector 23, and the selector 22 via the selector 22. In cycle t6 (2), the value x'1004 of the result of the addition is stored in the operand address register 25 via the arithmetic unit output buffer 24 and output to the data bus 606 as an address.
Data is read from the address 8'x'1004.

The read value x'3333 is held in the load buffer 27 at cycle t6 (1), and is stored in the data register D0 via the selector 20 at cycle t7 (2). (Instruction 8) The instruction 8 is the instruction decoding circuit 60 simultaneously with the instruction 7.
3 and are executed by the instruction execution circuit 604 in parallel. Strictly speaking, instruction 8 starts at cycle t6 (2) and ends at cycle t6 (2).
The processing is executed by the instruction execution circuit 604 up to 6 (1).

In cycle t6 (2), data register D
The value x'2222 of 0 and the value x'5555 of the data register D1 are multiplied by the multiplier 28 via the A bus 14 and the B2 bus 16, respectively. The value x'9f4a, the lower 16 bits of the product, is the cycle
The data is stored in the latch 32 at t6 (1). The sum output and carry output of the upper 16 bits of the product are added by the adder 29 via the selector 30 and the selector 31, respectively, and the value x'0b60 of the addition result is stored in the latch 33 in cycle t6 (1). Is done. (Instruction 9) The instruction 9 starts from cycle t6 (1) to cycle t8 (2).
And executed by the instruction execution circuit 604.

In cycle t6 (1), the value x'2000 of the address register A1 and the deviation value x'0004 are respectively
5 and the B2 bus 16, the selector 23, and the selector 22 via the selector 22. In cycle t7 (2), the value x'2004 of the result of the addition is stored in the operand address register 25 via the arithmetic unit output buffer 24 and output to the data bus 606 as an address.
The data is read from the address 8'x'2004.

The read value x'6666 is held in the load buffer 27 at cycle t7 (1), and is stored in the data register D1 via the selector 20 at cycle t8 (2). (Instruction 10) The instruction 10 is decoded by the instruction decoding circuit 603 at the same time as the instruction 9, and is executed by the instruction execution circuit 604 in parallel. Strictly speaking, the instruction 10 is executed by the instruction execution circuit 604 from a cycle t7 (2) to a cycle t8 (1).

In cycle t7 (2), the value x'0c84 of the product-sum lower-order register 35 and the value x'9f4a of the latch 32 are transferred via the A bus 14 and the B2 bus 16, and the selectors 22 and 23, respectively. The addition is performed by the adder 21. Cycle t7
In (1), the value x'abce of the addition result is output to the arithmetic unit output buffer 24.
, Is again stored in the product-sum lower-order register 35, and the value x′0b60 of the latch 33 is transferred to the latch 34. Further, in cycle t7 (1), the value x'0b60 held in the latch 34 and the value x'048d of the product-sum upper-order register 36 are added to the adder 2 via the selector 31 and the selector 30, respectively.
9 is added. At this time, the carry output from the most significant bit of the arithmetic unit 21 is added as a carry input to the least significant bit of the adder 29, and the value of the carry input is 0.

At cycle t8 (2), the value x'0fed of the addition result is stored again in the product-sum upper-order register 36 via the latch 33. Next, in cycle t8 (2), the value x'0000 of the product-sum carry accumulation register 37 selected by the selector 23 and the value x'0000 output by the selector 22 without selecting anything are determined by:
The arithmetic unit 21 adds the carry output from the most significant bit of the adder 29 as the carry input to the least significant bit. The value of the carry input is 0, and the value of the addition result x'00
00 is stored in the product-sum carry accumulation register 37 again in the cycle t8 (1) via the arithmetic unit output buffer 24.

As described above, the products are cumulatively added by the three addition operations, and the product-sum processing up to the second time is completed. (Instruction 11) (Description is omitted. The operation is indicated by the broken line in FIG. 11.) (Instruction 12) The instruction 12 is decoded by the instruction decoding circuit 603 at the same time as the instruction 10, and is executed by the instruction execution circuit 604 in parallel. Is done. Strictly, the instruction 12 is executed by the instruction execution circuit 604 from cycle t8 (2) to cycle t8 (1).

In cycle t8 (2), data register D
The value x'3333 of 0 and the value x'6666 of the data register D1 are multiplied by the multiplier 28 via the A bus 14 and the B2 bus 16, respectively. The value x'b852, the lower 16 bits of the product, is the cycle
The data is stored in the latch 32 at t8 (1). The sum output and carry output of the upper 16 bits of the product are added by the adder 29 via the selector 30 and the selector 31, respectively, and the value x'147a of the addition result is stored in the latch 33 at cycle t8 (1). Is done. (Instruction 13) (Description is omitted. The operation is indicated by the broken line in FIG. 11.) (Instruction 14) The instruction 14 is decoded by the instruction decoding circuit 603 at the same time as the instruction 13, and is executed by the instruction execution circuit 604 in parallel. Is done. Strictly, the instruction 14 is executed by the instruction execution circuit 604 from cycle t9 (2) to cycle t10 (1).

In cycle t 9 (2), the value x′abce of the product-sum lower-order register 35 and the value x′b852 of the latch 32 are transferred via the A bus 14 and the B 2 bus 16 and the selectors 22 and 23, respectively. The addition is performed by the adder 21. Cycle t9
In (1), the value x'6420 of the addition result is output to the arithmetic unit output buffer 24.
, Is again stored in the product-sum lower-order register 35, and the value x′147a of the latch 33 is transferred to the latch 34. Further, in the cycle t9 (1), the value x'147a held in the latch 34 and the value x'0fed of the product-sum upper-order register 36 are added to the adder 2 via the selector 31 and the selector 30, respectively.
9 is added. At this time, the carry output from the most significant bit of the arithmetic unit 21 is added as a carry input to the least significant bit of the adder 29, and the value of the carry input is 1.

In cycle t10 (2), the value x'2468 of the addition result is stored again in the product-sum upper-order register 36 via the latch 33. Next, in cycle t10 (2), the value x'0000 of the product-sum carry accumulation register 37 selected by the selector 23 and the value x'0000 output by the selector 22 without selecting anything are determined by:
The arithmetic unit 21 adds the carry output from the most significant bit of the adder 29 as the carry input to the least significant bit. The value of the carry input is 0, and the value of the addition result x'00
00 is stored in the product-sum carry accumulation register 37 again in the cycle t10 (1) via the arithmetic unit output buffer 24.

As described above, the products are cumulatively added by the three addition operations, and the product-sum processing up to the third time is completed. In addition,
The broken lines in FIGS. 11 and 12 indicate the operation of the instruction following the instruction 11, the instruction 13, and the instruction 14. In addition, the above 3
In the sum-of-products processing up to the first time, no carry was generated from the most significant bit at the time of addition of the sum-of-products upper digit register 36, but when the number of times of integration increases and a carry occurs, this is the sum-of-products carry accumulation register 37. Is accumulated in

As described above, the instruction execution circuit 604 executes the load instruction (MOV) and the multiplication instruction (MULA) simultaneously by the parallel operation of the arithmetic unit 21 and the multiplier 28, and executes the load instruction (MOV) and the cumulative addition. The instruction (ADDA) is simultaneously executed by the parallel operation of the arithmetic unit 21, the multiplier 28 and the adder 29.
As a result, the instruction reading circuit 602 that can read two instructions at the same time, the instruction decoding circuit 603 that detects instructions to be executed in parallel and controls the instruction execution circuit 604, and the processor 601 including the instruction execution circuit 604 have a product-sum operation. One process can be performed in two cycles.

As described above, the processor and the compiler according to the present invention have been described based on the embodiments. However, it goes without saying that the present invention is not limited to these embodiments. That is, (1) In the embodiment, the product sum 1 in the C language program
Compiler 102 translates the processing of this time into an instruction sequence consisting of a load instruction, a multiplication instruction, a load instruction, and an accumulative addition instruction. Processor 601 receives this instruction sequence, and executes the previous load instruction and multiplication instruction in parallel. Although the subsequent load instruction and the cumulative addition instruction are each decoded and executed in parallel, an instruction for executing the load and multiplication in parallel and an instruction for executing the load and the cumulative addition in parallel are defined. The same processing in the C language may be translated into an instruction sequence composed of these two instructions, and the processor 601 may receive this instruction sequence and decode and execute each of them independently. (2) In the embodiment, everything from the address register file 17 to the product-sum carry accumulation register 37 has a 16-bit width. However, all may have an 8-bit width or all may have a 32-bit width. (3) In the embodiment, the product-sum carry accumulation register 37 is provided to accumulate the carry at the time of accumulative addition of the product, and to keep the 48-bit sum for the 32-bit product. Alternatively, the sum may be kept only 32 bits.
In this case, one addition operation is achieved by two addition operations. Therefore, the present embodiment in which the arithmetic unit 21, the adder 29, and the arithmetic unit 21 are operated again is
And the adder 29 may be operated once each, or the arithmetic unit 21 may be operated twice. In particular, in the latter case, the operation of the adder 29 is limited to only the time of multiplication, so that the selector 30 and the selector 31 become unnecessary. (4) In the embodiment, the multiplier 28 and the adder 29 are provided inside the instruction execution circuit 604 of the processor 601. However, the instruction execution circuit 604 deletes a portion surrounded by a broken line in FIG. May be provided as an extended arithmetic unit so that the instruction execution circuit 604 is extended only when necessary. This makes it possible to provide a general-purpose processor that does not require an extended arithmetic unit and has a low hardware cost for applications that do not require a product-sum operation, and provide a processor that has an extended arithmetic unit added to an application that requires a product-sum operation. In addition, in applications that require the product-sum operation, access to the data used for the product-sum operation is as follows:
This is realized by a single access means of the arithmetic unit 21, the data bus 606, and the address register file 17, and the extended arithmetic unit and the instruction execution circuit 604 operate in parallel. Hardware costs required for adding an arithmetic unit can be minimized.

[0072]

As is apparent from the above description, the processor according to the present invention calculates the product of the array element of the first array data and the array element of the second array data stored in the storage area in each array. A processor for obtaining and adding cumulatively for each element, an instruction reading means for reading an instruction from a program memory, and decoding a predetermined first extended instruction and a second extended instruction read by the instruction reading means. Instruction decoding means, first to fourth registers, data loading means for loading array elements of the first and second array data into the first and second registers, respectively, and the first and second registers. Multiplying means for obtaining the product of the contents of the registers and storing the result in the third register, and obtaining the sum of the contents of the third register and the contents of the fourth register and storing the sum in the fourth register again Addition Means for executing the multiplication means when the first extension instruction is decoded by the instruction decoding means, and causing the data load means to newly load an array element of the first array data. 1 execution control means, and executing the adding means in parallel with loading the array element of the second array data into the data loading means when the second extended instruction is decoded by the instruction decoding means. And an instruction execution means comprising a second execution control means for causing the instruction to be executed.

According to this, the processor according to the present invention executes the data load means for loading data into the first register and the execution of the data load means to load data into the second register. Since the first execution control means and the second execution control means are separately controlled and the data loading to the first and second registers is not performed simultaneously, the data loading means includes Since only one system is required for obtaining the address for accessing the area and for accessing the storage area, the hardware cost is reduced as compared with the case of using the dedicated product-sum operation circuit shown in the second prior art. Can be kept low.

Also, in the processor according to the present invention, the first execution control means makes the data load means and the multiplication means parallel, and the second execution control means makes the data load means and the addition means Are performed in parallel, so that the product-sum operation can be performed at a higher speed than in the case of using the general-purpose processor described in the first related art.

In the processor according to the present invention, the instruction decoding means includes: a first load instruction for loading an array element of first array data from the storage area into the first register; An instruction in which a multiplication instruction for obtaining a product of the contents of the first register and the contents of the second register before storing the result of the instruction and storing the product in the third register is sequentially executed. Decode in parallel and read the array element of the second array data from the storage area to the second
A second load instruction for loading the register of
And a parallel decoding means for obtaining the sum of the contents of the fourth register and the contents of the fourth register, and decoding in parallel an instruction in which a cumulative addition instruction to be stored again in the fourth register is arranged in parallel. Can also.

Here, the first extended instruction includes a first load instruction for loading an array element of first array data from the storage area into the first register, and a result of the first load instruction. Is obtained by multiplying the contents of the first register and the contents of the second register before the third register is stored.
And the multiplication instruction stored in the second register is a second instruction for loading an array element of second array data from the storage area into the second register. And a cumulative addition instruction for obtaining the sum of the contents of the third register and the contents of the fourth register and storing the sum again in the fourth register.

Thus, it is not necessary to define the first and second extended instructions as separate instructions only for the product-sum operation, and the processor reads and decodes only general instructions, thereby enabling the processor to multiply at high speed. A sum operation can be performed. Further, the multiplication instruction implicitly includes information designating the third register, the cumulative addition instruction implicitly includes information designating the third register and the fourth register, The third register and the fourth register of the processor according to the present invention may be dedicated registers.

Thus, since the multiplication means and the addition means exchange data with the dedicated register, the circuit configuration can be simplified, and the hardware cost can be reduced. Further, the multiplying means of the processor according to the present invention includes a plurality of carry save adders connected in a tree, and a carry propagation adder for adding the sum output and the carry output of the last stage of the tree. The adding means may use the carry propagation adder to obtain the sum.

Thus, the adding means can replace one of a plurality of adders used for addition with one another.
Since the carry propagation adder constituting the multiplying means can be shared with the multiplying means, the hardware cost can be reduced. Further, the processor according to the present invention performs a sum-of-products operation in which a product of an array element of the first array data and an array element of the second array data stored in the storage area is obtained for each array element and cumulatively added. A main processor that operates in response to the same clock pulse and processes data in accordance with an instruction in a program memory, and a secondary extended operation device, wherein the main processor executes an instruction to read an instruction from the program memory. Said instruction execution means comprising: a read means; an instruction decoding means for decoding an instruction read by said instruction read means; and an instruction execution means for executing an instruction in accordance with a result of decoding by said instruction decoding means. Comprises an instruction execution control means and an adder, wherein the secondary extended operation device comprises a multiplier, and the main processor and the secondary extended operation device are provided. Is connected by a first bus for transmitting data from the instruction execution means to the multiplier and a second bus for transmitting the multiplication result of the multiplier to the instruction execution means, wherein the instruction execution control means comprises: When the instruction of the product-sum operation is decoded by the instruction decoding means, an address calculation for accessing an array element of the first array data using the adder and an array element of the second array data are performed. And performing the accumulative addition to access the data, and in parallel with this, causing the subordinate extended arithmetic unit to perform the multiplication using the multiplier.

As a result, the main processor and the sub-processor can perform parallel processing independently of each other, so that the utilization efficiency of hardware can be increased and the processing capability with respect to hardware cost can be increased. The compiler according to the present invention is a compiler that generates a machine instruction program for a processor including first to fourth registers, a multiplier, and an adder from a high-level language program, wherein the high-level language program includes Detecting means for obtaining a product of the array element of the first array data and the array element of the second array data for each array element and detecting a code for accumulative addition; and when the code is detected, In parallel with obtaining the product of the content of the first register and the content of the second register and storing the product in the third register, the array element of the first array data is newly stored in the storage area in parallel with the first A first extension instruction for loading into the first register, and loading an array element of the second array data from the storage area into the second register in parallel with the first register. Machine instruction generating means for generating a machine instruction program in which a second extended instruction for obtaining the sum of the contents and the contents of the fourth register and storing the sum again in the fourth register is provided. It is characterized by.

The first extended instruction includes a first load instruction for loading an array element of first array data from the storage area into the first register, and a result of the first load instruction. A multiplication instruction for obtaining a product of the contents of the first register and the contents of the second register before being stored and storing the product in the third register, wherein A second load instruction for loading an array element of second array data from the storage area into the second register; a content of the third register and a content of the fourth register; And the fourth
And the cumulative addition instruction stored in the register No. 1 may be an instruction arranged continuously.

Thus, the above-mentioned first to fourth registers, multipliers and adders are provided, and a function of executing data loading and multiplication in parallel and executing data loading and cumulative addition in parallel is provided. A machine instruction program suitable for the processor having the program is generated. Therefore, the processor reads, decodes, and executes the machine instruction program generated by the compiler, thereby realizing high-speed product-sum operation processing.

Further, the machine instruction generating means may include
Loading the first array element from the storage area corresponding to the first array element of the first array data into the first register before the repetition of the first extended instruction and the second extended instruction A first prefix load instruction and a second prefix load instruction for loading an array element from the storage area corresponding to the first array element of the second array data into the second register are added. Can also be generated.

Thus, in the high-level language program, a code for obtaining the product of the array element of the first array data and the array element of the second array data for each array element and performing cumulative addition is described. The first
And a machine instruction program for executing a product-sum operation for the first array element of the second array data.

Further, the multiplication instruction generated by the compiler according to the present invention may implicitly include information designating the third register. Thereby, the size of the instruction code of the multiplication instruction can be reduced. Further, the cumulative addition instruction generated by the compiler according to the present invention may implicitly include information designating the third register and the fourth register.

Thus, the size of the instruction code of the cumulative addition instruction can be reduced. Also,
A method for multiplying and accumulating data according to the present invention uses a processor having first to fourth registers, a multiplier and an adder, using an array element of first array data and a second array data stored in a storage area. A product-sum operation method for obtaining a product of each of the array elements for each array element and accumulatively adding the product, wherein a first data loading step of loading an array element of the first array data into the first register; Calculating the product of the contents of the first register and the contents of the second register before the array elements of the first array data are loaded into the first register by the first data loading step. A second data loading step of loading an array element of the second array data into the second register in parallel with the multiplying step of storing the data in the third register; The fourth record And repeating to parallel and an addition step of storing again calculates the sum of the contents of static in the fourth register.

Thus, the processor can execute the data loading step and the multiplication step in parallel and the data loading step and the addition step in parallel, thereby executing the product-sum operation at low cost and at high speed. be able to. In addition, the recording medium according to the present invention includes an array element of first array data and a second array data stored in a storage area using a processor including first to fourth registers, a multiplier, and an adder. A product-sum operation program for calculating a product with each array element for each array element and accumulatively adding the product, wherein the product-sum operation program stores the array element of the first array data in the first array data. A first data loading step of loading the first register data into the first register, and contents of the first register before the array elements of the first array data are loaded into the first register by the first data loading step. Loading a first extension instruction in parallel with a multiplication step of obtaining a product of the contents of the second register and storing the product in the third register, and loading an array element of the second array data into the second register You A second extended instruction that performs a second data load step and an addition step of obtaining the sum of the contents of the third register and the contents of the fourth register and storing the sum again in the fourth register is executed by a second extended instruction. A product-sum calculation program characterized by being repeated is recorded.

Thus, the processor can execute the data loading step and the multiplication step in parallel and the data loading step and the addition step in parallel, thereby executing the product-sum operation at low cost and at high speed. be able to. As described above, the processor, the compiler, the product-sum operation method, and the recording medium according to the present invention are techniques for processing the product-sum operation at a low hardware cost and at a high speed, and thus the product-sum operation is frequently used. It is very useful in the development of multimedia related products, and greatly contributes to the advancement and development of the multimedia related industry.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a compiler according to an embodiment.

FIG. 2 is a flowchart showing a processing flow of a syntax analysis unit according to the embodiment.

FIG. 3 is a flowchart showing a processing flow of a machine instruction generation unit according to the embodiment.

FIG. 4 is a diagram showing a C language program for performing a product-sum operation.

FIG. 5 is a list showing machine instruction programs generated by the compiler according to the embodiment when the C language program shown in FIG. 4 is given as an input.

FIG. 6 is a schematic configuration diagram of a processor according to the same embodiment.

FIG. 7 is a processing timing chart showing processing timings of an instruction reading circuit, an instruction decoding circuit, and an instruction execution circuit according to the same embodiment.

FIG. 8 is a block diagram showing a configuration of an instruction execution circuit according to the same embodiment.

9 is an explanatory diagram of the contents of a data memory storing data accessed by the machine instruction program of FIG. 5;

10 is an operation timing chart of the instruction execution circuit corresponding to the machine instruction program of FIG. 5 in cycles t1 to t4.

11 is an operation timing chart of an instruction execution circuit corresponding to the machine instruction program of FIG. 5 in cycles t5 to t8.

12 is an operation timing chart of the instruction execution circuit corresponding to the machine instruction program of FIG. 5 in cycles t9 to t10.

FIG. 13 is a program list as a result of translating a C language program into a machine instruction program by a conventional compiler.

FIG. 14 is a block diagram showing a configuration of a conventional dedicated product-sum operation circuit added to a general-purpose processor.

[Explanation of symbols]

 14 A bus (ABUS) 15 B1 bus (B1BUS) 16 B2 bus (B2BUS) 17 Address register file (ARF) 18 Data register file (DRF) 21 Operation unit (ALU) 24 Operation unit output buffer (ALOB) 25 Operand address buffer (OAB) 26 Store buffer (STB) 27 Load buffer (LDB) 28 Multiplier (MPY) 29 Adder (CPA) 32 Latch (PRL) 33 Latch (PRH1) 34 Latch (PRH2) 35 Multiply-accumulate lower digit register (ACCL) ) 36 Multiply-accumulate upper digit register (ACCH) 37 Multiply-add carry register (ACCC) 101 C language program 102 Compiler 103 File reading unit 104 Reading buffer 105 Syntax analysis unit 106 Intermediate code buffer 107 Machine instruction generation unit 108 Output Buffer 109 File output unit 110 Machine instruction program 601 Pro Sessor 602 Instruction reading circuit 603 Instruction decoding circuit 604 Instruction execution circuit 605 Instruction bus 606 Data bus 607 Program memory 608 Data memory

Claims (12)

[Claims] 1. A processor for obtaining a product of an array element of a first array data and an array element of a second array data stored in a storage area for each array element and accumulatively adding the product. An instruction reading means for reading an instruction; an instruction decoding means for decoding a predetermined first extended instruction and a second extended instruction read by the instruction reading means; a first to a fourth register; Data loading means for loading array elements of the first and second array data into the first and second registers, respectively; obtaining a product of the contents of the first and second registers and storing the product in the third register Multiplying means, adder means for obtaining the sum of the contents of the third register and the contents of the fourth register, and storing the sum again in the fourth register; A first execution control unit for causing the data loading unit to newly load an array element of the first array data in parallel with executing the multiplication unit when the instruction is read; And a second execution control means for executing the addition means in parallel with loading the array elements of the second array data into the data loading means when the extended instruction is decoded. A processor comprising: 2. The first extended instruction includes a first load instruction for loading an array element of first array data from the storage area into the first register, and a result of the first load instruction. A multiplication instruction for obtaining a product of the contents of the first register and the contents of the second register before being stored and storing the product in the third register, wherein The second extended instruction loads an array element of second array data from the storage area into the second register.
Load instruction, the contents of the third register and the fourth
And an accumulative addition instruction for obtaining the sum of the contents of the register and storing the sum again in the fourth register. The instruction decoding means reads the array of the first array data from the storage area. A first load instruction for loading an element into the first register, and the product of the contents of the first register and the contents of the second register before the result of the first load instruction is stored And multiply instructions to be stored in the third register and decode instructions arranged in parallel in parallel,
A second load instruction for loading an array element of the second array data from the storage area into the second register; and a sum of the contents of the third register and the contents of the fourth register. 2. The processor according to claim 1, further comprising parallel decoding means for decoding, in parallel, an instruction in which the cumulative addition instruction stored in the fourth register is arranged consecutively. 3. The multiplication instruction implicitly includes information designating the third register, and the cumulative addition instruction implicitly includes information designating the third register and the fourth register. 3. The processor of claim 2, wherein the third register and the fourth register are dedicated registers. 4. The multiplying means comprises a plurality of carry save adders connected in a tree, and a carry propagation adder for adding a sum output and a carry output of the last stage of the tree. 4. The processor according to claim 3, wherein the means uses the carry propagation adder to determine the sum. 5. A processor for executing a sum-of-products operation for obtaining a product of an array element of the first array data and an array element of the second array data placed in a storage area for each array element and cumulatively adding the product. A main processor that operates in response to the same clock pulse and processes data in accordance with an instruction in a program memory; and a subordinate extended arithmetic unit, wherein the main processor reads instruction from the program memory, An instruction decoding unit that decodes the instruction read by the instruction reading unit; and an instruction execution unit that executes the instruction in accordance with the result of the decoding by the instruction decoding unit. Comprising a control means and an adder, wherein the secondary extended arithmetic unit comprises a multiplier, and wherein the main processor and the secondary extended arithmetic unit are
A first bus configured to transmit data from the instruction execution unit to the multiplier and a second bus configured to transmit a multiplication result of the multiplier to the instruction execution unit; When the instruction of the product-sum operation is decoded by the means, the adder is used to calculate an address for accessing an array element of the first array data and to access an array element of the second array data. For performing the address calculation and the accumulative addition for the above, and in parallel with this, causing the subordinate extended arithmetic unit to perform the multiplication using the multiplier. 6. A compiler for generating, from a high-level language program, a machine instruction program for a processor including first to fourth registers, a multiplier, and an adder, wherein a first array is included in the high-level language program. Detecting means for obtaining a product of the array element of data and the array element of the second array data for each array element and detecting a code for accumulative addition; and detecting the first code when the code is detected. In parallel with obtaining the product of the contents of the register and the contents of the second register and storing the product in the third register, an array element of the first array data is newly stored in the first register from a storage area. A first extension instruction for loading and an array element of the second array data from a storage area are loaded into the second register in parallel with the contents of the third register and the fourth register. The fourth again sought the sum of the contents of the static
And a machine instruction generating means for generating a machine instruction program in which a second extended instruction is stored in the register. 7. The first extended instruction includes: a first load instruction for loading an array element of first array data from the storage area into the first register; and a result of the first load instruction. A multiplication instruction for obtaining a product of the contents of the first register and the contents of the second register before being stored and storing the product in the third register, wherein The second extended instruction loads an array element of second array data from the storage area into the second register.
Load instruction, the contents of the third register and the fourth
7. The compiler according to claim 6, wherein the accumulative addition instruction for obtaining the sum of the contents of the second register and storing the sum again in the fourth register is an instruction arranged consecutively. 8. A storage area corresponding to a first array element of the first array data before the repetition of the first extension instruction and the second extension instruction. A first pre-load instruction for loading the first array element from the first array element into the first register; and storing the array element from the storage area corresponding to the first array element of the second array data in the second array data. 8. The compiler according to claim 7, further comprising: generating a second preload instruction to be loaded into a register. 9. The compiler according to claim 8, wherein the multiplication instruction implicitly includes information designating the third register. 10. The compiler according to claim 9, wherein the cumulative addition instruction implicitly includes information designating the third register and the fourth register. 11. Using a processor having first to fourth registers, a multiplier, and an adder, an array element of a first array data and an array element of a second array data stored in a storage area. A product-sum operation method for obtaining a product for each array element and accumulating and adding, wherein a first data loading step of loading an array element of the first array data into the first register; Calculating a product of the contents of the first register and the contents of the second register before the array elements of the first array data are loaded into the first register by the data loading step; A second data loading step of loading an array element of the second array data into the second register; a multiplication step of loading the array element of the second array data into the second register; Inside Product-sum operation method and repeating to parallel and an addition step of storing again the fourth register obtains the sum of the. 12. An array element of a first array data and an array element of a second array data stored in a storage area using a processor having first to fourth registers, a multiplier, and an adder. A storage medium describing a product-sum operation program for obtaining a product for each array element and performing cumulative addition, wherein the product-sum operation program loads an array element of the first array data into the first register. A first data loading step, and the contents of the first register and the contents of the second register before the array elements of the first array data are loaded into the first register by the first data loading step. A first extension instruction in parallel with a multiplication step of obtaining a product of the contents and storing the product in the third register; and a second data for loading an array element of the second array data into the second register. A second extension instruction is executed in parallel with the loading step and the adding step of obtaining the sum of the contents of the third register and the contents of the fourth register and storing the sum again in the fourth register. A recording medium on which a product-sum operation program is recorded.