JPH117335A - Semiconductor integrated circuit and system, and method for reducing skew between clock signal and data signal - Google Patents

Abstract

(57) [Summary] To reduce skew between a clock signal and a data signal. A slave (20) receives a phase difference reduction circuit (22) for reducing a phase difference between a clock signal (CLK) and a data signal (Data), and a data signal (Data ') with a reduced phase difference between the clock signal (CLK) and the clock signal (CLK). And a circuit 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit and system capable of reducing a phase difference between a clock signal and a data signal, and a method for reducing a skew between a clock signal and a data signal. .

[0002]

2. Description of the Related Art With the spread of multimedia, it has been recommended to speed up a system centered on a personal computer. In such a situation, a semiconductor device occupies a particularly large place, and it has been a long time since the speeding up of the semiconductor device has been called for.

In a system constituted by a plurality of semiconductor devices, it is necessary to transfer signals between the devices.
In order to perform faster transfer operations, recent transfer methods are:
Synchronous systems have become known in which other signals are synchronized with a reference signal that repeats transitions in a certain period called a clock signal.

FIG. 23A shows a configuration of a conventional synchronization system. The buffer 703a of the transmitting chip 705 outputs the data signal Data. The buffer 703 b of the receiving chip 704 receives the data signal Data and outputs it to the holding circuit 701. The holding circuit 701 holds the data signal Data in synchronization with the reference clock signal SysCLK, and transfers it to the internal circuit 702.

[0005]

In such a synchronous system, it is common practice to increase the frequency of the reference clock signal in order to perform a higher-speed operation. However, there is a timing shift (ie, skew) between the reference clock signal and another signal (for example, a data signal). This skew causes a malfunction of the holding circuit. FIG. 23B shows the reference clock signal SysCL.
A shift in the phase of K from the phase of the data signal Data causes a mislatch, which indicates that the holding circuit malfunctions.

FIGS. 24A to 24C show that the phase shift T does not matter when the frequency of the reference clock signal is low, but the phase shift T becomes problematic as the frequency of the reference clock signal increases. Is shown.

FIG. 24A shows a reference clock signal SysCL.
The case where the phase of K completely matches the phase of the data signal is shown.

FIG. 24B shows a reference clock signal SysCL.
When the frequency of K is low, the reference clock signal SysCL
A case where a phase shift T occurs between the phase of K and the phase of the data signal is shown. In this case, there is no particular problem since correct data is output.

FIG. 24C shows a case where a phase shift T occurs between the phase of the reference clock signal SysCLK and the phase of the data signal when the frequency of the reference clock signal is high. In this case, a problem occurs because correct data is not output. As described above, the influence of the phase shift becomes more serious as each signal operates at a higher speed, which is an obstacle to the high-speed operation of the system.

Conventionally, as a method for minimizing the phase shift, a method has been adopted in which a transfer path for a reference clock signal and a transfer path for a data signal are arranged as close as possible. However, this method has a drawback that it imposes restrictions on the layout of signal wiring and a drawback that it cannot cope with a phase shift due to power supply fluctuation or temperature fluctuation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in consideration of the above-described problems, and provides a semiconductor integrated circuit and a system capable of reducing a phase difference between a clock signal and a data signal. It is an object to provide a method for reducing the skew between them.

[0012]

According to the present invention, there is provided a semiconductor integrated circuit comprising: a phase difference reducing circuit for reducing a first phase difference between a clock signal and a data signal; And a circuit for receiving the data signal in which the phase difference is reduced, whereby the above object is achieved.

The phase difference reducing circuit includes: a delay amount determining circuit for determining a first delay amount so that a second phase difference between the clock signal and the dummy pattern signal is reduced; A variable delay circuit for delaying one of the clock signal and the data signal according to a delay amount may be provided.

The delay amount determining circuit further determines a second delay amount such that the first phase difference between the clock signal and the data signal is reduced. One of the clock signal and the data signal may be delayed according to a second delay amount.

[0015] The dummy pattern signal may be a signal that changes at least once from a first logic level to a second logic level.

The data signal is inputted to the phase difference reducing circuit via a data line, and the dummy pattern signal is outputted through the data line before the data signal is inputted to the phase difference reducing circuit. It may be input to a phase difference reduction circuit.

A system according to the present invention includes a first semiconductor integrated circuit and a second semiconductor integrated circuit, wherein the first semiconductor integrated circuit outputs a data signal to the second semiconductor integrated circuit. And a second semiconductor integrated circuit that receives the data signal output from the first semiconductor integrated circuit and reduces a first phase difference between a clock signal and the data signal. And a circuit for receiving the data signal with the first phase difference between the clock signal and the clock signal reduced. This allows
The above object is achieved.

The phase difference reducing circuit includes: a delay amount determining circuit for determining a first delay amount so that a second phase difference between the clock signal and the dummy pattern signal is reduced; A variable delay circuit for delaying one of the clock signal and the data signal according to a delay amount may be provided.

The delay amount determining circuit further determines a second delay amount such that the first phase difference between the clock signal and the data signal is reduced, and the variable delay circuit includes One of the clock signal and the data signal may be delayed according to a second delay amount.

[0020] The dummy pattern signal may be a signal that changes at least once from a first logic level to a second logic level.

The first semiconductor integrated circuit and the second semiconductor integrated circuit are connected to each other via a data line,
The data signal is transferred from the first semiconductor integrated circuit to the second semiconductor integrated circuit via the data line, and the dummy pattern signal is obtained by converting the data signal from the first semiconductor integrated circuit to the second semiconductor integrated circuit. Before being transferred to the circuit, the data may be transferred from the first semiconductor integrated circuit to the second semiconductor integrated circuit via the data line.

The method of the present invention is a method for reducing skew between a clock signal and a data signal, comprising: (a) reducing a first phase difference between the clock signal and the data signal; (B) receiving the data signal in which the first phase difference between the clock signal and the clock signal is reduced, whereby the object is achieved.

The step (a) comprises: (a-1) determining a first delay amount such that a second phase difference between the clock signal and the dummy pattern signal is reduced; -2) delaying one of the clock signal and the data signal according to the first delay amount.

The step (a) includes: (a-3) further determining a second delay amount such that the first phase difference between the clock signal and the data signal is reduced; (A-4) delaying one of the clock signal and the data signal according to the second delay amount.

[0025] The dummy pattern signal may be a signal that changes at least once from a first logic level to a second logic level.

Another method of the present invention is a method for reducing a skew between a clock signal and a data signal in a semiconductor integrated circuit connected to a data line, wherein:
Receiving the dummy pattern signal via the data line during the period, (b) receiving the data signal via the data line during the second period, and (c) receiving the clock signal and the dummy signal. Reducing the phase difference between the clock signal and the data signal based on the phase difference between the pattern signal and the data signal, thereby achieving the above object.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 shows the configuration of a system 1 according to Embodiment 1 of the present invention. The system 1 includes a clock signal CL
It includes a clock signal generator 10 that generates K, a slave 20 that operates according to the clock signal CLK, and a master 30 that operates according to the clock signal CLK and outputs the data signal Data to the slave 20. Each of master 30 and slave 20 may be a semiconductor integrated circuit.

In this specification, signals transferred between different circuits are collectively referred to as "data signal Data". "Data signal Data" includes an arbitrary signal transferred between master 30 and slave 20.

The clock signal CLK is supplied to the clock signal line 1
0a is supplied to the slave 20. Data signal D
The data “ata” is supplied to the slave 20 via the data signal line 10b. As described above, the clock signal CLK and the data signal Data pass through different paths via the slave 20.
Supplied to Therefore, there is a skew between the clock signal CLK and the data signal Data (that is, the difference between the phase of the clock signal CLK and the phase of the data signal Data).
Can occur. Further, the value of the skew is indeterminate due to a power supply voltage fluctuation, a temperature fluctuation, a process fluctuation, and the like.

The phase difference reducing circuit 22 is provided in the slave 20 in order to reduce the skew caused by the above-described cause. The phase difference reducing circuit 22 outputs the clock signal C
The phase difference between LK and data signal Data is reduced. The data signal Data whose phase difference has been reduced by the phase difference reducing circuit 22 is supplied to the internal circuit 24 as a data signal Data '. The internal circuit 24 outputs the data signal Da
ta ′ and processes the data signal Data ′.
The internal circuit 24 can be any circuit that performs processing on the data signal Data '.

Preferably, phase difference reducing circuit 22 makes the phase difference between clock signal CLK and data signal Data substantially zero. Thus, regardless of the path on which the clock signal CLK and the data signal Data are supplied, the data signal Dat synchronized with the clock signal CLK is provided.
a ′ can be obtained.

The master 30 receives the dummy pattern signal Dum
and an output circuit 32 for selectively outputting my and data signal Data to data signal line 10b. Output circuit 32
Is a dummy pattern signal Dum during the initialization period.
My is output to the data signal line 10b, and during the operation / transfer period, the data signal Data is output to the data signal line 10b. Note that the initialization period is provided prior to the operation / transfer period. In this way, the dummy pattern signal Dummy is input to the slave 20 via the data signal line 10b during the initialization period, and the data signal Dummy via the data signal line 10b during the operation / transfer period.
data is input to the slave 20.

Here, "Dummy pattern signal Dumm"
"y" refers to a signal whose logic level changes at least once during the initialization period. That is, the dummy pattern signal Dummy changes from the H level to the L level or from the L level to the H level during the initialization period.

The dummy pattern signal Dummy is used to determine a delay amount corresponding to a phase difference between the clock signal CLK and the data signal Data, as described later. In order to determine the delay amount, the dummy pattern signal Dummy needs to have at least one edge (rising edge or falling edge) in the initialization period. This is because it is necessary to determine the delay amount so that the edge of the clock signal CLK matches the edge of the dummy pattern signal Dummy. Preferably, the dummy pattern signal Dum
my is a clock signal having the same cycle as the clock signal CLK.

FIG. 2 shows the configuration of the output circuit 32.

The output circuit 32 outputs a dummy pattern signal Du.
a dummy pattern signal generator 32a for generating mmy;
Data signal generator 32b for generating data signal Data
And a selector 32c for selecting one of the output of the dummy pattern signal generator 32a and the output of the data signal generator 32b. During the initialization period, the output of the dummy pattern signal generator 32a is selected by the selector 32c. As a result, the dummy pattern signal Dummy is output to the data signal line 10b. During the operation / transfer period, the output of the data signal generator 32b is selected by the selector 32c. As a result, data signal Data is output to data signal line 10b.

The switching of the selector 32c is performed according to a control signal Mode1 for defining an initialization period or a control signal Mode2 for defining an operation / transfer period.
These control signals may be generated inside the output circuit 32 or may be generated outside the output circuit 32.

When a clock signal having the same cycle as the clock signal CLK is used as the dummy pattern signal Dummy, the dummy pattern signal generator 32
a is unnecessary. In this case, the clock signal generator 1
The clock signal CLK supplied from 0 may be input to the selector 32c.

FIG. 3 shows the configuration of the phase difference reducing circuit 22.

The phase difference reducing circuit 22 outputs the clock signal CL
Delay amount determining circuit 22 that determines delay amount D such that the phase difference between K and dummy pattern signal Dummy is reduced.
a and a variable delay circuit 22b capable of setting a delay amount D. For example, when the variable delay circuit 22b has a configuration in which a plurality of delay elements are connected in series, the number of delay elements through which a signal passes among the plurality of delay elements is variably set according to the delay amount D. By doing so, it is possible to set a desired delay amount in the variable delay circuit 22b.

In the initialization period, the delay amount determining circuit 22a determines the delay amount D. The delay amount D is determined so that the phase difference between the clock signal CLK and the dummy pattern signal Dummy is reduced. For example, the edge of the clock signal CLK and the dummy pattern signal Dumm
The delay amount D is determined so that the edges are compared with the edges of y. The delay amount D determined by the delay amount determining circuit 22a is set in the variable delay circuit 22b.

In the operation / transfer period, the data signal Data is delayed according to the delay amount D set in the variable delay circuit 22b during the initialization period. The phase difference reducing circuit 22 converts the delayed data signal Data into the data signal D.
Output to the internal circuit 24 as “ata ′”. Internal circuit 24
Operate according to the clock signal CLK. For example, the internal circuit 24 takes in the data signal Data 'in response to the edge of the clock signal CLK. Thus, the phase difference between clock signal CLK and data signal Data 'can be reduced more than the phase difference between clock signal CLK and data signal Data.

The same effect can be obtained by delaying clock signal CLK according to delay amount D instead of data signal Data. In this case, the phase difference reducing circuit 22 outputs the data signal Data to the internal circuit 24, and outputs the delayed clock signal CLK to the clock signal C
LK 'is output to the internal circuit 24. Internal circuit 24
Operate according to the clock signal CLK ′. For example,
The internal circuit 24 takes in the data signal Data in response to the edge of the clock signal CLK '. In this way,
The clock signal CLK ′ and the data signal Data are more than the phase difference between the clock signal CLK and the data signal Data.
Can be reduced. When the clock signal CLK is delayed according to the delay amount D, it is not necessary to supply the clock signal CLK to the internal circuit 24.

As described above, before the data signal Data is transferred from the master 30 to the slave 20, the delay amount D is previously set in the variable delay circuit 22b, so that the phase difference between the clock signal CLK and the data signal Data is increased. Can be reduced. Since the dummy pattern signal Dummy and the data signal Data are transferred from the master 30 to the slave 20 via the same data signal line 10b, the phase difference between the clock signal CLK and the data signal Data, and the clock signal CLK Dummy pattern signal Dumm
This is because the phase difference with y is substantially equal.

Preferably, the delay amount D is equal to the clock signal C
The phase difference between LK and the dummy pattern signal Dummy is determined to be substantially zero. In this case,
The phase difference between the clock signal CLK and the data signal Data can be made substantially zero.

It should be noted that even if the phase difference between the clock signal CLK and the dummy pattern signal Dummy is made substantially zero during the initialization period, the clock signal CLK and the data signal Data are not generated during the operation / transfer period.
May not be substantially zero. Therefore, the clock signal CLK and the data signal Data
It is preferable to determine the delay amount D ′ during the operation / transfer period so as to reduce the phase difference between the variable delay circuit 22b and the delay amount D ′ during the operation / transfer period. In order to determine the delay amount D ′, the data signal Data needs to have at least one edge (rising edge or falling edge) in the operation / transfer period. This is because it is necessary to determine the delay amount D ′ such that the edge of the clock signal CLK matches the edge of the data signal Data. The data signal Data delayed according to the delay amount D ′ is output from the phase difference reduction circuit 22 as the data signal Data ′. In this manner, the clock signal CLK and the data signal Dat are compared with the phase difference between the clock signal CLK and the data signal Data.
a ′ can be reduced. Note that a similar effect can be obtained by delaying the clock signal CLK according to the delay amount D 'instead of the data signal Data.

FIG. 4A shows that during the initialization period,
FIG. 7 shows a state in which the clock signal CLK and the dummy pattern signal Dummy are synchronized. In this example, the dummy pattern signal Dummy is a clock signal having the same cycle as the clock signal CLK. In the first cycle of the initialization period, the rising edge of the clock signal CLK does not coincide with the rising edge of the dummy pattern signal Dummy. In several cycles after the initialization period, it can be seen that the rising edge of the clock signal CLK and the rising edge of the dummy pattern signal Dummy gradually match.

The edge used to synchronize the clock signal CLK with the dummy pattern signal Dummy is not limited to the rising edge. A falling edge may be used to synchronize the clock signal CLK with the dummy pattern signal Dummy. Alternatively, both rising and falling edges may be used.

FIG. 4B shows how the clock signal CLK and the data signal Data are synchronized during the operation / transfer period. When the phase difference α between the clock signal CLK and the data signal Data is detected, the phase difference α is adjusted in a cycle next to the cycle in which the phase difference α is detected.

According to the present invention, the phase shift between the clock signal and the data signal can be minimized even when the transfer path for the clock signal and the transfer path for the data signal are not arranged close to each other. Further, according to the present invention, it is possible to cope with a phase shift due to power supply fluctuation or temperature fluctuation which cannot be dealt with by the conventional method of arranging the transfer path of the clock signal and the transfer path of the data signal in close proximity. Can be.

In the present invention, it is preferable that the clock signal transfer path and the data signal transfer path are arranged close to each other. This is to minimize the phase shift based on the difference in the length of the transfer path.

Hereinafter, an example in which the present invention is applied to a memory system will be described.

FIG. 5A shows the configuration of the memory system 100. The memory system 100 includes a clock signal generator 110 that generates a clock signal CLK, and a clock signal C.
LK, and a clock signal C
It includes a memory controller 130 that operates according to LK and a processor 140 that operates according to a clock signal CLK. The clock signal generator 110, the memory 120, the memory controller 130, and the processor 140 can be formed on a single semiconductor chip. Alternatively, they
They may be formed on different semiconductor chips.

The processor 140 comprises: an output circuit 142 for selectively outputting the dummy pattern signal Dummy and the data signal Data to the data signal line 110b;
0 is output from the data signal line 110.
d, the clock signal CLK and the output signal Out
And a synchronizing circuit 144 for synchronizing with. Output circuit 14
2 and the synchronization circuit 144 are connected to the clock signal C
It operates according to LK.

Here, the data signal Data includes a control signal, an address signal, and a signal indicating data to be written to the memory 120. The control signal is, for example, RAS,
CAS, read / write control signal, and the like.

The dummy pattern signal Dummy and the data signal Data are transferred to the memory 120 via the memory controller 130. The output signal Out is transferred to the processor 140 via the memory controller 130.

The memory 120 includes a synchronization circuit 122 for synchronizing the clock signal CLK and the data signal Data, a memory core 124, and an output for selectively outputting the dummy pattern signal Dummy and the output signal Out to the data signal line 110d. Circuit 126 is included. The clock signal CLK is supplied to the synchronization circuit 122 and the output circuit 126.

Memory core 124 includes a plurality of memory cells (not shown) and a peripheral circuit (not shown) for accessing the memory cells. The peripheral circuit includes, for example, a data latch, an address latch, a decoder, a sense amplifier, and the like. The memory core 124 is typically a synchronous memory (for example, SDRAM) that operates in synchronization with the clock signal CLK. However, the memory core 124
Is not limited to such a synchronous memory. The memory core 124 may be a type of memory that is not synchronized with the clock signal CLK. In this case, the memory core 1
The clock signal CLK supplied to 24 becomes unnecessary.

The clock signal CLK is applied to the clock signal line 1
It is supplied to the memory 120 via 10a. The data signal Data is transmitted to the memory 12 via the data signal line 110b.
0 is supplied. As described above, the clock signal CLK and the data signal Data are transferred to the memory 1 via different paths.
20. The synchronization circuit 122 of the memory 120
It is provided to reduce a skew that can occur between the clock signal CLK and the data signal Data. That is, the synchronization circuit 122 has the same function as the phase difference reduction circuit 22 shown in FIG.

The clock signal CLK is applied to the clock signal line 1
It is supplied to the processor 140 via 10c. The output signal Out is supplied to the processor 140 via the data signal line 110d. Thus, the clock signal CLK
And the output signal Out are supplied to the processor 140 via different paths. Synchronous circuit 1 of processor 140
Reference numeral 44 is provided to reduce a skew that may occur between the clock signal CLK and the output signal Out. That is, the synchronization circuit 144 has the same function as the phase difference reduction circuit 22 shown in FIG.

FIG. 6 shows the configuration of the synchronization circuit 122. The synchronization circuit 144 has a similar configuration.

In the example shown in FIG. 6, the data signal Dat
“a” is 6-bit data including a 4-bit data signal and a 2-bit control signal. The 4-bit data signal includes 1-bit signals Data (0), Data (1),
Data (2) and Data (3) are included. The 2-bit control signal is a 1-bit signal Cont (0), Cont (0)
(1) is included. The 2-bit control signal is, for example, a read / write control signal or a chip enable signal. It is needless to say that the number of bits of the data signal and the number of bits of the control signal are not limited to the example shown in FIG.

The synchronization circuit 122 has the same number of synchronization circuits 1 as the number of bits of the data signal Data so that each one-bit signal can be synchronized with the clock signal CLK.
22a to 122f.

The synchronization circuit 122a receives a 1-bit data signal Data (0) and a clock signal CLK. Synchronizing circuit 122a compares the phase of data signal Data (0) with the phase of clock signal CLK, and outputs data signal Data (Data) such that the difference between the phases becomes substantially zero.
The delay amount of a (0) is determined. This makes it possible to match the edge of data signal Data (0) with the edge of clock signal CLK.

The synchronization circuits 122b to 122f have the same configuration as the synchronization circuit 122a.

The synchronization circuits 122a to 122f are connected to the input / output line 123, respectively. I / O line 1
Reference numeral 23 is used for transmitting a delay amount determined in response to a transition of a signal level in one of the synchronization circuits 122a to 122f to another synchronization circuit. For example, the level of the data signal Data (0) changes (that is, the data signal Data (0)
Has changed from the L level to the H level, or from the H level to the L level). In this case, the amount of delay is determined such that the edge of data signal Data (0) matches the edge of clock signal CLK. The delay amount determined in this way is used for the other synchronization circuits 122b to 122b.
f.

In this way, it becomes possible to synchronize the data signal whose level has not transitioned with the clock signal CLK. Such an operation is particularly effective as a synchronous operation of the synchronous circuit 122 during the operation / transfer period. This is because, unlike a clock signal that can be used as the dummy pattern signal Dummy, the data signal Data is
This is because the level does not always change within a predetermined period.

In the following, referring again to FIG.
The operation of the memory system 100 when writing data to 0 will be described.

Processor 140 outputs a control signal, an address signal, and a signal indicating data to be written to memory 120 to memory controller 130. The control signal is, for example, RAS, CAS, a read / write control signal, or the like.

Memory controller 130 receives an address signal from processor 140 and converts the address signal. The converted address signal is stored in the memory 120
Is output to Further, the memory controller 130 receives a control signal and a signal indicating data to be written in the memory 120 from the processor 140, and outputs the received signal to the memory 120 without conversion.

During the initialization period, the output circuit 142 of the processor 140 outputs the dummy pattern signal Dum
my is output to the data signal line 110b. The dummy pattern signal Dummy is transferred to the memory 120 via the memory controller 130. Dummy pattern signal D
ummy is, for example, a pulse signal having the same cycle as the clock signal CLK. Synchronous circuit 1 of memory 120
Reference numeral 22 detects the edge of the clock signal CLK and the edge of the dummy pattern signal Dummy, and sets the amount of delay so that the edges match.

In the operation / transfer period, the processor 14
The 0 output circuit 142 outputs the data signal Data to the data signal line 110b. "Data signal Data"
A control signal, an address signal, and a signal indicating data to be written to the memory 120 are included. The data signal Data is
The data is transferred to the memory 120 via the memory controller 130.

In the operation / transfer period, power supply fluctuations and temperature fluctuations may occur due to the operation of the memory 120. Along with these fluctuations, a case may occur in which the clock signal CLK and the data signal Data are not synchronized with the delay amount set during the initialization period. Synchronous circuit 122 of memory 120
Is the edge of the clock signal CLK and the data signal Data
Are detected, and the delay amount is reset so that those edges match. As a result, a data signal Data 'synchronized with the clock signal CLK is obtained. Data signal Data 'is output to memory core 124. Thus, data signal D synchronized with clock signal CLK
data 'is written to the memory 120.

The synchronous circuit 122 performs a synchronous operation not only during the initialization period but also during the operation and transfer periods, so that the overall accuracy of the memory system 100 can be ensured. However, it is not essential that the synchronizing circuit 122 performs the synchronizing operation during the operation / transfer period. If the overall accuracy of the memory system 100 can be sufficiently ensured by the synchronous operation of the synchronous circuit 122 during the initialization period, the synchronous operation 122 during the operation / transfer period
May be omitted.

Next, the operation of the memory system 100 when reading data from the memory 120 will be described.

The operation of output circuit 126 and synchronization circuit 144 is the same as the operation of output circuit 142 and synchronization circuit 122. Edge of clock signal CLK and output signal Ou
The amount of delay is adjusted by the synchronous circuit 144 so that the edge of t
Is set to

It should be noted that the output circuit 142 is connected to the synchronous circuit 122
And the length of the data signal line 110b reaching the output circuit 126
When the length of the data signal line 110d from the data line 110 to the synchronization circuit 144 is substantially equal, the delay amount equal to the delay amount set in the synchronization circuit 122 is set to the synchronization circuit 144 without calculating the delay amount in the synchronization circuit 144. May be set. When the length of the data signal line 110b is substantially equal to the length of the data signal line 110d, the skew between the clock signal CLK and the data signal Data is substantially equal to the skew between the clock signal CLK and the output signal Out. It is considered that. Thus, the configuration of the synchronization circuit 144 can be simplified.

FIG. 5B shows a configuration of a system 100a that synchronizes the data signal Data and the clock signal CLK by delaying the clock signal CLK instead of delaying the data signal Data. 5B, the same components as those shown in FIG. 5A are denoted by the same reference numerals, and description thereof will be omitted.

The memory 120a includes a synchronization circuit 122a,
It includes a memory core 124 and an output circuit 126.

Synchronous circuit 122a receives clock signal CLK
To synchronize the data signal Data with the clock signal CLK. The synchronization circuit 122a outputs the data signal Data to the memory core 124, and outputs the delayed clock signal CLK to the memory core 124 as the clock signal CLK '. Memory core 124 receives data signal Data in synchronization with clock signal CLK ′. The output circuit 126 is supplied with the clock signal CLK ′.

FIG. 7 shows the structure of the synchronization circuit 122a.
The synchronization circuit 122a synchronizes the clock signal CLK with the data signal Data.
, Latch circuits 127 a to 127 f, and holding circuit 125
g.

The holding circuit 125g includes synchronization circuits 125a to 125g.
In the case where the signal level transitions at one of the 125f, the delay amount determined in response to the signal transition is transmitted to all synchronous circuits. Holding circuit 125
g is activated according to the control signal Mode2.

FIG. 8 shows the structure of the synchronization circuit 125a.
The synchronization circuits 125b to 125f have the same configuration as the synchronization circuit 125a.

Synchronous circuit 125a receives clock signal CLK
A delay amount determining circuit 1260 for determining a delay amount so as to reduce a phase difference between the data signal Data and the data signal Data, and a variable delay circuit 1250 for delaying the clock signal CLK according to the delay amount. The synchronization circuit 125a outputs the control signal M
It is activated according to mode1 and mode2.

The variable delay circuit 1250 includes a delay element 125
2-1 to 1252-n, AND elements 1254-1 to 125-1
254-n and a holding circuit 1256. Where n
Is any integer.

The holding circuit 1256 holds the levels of the control signals CTRL (1) to CTRL (n) input to the holding circuit 1256. Control signals CTRL (1) to CTRL
Only one of (n) is set to the H level. For example, assume that the level of control signal CTRL (1) is H level and the levels of control signals CTRL (2) to CTRL (n) are L level. In this case, the clock signal CLK passes through the AND element 1254-1,
Pass through the delay elements 1252-1 to 1252-n. The number of delay elements through which the clock signal CLK passes can be controlled using the control signals CTRL (1) to CTRL (n). Thereby, the delay amount of the clock signal CLK can be adjusted. The clock signal CLK delayed by the variable delay circuit 1250 is
It is output from the variable delay circuit 1250 as K ′ (0).

The control signal M is supplied to the delay amount determination circuit 1260.
mode1 and Mode2 are input. Control signal Mo
de1 defines an initialization period. For example, a period in which the level of the control signal Mode1 is at the H level is an initialization period. The control signal Mode2 operates and
Specifies the transfer period. For example, a period in which the level of the control signal Mode2 is at the H level is an operation / transfer period. These control signals are supplied from the processor 140 via the memory controller 130.

The delay amount determining circuit 1260 includes the phase comparator 1
262, an up / down counter 1264, and a phase comparator 1266.

The phase comparator 1262 outputs the control signal Mode
1 is activated during the initialization period.
The phase comparator 1262 compares the phase of the clock signal CLK ′ (0) with the phase of the data signal Data. When the phase of data signal Data is ahead of clock signal CLK ′ (0), phase comparator 1262 outputs up signal up1 to up / down counter 1264.
The phase of the data signal Data is the clock signal CLK '.
If it is later than (0), the phase comparator 1262
Transmits the down signal down1 to the up / down counter 12
64.

Up / down counter 1264 shifts the output of up / down counter 1264 in response to up signal up1 such that the delay amount of clock signal CLK is reduced. For example, an up-down counter 1264
Responds to the up signal up1 by “CTRL (1) =
H ”is shifted to“ CTRL (2) = H ”. The up / down counter 1264 outputs a down signal down1
, The output of the up / down counter 1264 is shifted so that the delay amount of the clock signal CLK increases. For example, the up / down counter 1264 shifts “CTRL (2) = H” to “CTRL (1) = H” in response to the down signal down1.

The phase comparator 1266 outputs the control signal Mode
2 is activated in the operation / transfer period. Phase comparator 1266 compares the phase of clock signal CLK ′ (0) with the phase of data signal Data. When the phase of data signal Data is ahead of clock signal CLK '(0), phase comparator 1266 outputs up signal u.
p2 is output to the holding circuit 125g. Data signal Dat
If the phase of “a” is behind the clock signal CLK ′ (0), the phase comparator 1266 outputs the down signal down.
2 is output to the holding circuit 125g.

The holding circuit 125g responds to the up signal up2 or the down signal down2, and
An up signal up3 or a down signal down3 is output to each of a to 125f. Thereby, the synchronization circuit 1
25a to 125f can be controlled simultaneously.

As described above, the synchronization circuit 125a outputs the clock signal CLK 'synchronized with the data signal Data.
(0) is output. The latch circuit 127a responds to the edge of the clock signal CLK '(0) to respond to the data signal Dat.
Latch a. Clock signal CLK '(0) and data signal Data output from latch circuit 127a
(0) is output to the memory core 124.

Similarly, the clock signal CLK '(1)
To CLK ′ (5) and data signals Data (1) to Da
ta (3), control signals Cont (0) to Cont (1)
Are output to the memory core 124. Memory core 124
Operates according to one of the clock signals CLK '(0) to CLK' (5).

Hereinafter, another example in which the present invention is applied to a memory system will be described.

FIG. 9 shows the configuration of the memory system 200. The memory system 200 has a plurality of memories 220. Each of the memories 220 includes a synchronization circuit 122
, A memory core 124, an output circuit 126, and a flag signal generation circuit 222.

In FIG. 9, the same components as those of the memory system 100 shown in FIG. 5A are denoted by the same reference numerals, and description thereof will be omitted.

When the memory controller 130 controls the plurality of memories 220, if the synchronization processing during the initialization period is always performed before transferring the data signal Data, the initialization period will be lengthened, and the high speed operation of the memory system 200 will occur. There is a possibility that it will be an obstacle to conversion. In the memory system 200, when the synchronization circuit 122 performs the synchronization process during the operation / transfer period, the synchronization circuit 122 does not perform the synchronization process in the next initialization period following the operation / transfer period. Is controlled.

The flag signal generation circuit 222 includes the synchronization circuit 1
22 performs the synchronization process (that is, the edge of the clock signal CLK and the data signal Dat
H for a certain period from the time when the edge of a ′ coincides)
A flag signal Flag which becomes a level is generated (FIG. 10A).
reference). While the flag signal Flag is at the H level,
It is preferable that the time is about several tens to several tens ns. Especially,
When the frequency of the clock signal CLK is high, the period during which the flag signal Flag is at the H level is preferably 20 ns or less.

FIG. 10B shows a configuration of the flag signal generation circuit 222.

The flag signal generation circuit 222 detects a level transition of the data signal Data ',
And an RS flip-flop (RS-FF) 222b;
And a counter 222c.

The detector 222a outputs the data signal Data '
The pulse signal set is generated in response to the level transition. The pulse signal set is supplied to the RS-FF 222b and the counter 222c. The detector 222a includes, for example, a delay element 222e and an exclusive OR element 222f. The RS-FF 222b outputs the pulse signal set
, The level of the flag generation signal Flag is changed from L level to H level.

The counter 222c resets the count value in response to the pulse signal set. Thereafter, the counter 222c increments the count value in response to the edge of the clock signal CLK. When the count value of the counter 222c reaches a predetermined value, the counter 222c
Outputs a pulse signal reset to the RS-FF 222b.

The RS-FF 222b outputs the pulse signal res
, the level of the flag generation signal Flag is set to H
Change from level to L level.

In this manner, the flag signal Flag which becomes H level for a certain period from the time when the data signal Data 'transits is generated.

The flag signal Flag is transmitted to the processor 140
Is forwarded to The processor 140 outputs the flag signal Fla
It is determined whether or not to perform the synchronization processing according to the level of g.

By such processing, it is possible to prevent a device having a high synchronization accuracy from performing the synchronization process during the initialization period. As a result, the number of devices (memory) that require synchronization processing during the initialization period is reduced, and the synchronization processing is optimized. As a result, the speed of the memory system 200 can be increased. In the example described above, when the level of the flag signal Flag is at the H level, the flag signal Flag
Are not synchronized in the next initialization period, and when the level of the flag signal Flag is L level, the flag signal
In the memory 220 corresponding to g, the synchronization processing is performed in the next initialization period. Flag signal F
If the level of the flag is L level, the operation of the memory 220 corresponding to the flag signal Flag is forcibly completed at that time, the operation / transfer period is shifted to the initialization period, and the synchronization process is performed in the initialization period. It may be performed. (Embodiment 2) FIG. 11 shows a configuration of a system 2 according to Embodiment 2 of the present invention. The system 2 includes a clock signal generator 10, a slave 20a, and a master 30a. 11, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The master 30a includes an output circuit 32a.
The output circuit 32a outputs the dummy pattern signal Dummy to the data signal line 10b during the initialization period, and outputs the data signal Data to the data signal line 1 during the operation / transfer period.
0b. The output circuit 32a outputs a control signal Mode1 that defines an initialization period to the control signal line 10c. The output circuit 32a receives the control signal REFOUT via the control signal line 10d. Control signal REFO
UT is a control signal indicating that the initialization period has ended. For example, the end of the initialization period means that the level of the control signal REFOUT changes from L level to H level.
It is represented by transitioning to a level.

The slave 20a includes a phase difference reducing circuit 320
And an internal circuit 24.

FIG. 12 shows the configuration of the phase difference reducing circuit 320.

The clock signal CLK is input to the phase difference reduction circuit 320 via the clock signal line 10a, and the dummy pattern signal Dummy is input via the data signal line 10b.
And data signal Data are input. The control signal Mode1 defining the initialization period is further input to the phase difference reduction circuit 320 via the control signal line 10c.

The phase difference reducing circuit 320 outputs the clock signal C
The clock signal CLK is delayed so that the phase difference between LK and the dummy pattern signal Dummy is reduced. Hereinafter, the clock signal CLK thus delayed is referred to as a clock signal CLK ′.

The phase difference reducing circuit 320 outputs a control signal REFOUT indicating a result of comparing the phase of the dummy pattern signal Dummy with the phase of the clock signal CLK ′ to the control signal line 10d.

Hereinafter, the operation of the phase difference reducing circuit 320 will be described with reference to FIG.

First, the master 30a (FIG. 11) changes the level of the control signal Mode1 from L level to H level. Thus, an initialization period is started. The initialization period is defined as a period during which the control signal Mode1 is at the H level.

In the initialization period, the dummy pattern signal Dummy is input to the phase difference reduction circuit 320 via the data signal line 10b. Here, it is assumed that the dummy pattern signal Dummy is a clock signal having the same cycle as the clock signal CLK.

In the initialization period, the phase comparator 322 is activated by the control signal Mode1.
The phase comparator 322 compares the phase of the clock signal CLK with the phase of the dummy pattern signal Dummy. When the phase of clock signal CLK is ahead of the phase of dummy pattern signal Dummy, phase comparator 322 outputs pulse signal Bac having a pulse width corresponding to the phase difference.
k is output to the variable delay circuit 324. Clock signal CL
If the phase of K is behind the phase of the dummy pattern signal Dummy, the phase comparator 322 outputs a pulse signal Front having a pulse width corresponding to the phase difference to the variable delay circuit 324.

The variable delay circuit 324 outputs the pulse signal Bac
k, the delay amount is increased, and the pulse signal Front
To reduce the amount of delay. Clock signal CLK
Is delayed according to the delay amount set in the variable delay circuit 324. Thus, the amount of delay of variable delay circuit 324 is determined such that the edge of clock signal CLK matches the edge of dummy pattern signal Dummy.

The phase comparator 326 outputs the clock signal CL
The phase of K 'is compared with the phase of the dummy pattern signal Dummy. When the phase difference between the clock signal CLK 'and the dummy pattern signal Dummy is larger than a predetermined value, the level of the control signal REFOUT is at the L level.
Clock signal CLK 'and dummy pattern signal Dummy
Is less than or equal to a predetermined value, the level of control signal REFOUT is at H level. Ideally, the predetermined value is zero. However, in an actual design, it is sufficient that the predetermined value is sufficiently close to zero.
In response to the change of the level of the control signal REFOUT from the L level to the H level, the delay amount of the variable delay circuit 324 is locked.

When the level of control signal Mode1 is L level, switch 328 outputs data signal line 10b.
Is output to the holding circuit 330, and when the level of the control signal Mode1 is H level,
The signal input through the data signal line 10b is not output to the holding circuit 330.

The holding circuit 330 outputs the clock signal CLK '
, The signal output from the switch 328 is held and output to the internal circuit 24 (FIG. 11).

Master 30a (FIG. 11) provides control signal RE
After confirming that the level of FOUT has changed from the L level to the H level, the level of the control signal Mode1 is changed from the H level to the L level. Thus, the initialization period ends. Thereafter, the operation / transfer period is started. During the operation / transfer period, the data signal line 10
b through the phase difference reduction circuit 320
Is input to

When the lock time from the start of the initialization period to the locking of the delay amount in variable delay circuit 324 can be predicted in advance, there is no need to output control signal REFOUT. This is because the transfer operation of the data signal Data may be started after the lock time has elapsed.

FIG. 13 shows the waveform of each signal used in the phase difference reduction circuit 320.

At time T ₁ , the level of control signal Mode 1 changes from L level to H level. Thus, an initialization period is started. At time T _1, the phase of the clock signal CLK is ahead of the dummy pattern signal Dummy phases. Therefore, the delay amount of the variable delay circuit 324 is increased by the pulse signal Back. The clock signal CLK is delayed according to the delay amount set in the variable delay circuit 324.

At time T ₂ , the phase of clock signal CLK ′ matches the phase of dummy pattern signal Dummy. In FIG. 13, a white circle indicates that the edge of the clock signal CLK 'matches the edge of the dummy pattern signal Dummy.

[0127] At time T _3, in response to the phase difference between the clock signal CLK 'and the dummy pattern signal Dummy has disappeared, the level of the control signal REFOUT L
The level changes from the level to the H level.

At time T ₄ , the level of control signal Mode 1 changes from H level to L level. Thus, the initialization period ends. FIG. 14 shows the configuration of the phase difference reduction circuit 420. The phase difference reduction circuit 420 can be replaced with the phase difference reduction circuit 320 shown in FIG.

The phase difference reducing circuit 420 controls the control signal Mod
Instead of using e1, the start of the initialization period is detected by detecting a predetermined initialization pattern. Therefore, the control signal Mode1 is not input to the phase difference reduction circuit 420. The phase difference reducing circuit 420 receives the clock signal CLK via the clock signal line 10a.
Is input, and the dummy pattern signal Dummy and the data signal Data are input via the data signal line 10b.

The phase difference reducing circuit 420 generates the clock signal C
The clock signal CLK is delayed so that the phase difference between LK and the dummy pattern signal Dummy is reduced. Hereinafter, the clock signal CLK thus delayed is referred to as a clock signal CLK ′.

From the phase difference reducing circuit 420, a control signal REFOUT indicating the result of comparing the phase of the dummy pattern signal Dummy with the phase of the clock signal CLK 'is output.

Hereinafter, the operation of the phase difference reduction circuit 420 will be described with reference to FIG.

The decoder 421 determines whether or not a signal input via the data signal line 10b includes a predetermined initialization pattern. The predetermined initialization pattern is, for example, a signal having a pattern of HLHHLL (see FIG. 15A).

When the decoder 421 detects the initialization pattern, the decoder 421 recognizes that the initialization period starts. During the initialization period, the dummy pattern signal Dummy is input to the phase difference reduction circuit 420 via the data signal line 10b. Here, it is assumed that the dummy pattern signal Dummy is a clock signal having the same cycle as the clock signal CLK. The decoder 421 switches the selector 428 so as to output a signal input via the data signal line 10b to the phase comparator 422.

Phase comparator 422 and variable delay circuit 42
The function and operation of the phase comparator 3 shown in FIG.
22 and those of the variable delay circuit 324.
Therefore, detailed description is omitted here.

The phase comparator 426 has a phase comparator 326.
A control signal REFOUT is generated in the same manner as (FIG. 12). Phase comparator 426 outputs a signal indicating that the initialization period has ended to decoder 421 in response to the level of control signal REFOUT changing from L level to H level.

The decoder 421 responds to a signal from the phase comparator 426 to output a signal input via the data signal line 10b to the holding circuit 430.
Switch 28. The decoder 421 includes the variable delay circuit 4
Lock the amount of delay at 24.

The holding circuit 430 outputs the clock signal CLK ′
, The signal output from the selector 428 is held and output to the internal circuit 24 (FIG. 11).

The master 30a (FIG. 11) controls the control signal RE.
After confirming that the level of FOUT has changed from the L level to the H level, the transfer operation of the data signal Data is started.

When the lock time from the start of the initialization period to the locking of the delay amount in variable delay circuit 424 can be predicted in advance, there is no need to output control signal REFOUT. This is because the transfer operation of the data signal Data may be started after the lock time has elapsed.

FIG. 15B shows the waveform of each signal when the phase of the clock signal CLK is delayed from the phase of the dummy pattern signal Dummy.

A pulse signal Front having a pulse width W1 corresponding to the phase difference between the clock signal CLK and the dummy pattern signal Dummy is output to the variable delay circuit 424. As a result, the clock signal CLK is delayed, and the phase of the clock signal CLK ′ and the dummy pattern signal Dum
my coincides with the phase. In FIG. 15B, two white circles indicate an edge of the clock signal CLK and an edge of the clock signal CLK 'corresponding to the edge.

FIG. 15C shows the waveform of each signal when the phase of the clock signal CLK leads the phase of the dummy pattern signal Dummy.

A pulse signal Back having a pulse width W2 corresponding to the phase difference between the clock signal CLK and the dummy pattern signal Dummy is output to the variable delay circuit 424. As a result, the clock signal CLK is delayed, and the phase of the clock signal CLK ′ and the dummy pattern signal Dumm
The phase of y matches. In FIG. 15C, two white circles indicate an edge of the clock signal CLK and an edge of the clock signal CLK 'corresponding to the edge.

As described above, phase difference reduction circuits 320 and 420 reduce the phase difference between clock signal CLK and data signal Data by delaying clock signal CLK. Alternatively, the phase difference reduction circuits 320 and 420 may be modified so as to reduce the phase difference between the clock signal CLK and the data signal Data by delaying the data signal Data. The phase difference reduction circuits 320 and 420 thus modified are also included in the scope of the present invention. (Third Embodiment) FIG. 16 shows a configuration of a system 3 according to a third embodiment of the present invention. The system 3 includes a clock signal generator 10, a slave 20b, and a master 30a. 16, the same components as those shown in FIG. 11 are denoted by the same reference numerals, and description thereof will be omitted.

The clock signal CLK is supplied to the master 30a. Master 30a operates according to clock signal CLK. The slave 20b has a clock signal CL
K is not supplied. The slave 20b receives the clock signal C
LK ′ is generated inside the slave 20b and operates according to the clock signal CLK ′.

According to the system 3, there is no need to transfer the clock signal CLK supplied to the circuit on the transmitting side to the circuit on the receiving side. Such a system configuration is particularly effective when the distance between the circuit on the transmitting side and the circuit on the receiving side is very large.

The slave 20b includes a phase difference reduction circuit 520
And an internal circuit 24. The internal circuit 24 operates according to the clock signal CLK '.

FIG. 17 shows the structure of the phase difference reduction circuit 520.

The dummy pattern signal Dummy and the data signal Data are input to the phase difference reduction circuit 520 via the data signal line 10b. Phase difference reduction circuit 520
Is further supplied with a control signal Mode1 for defining an initialization period via a control signal line 10c.

The phase difference reducing circuit 520 generates the clock signal CLK 'so that the phase difference between the dummy pattern signal Dummy and the clock signal CLK' is reduced.

The phase difference reducing circuit 520 outputs a control signal REFOUT indicating the result of comparing the phase of the dummy pattern signal Dummy with the phase of the clock signal CLK ′ to the control signal line 10d.

Hereinafter, the operation of the phase difference reduction circuit 520 will be described with reference to FIG.

First, master 30a (FIG. 16) changes the level of control signal Mode1 from L level to H level. Thus, an initialization period is started. The initialization period is defined as a period during which the control signal Mode1 is at the H level.

In the initialization period, the dummy pattern signal Dummy is input to the phase difference reduction circuit 520 via the data signal line 10b. Here, it is assumed that the dummy pattern signal Dummy is a clock signal having the same cycle as the clock signal CLK.

In the initialization period, phase comparator 522 is activated by control signal Mode1.
The phase comparator 522 compares the phase of the dummy pattern signal Dummy with the phase of the clock signal CLK ′. The clock signal CLK ′ is generated by the oscillator (VCO) 524. When the phase of the clock signal CLK ′ is ahead of the phase of the dummy pattern signal Dummy, the phase comparator 522 outputs a pulse signal Back having a pulse width corresponding to the phase difference to the VCO control circuit 523. When the phase of the clock signal CLK 'is behind the phase of the dummy pattern signal Dummy, the phase comparator 522 outputs a pulse signal Front having a pulse width corresponding to the phase difference to the VCO control circuit 523.

The VCO control circuit 523 outputs the pulse signal Ba
VCO5 so that the oscillation frequency decreases in response to
24, and controls the VCO 524 so that the oscillation frequency increases in response to the pulse signal Front. The phase of the clock signal CLK ′ is adjusted by the VCO 524. In this way, the oscillation frequency of the VCO 524 is determined so that the edge of the clock signal CLK 'matches the edge of the dummy pattern signal Dummy.

The phase comparator 522 controls the control signal REFOU.
Generate T. When the phase difference between the clock signal CLK 'and the dummy pattern signal Dummy is larger than a predetermined value, the level of the control signal REFOUT is at the L level. Clock signal CLK 'and dummy pattern signal Dum
When the phase difference between the control signal MY and the control signal MY is equal to or smaller than a predetermined value, the level of the control signal REFOUT is at the H level. Ideally, the predetermined value is zero. However, in an actual design, it is sufficient that the predetermined value is sufficiently close to zero.

The potential holding circuit 526 outputs the control signal REFO
In response to the change in the level of the UT from the L level to the H level, the potential supplied from the phase comparator 522 is held. The potential held by the potential holding circuit 526 is
It is supplied to the VCO control circuit 523. Thereby, VC
The oscillation state of O524 is locked. Switch 528
Outputs the signal input via the data signal line 10b to the holding circuit 530 when the level of the control signal Mode1 is L level, and outputs the data when the level of the control signal Mode1 is H level. The signal input through the signal line 10b is not output to the holding circuit 530.

The holding circuit 530 outputs the clock signal CLK ′
, The signal output from the switch 528 is held and output to the internal circuit 24 (FIG. 16).

The master 30a (FIG. 16) controls the control signal RE.
After confirming that the level of FOUT has changed from the L level to the H level, the level of the control signal Mode1 is changed from the H level to the L level. Thus, the initialization period ends. Thereafter, the operation / transfer period is started. During the operation / transfer period, the data signal line 10
b through the phase difference reduction circuit 520
Is input to

Note that VC from the start of the initialization period
If the lock time until the oscillation state of O524 is locked can be predicted in advance, the control signal REFO
There is no need to output a UT. This is because the transfer operation of the data signal Data may be started after the lock time has elapsed.

FIG. 18 shows the waveform of each signal used in the phase difference reduction circuit 520.

At time T ₁ , the level of control signal Mode 1 changes from L level to H level. Thus, an initialization period is started. At time T _1, the phase dummy pattern signal Dummy of the clock signal CLK '
Phase is advanced. Therefore, the pulse signal Back
As a result, the oscillation frequency of the VCO 524 is reduced. After that, the pulse signal Front and the pulse signal Back
, The oscillation frequency of VCO 524 is adjusted.

At time T ₂ , the phase of clock signal CLK ′ matches the phase of dummy pattern signal Dummy. In FIG. 18, a white circle indicates that the edge of the clock signal CLK ′ coincides with the edge of the dummy pattern signal Dummy.

[0166] At time T _3, in response to the phase difference between the clock signal CLK 'and the dummy pattern signal Dummy has disappeared, the level of the control signal REFOUT L
The level changes from the level to the H level.

At time T ₄ , the level of control signal Mode 1 changes from H level to L level. Thus, the initialization period ends. FIG. 19 shows the configuration of the phase difference reduction circuit 620. The phase difference reduction circuit 620 can be replaced with the phase difference reduction circuit 520 shown in FIG.

The phase difference reducing circuit 620 controls the control signal Mod
Instead of using e1, the start of the initialization period is detected by detecting a predetermined initialization pattern. Therefore, the control signal Mode1 is not input to the phase difference reduction circuit 620. The phase difference reduction circuit 620 has a dummy pattern signal D via the data signal line 10b.
ummy and the data signal Data are input.

The phase difference reducing circuit 620 generates the clock signal CLK 'so that the phase difference between the dummy pattern signal Dummy and the clock signal CLK' is reduced.

The phase difference reduction circuit 620 outputs a control signal REFOUT indicating the result of comparing the phase of the dummy pattern signal Dummy with the phase of the clock signal CLK '.

Hereinafter, the operation of the phase difference reducing circuit 620 will be described with reference to FIG.

The decoder 621 determines whether or not a signal input via the data signal line 10b includes a predetermined initialization pattern. The predetermined initialization pattern is, for example, a signal having a pattern of HLHHLL (see FIG. 20A).

When the decoder 621 detects the initialization pattern, the decoder 621 recognizes that the initialization period starts. During the initialization period, the dummy pattern signal Dummy is input to the phase difference reduction circuit 620 via the data signal line 10b. Here, it is assumed that the dummy pattern signal Dummy is a clock signal having the same cycle as the clock signal CLK. The decoder 621 switches the selector 628 so as to output a signal input via the data signal line 10b to the phase comparator 622.

Phase comparator 622, VCO control circuit 623
The functions and operations of VCO 624 and VCO 624 correspond to phase comparator 522, VCO control circuit 523 and VCO shown in FIG.
Identical to those of CO524. Therefore, detailed description is omitted here. The phase comparator 622 controls the control signal REFOUT similarly to the phase comparator 522 (FIG. 17).
Generate

The potential holding circuit 626 controls the control signal REFO
In response to the UT level changing from the L level to the H level, the potential supplied from the phase comparator 622 is held. The potential held by the potential holding circuit 626 is
It is supplied to the VCO control circuit 623.

The decoder 621 outputs the control signal REFOUT
Is switched from the L level to the H level, the selector 628 is switched to output a signal input via the data signal line 10b to the holding circuit 630.

The holding circuit 630 outputs the clock signal CLK ′
, The signal output from the selector 628 is held and output to the internal circuit 24 (FIG. 16).

The master 30a (FIG. 16) controls the control signal RE.
After confirming that the level of FOUT has changed from the L level to the H level, the transfer operation of the data signal Data is started.

It should be noted that, from the start of the initialization period, VC
If the lock time until the oscillation state of O624 is locked can be predicted in advance, the control signal REFO
There is no need to output a UT. This is because the transfer operation of the data signal Data may be started after the lock time has elapsed.

FIG. 20B shows a state where the phase of the clock signal CLK 'coincides with the phase of the dummy pattern signal Dummy.

As described above, phase difference reduction circuits 520 and 620 reduce the phase difference between clock signal CLK ′ and data signal Data by adjusting the oscillation frequency of VCOs 524 and 624. Alternatively, phase difference reduction circuits 520 and 620 may be modified so as to reduce the phase difference between clock signal CLK ′ and data signal Data by delaying data signal Data. Phase difference reduction circuit 520 so modified
And 620 are also within the scope of the present invention.

In the system 3 described above, during the operation for transferring the data signal Data and the transfer period, the VCO 52
4 (or 624) continues to oscillate in the locked oscillation state during the initialization period. Therefore, during the operation / transfer period, the phase of the clock signal CLK ′ and the phase of the data signal Data may be shifted.

Hereinafter, a correction process for reducing a phase shift that may occur during the operation / transfer period will be described. In addition,
This correction process is performed on the assumption that the cycle of the data signal Data is a constant multiple of the cycle of the clock signal CLK '.

FIG. 21A shows a configuration of a phase difference reduction circuit 520a having a function of executing a correction process. The phase difference reduction circuit 520a includes the phase difference reduction circuit 52 shown in FIG.
It is obtained by replacing the VCO 524 at 0 with a VCO 524a and adding a correction circuit 532 that executes a correction process. 21A, the same components as those shown in FIG. 17 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 21B shows a configuration of VCO 524a and correction circuit 532.

VCO 524a includes a ring oscillator 524c in which n inverters are connected in a ring, and a selector 524b for selecting a signal output from the k-th inverter among the n inverters. Where n
Is an arbitrary integer of 2 or more, and k is an integer of 1 or more and n or less. Hereinafter, for the sake of simplicity, it is assumed that ring oscillator 524c includes three inverters. That is, it is assumed that n = 3.

The ring oscillator 524c includes an inverter 524c1 and an inverter 524c connected in a ring.
2 and an inverter 524c3. Nodes N ₁ , N ₂ and N ₃ are connected to inverter 524c1, inverter 524
c2 and the output of the inverter 524c3.

[0188] state of the ring oscillator 524c, the node voltage level and the node of the voltage level and the node N ₂ of N ₁ N
It is represented by a set of _three voltage levels. The ring oscillator 524c has the following states 1 to 6. State 1 to state 6 make a transition in this order, and return to state 1 after state 6.

State 1: (H, L, H) State 2: (L, L, H) State 3: (L, H, H) State 4: (L, H, L) State 5: (H, H) , L) condition 6: (H, L, L) where, (x, y, z), the voltage level of node N ₁ is the x level, the voltage level of the node N ₂ is y level, the node the voltage level of the N ₃ indicates the state is z level.

Each of the voltage levels of node N ₁ , node N ₂ and node N ₃ alternates between H level and L level. Therefore, the signal SN ₃ output from the node signals SN ₁ output from the N _1, the signal SN ₂ and the node N ₃ is output from the node N ₂ becomes a clock signal that oscillates at a predetermined period.

Selector 524b selects _{one of} signal SN ₁ , signal SN ₂ and signal SN ₃ according to selection signal Sel. The signal selected by the selector 524b is output from the VCO 524a as a clock signal CLK '.

The correction circuit 532 includes the ring oscillator 52
Holding circuits 534a and 534b for holding the state of FIG.
A counter 536 for counting the number of turns in the state of the ring oscillator 524c, holding circuits 538a and 538b for holding the count value of the counter 536, and a holding circuit 534
a change amount detection circuit 540a for detecting a change amount between the state held in the holding circuit a and the state held in the holding circuit 534b, the count value held in the holding circuit 538a, and the holding circuit 53
8b, a change amount detection circuit 540b for detecting a change amount with respect to the count value held in 8b, and a division circuit 542 for dividing the change amount detected by the change amount detection circuit 540a by the change amount detected by the change amount detection circuit 540b. And a control circuit 54 for generating a control signal S _V based on the result of the division.
4 and a control circuit 546 that generates a selection signal Sel based on the change amount detected by the change amount detection circuit 540a.
And

Holding circuits 534a, 534b, counter 5
36, holding circuits 538a, 538b, change amount detection circuit 5
40a, 540b, a division circuit 542, a control circuit 544,
Each of 546 is activated by control signal Mode2.

Hereinafter, the operation of the correction circuit 532 will be described.

In response to the transition of the level of data signal Data, holding circuit 534a and holding circuit 534
The current state of the ring oscillator 524c is held in one of the positions b. The other of the holding circuits 534a and 534b holds the state immediately before the ring oscillator 524c.

The change amount detection circuit 540a determines the current state of the ring oscillator 524c and the ring oscillator 524c.
The amount of change from the previous state is detected. For example, the current state of the ring oscillator 524c is “state 3”,
The state immediately before the ring oscillator 524c is “state 1”.
In the case of, the change amount is 2 (= 3-1).
The change amount detection circuit 540a outputs a signal having a value of 2 to the division circuit 542 as a signal indicating the change amount.

The counter 536 includes the ring oscillator 52
The number of turns in the state of 4c is counted. Counter 536
Increments the count value by one in response to the state of the ring oscillator 524c transitioning from state 1 to the next state 1.

In response to the transition of the level of data signal Data, holding circuit 538a and holding circuit 538
The current count value of the counter 536 is held in one of b. The other of the holding circuit 538a and the holding circuit 538b holds the count value immediately before the counter 536.

The change amount detection circuit 540b includes a counter 53
The change amount between the current count value of No. 6 and the count value immediately before the counter 536 is detected. The amount of change is determined by the data signal Data after the level of the data signal Data transitions.
Ring oscillator 524 until the next level transitions
Shows the number of turns in state c. For example, when the current count value is “5” and the previous count value is “2”, the change amount is 3 (= 5-2). The change amount detection circuit 540b outputs a signal having a value of 3 to the division circuit 542 as a signal indicating the change amount.

The dividing circuit 542 includes a change amount detecting circuit 540
a change amount detection circuit 540b
Divide by the amount of change detected by. The division result indicates how many phases of the data signal Data have a phase shift corresponding to one rotation of the ring oscillator 524c. For example, in the case of the example described above, the division result is 2/3 (= 2 ÷ 3). This indicates that the data signal Data is delayed by an amount corresponding to ２ of the state of the ring oscillator 524c per one turn of the ring oscillator 524c.

Control circuit 544 generates control signal S _V according to the result of the division. Control signal S _V is supplied to the VCO control circuit 523. Thereby, according to the division result,
The oscillation frequency of the VCO 524a is adjusted. For example, the division if the result is 2/3, the control circuit 544, a control signal S _V as the period of the ring oscillator length by a clock signal CLK corresponding to 2/3 state amount of 524c 'is longer Generate.

The control circuit 546 includes a change amount detection circuit 540.
a, the selection signal Sel
Change the value of. For example, when the change amount detected by the change amount detection circuit 540a is 2, the data signal Data
By the time the level of “a” transitions this time, the data signal Data
Is delayed by an amount corresponding to two states of the ring oscillator 524c. In this case, the control circuit 546
The value of the selection signal Sel is changed so that the signal is output from a node two stages behind the node to which the signal is output.

As described above, the correction circuit 532 outputs the data signal Da from the previous transition of the level of the data signal Data to the transition of the current level of the data signal Data.
The amount of delay of ta is calculated, and the VCO 524a delays the clock signal CLK 'by an amount corresponding to the amount of delay.
Further, the correction circuit 532 calculates a delay amount of the data signal Data per one turn of the ring oscillator 524c,
VCO 524a generates a clock signal CLK 'having a frequency lower by an amount corresponding to the delay amount. As a result, the edge of the data signal Data is shifted to the clock signal CL.
The phase of the clock signal CLK 'is adjusted so as to coincide with the edge of K'.

[0204] Figure 22A is a signal output from the signal SN _2, the node N ₃ is output signal SN ₁ is, from the node N ₂ outputted from the node N ₁ of the ring oscillator 524c SN
₃ shows a waveform. As shown in FIG. 22A, the signal SN ₂
Phase is later than the delay amount by the signals SN ₁ phase corresponding to one stage of the inverter, the phase of the signal SN ₃ is later than the delay amount by the signals SN ₂ phase corresponding to one stage of inverter ing.

FIG. 22B shows an example of the correction processing executed by the correction circuit 532.

In the example shown in FIG. 22B, data signal D
ata changes from L level to H level at time T ₁ ,
Assume changes from H level to L level at time T _2. In the period from time T ₁ to time T ₂ , data signal Data is delayed by an amount corresponding to two states of ring oscillator 524 c, and in the period from time T ₁ to time T ₂ , the number of revolutions of ring oscillator 524 c is Assume it is 3.

In this case, the clock signal CLK 'is delayed by the delay amount α by the above-described correction processing. here,
The delay amount α is an amount corresponding to two states of the ring oscillator 524c. As a result, at time T _2, the edge of the edge of the data signal Data and the clock signal CLK 'matches. Further, by the above-described correction process, from the time T _2, the period of the clock signal CLK 'becomes (T + β).
Here, T is indicates the period of the clock signal CLK 'in the period from time T ₁ to T _2, beta ring oscillator 5
The length corresponding to 2/3 of 24c is shown.

[0208] Further, in the example shown in FIG. 22B, the assumed data signal Data is at time T ₃ changes from L level to H level. Further, the data signal Data in the period from time T _2, to the time T ₃ has the ring oscillator 5
Only delayed an amount corresponding to the 1 state portion of 24c, the ring oscillator 524 in a period from time T _2, until time T ₃
Assume that the number of turns of c is 2.

In this case, the clock signal CLK 'is delayed by the delay amount γ by the above-described correction processing. here,
The delay amount γ is an amount corresponding to one state of the ring oscillator 524c. As a result, at time T _3, the edge of the edge of the data signal Data and the clock signal CLK 'matches. Further, by the above-described correction process, from the time T _3, the clock signal CLK 'period of (T' becomes + [delta]). Here, T 'is the clock signal CLK during the period from time T _2, to T _3' indicates a period of, [delta] indicates a length corresponding to 1/2 state amount of the ring oscillator 524c.

[0210]

According to the present invention, it is possible to provide a semiconductor integrated circuit, a system and a method which do not cause skew even when a clock signal and a data signal are transferred through different paths.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a system 1 according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an output circuit 32.

FIG. 3 is a diagram illustrating a configuration of a phase difference reduction circuit 22.

FIG. 4A is a diagram showing how a clock signal CLK and a dummy pattern signal Dummy are synchronized during an initialization period.

FIG. 4B is a diagram showing a clock signal CL during an operation / transfer period.
FIG. 6 is a diagram illustrating a state in which K and a data signal Data are synchronized.

5A is a diagram showing a configuration of a memory system 100. FIG.

FIG. 5B is a diagram showing a configuration of a memory system 100a.

FIG. 6 is a diagram showing a configuration of a synchronization circuit 122.

FIG. 7 is a diagram showing another configuration of the synchronization circuit 122.

FIG. 8 is a diagram illustrating a configuration of a synchronization circuit 125a.

FIG. 9 is a diagram showing a configuration of a memory system 200.

FIG. 10A is a diagram showing a waveform of a flag signal Flag.

FIG. 10B is a diagram showing a configuration of a flag signal generation circuit 222.

FIG. 11 is a diagram showing a configuration of a system 2 according to a second embodiment of the present invention.

FIG. 12 is a diagram showing a configuration of a phase difference reduction circuit 320.

FIG. 13 is a diagram showing waveforms of signals used in the phase difference reduction circuit 320.

FIG. 14 is a diagram showing a configuration of a phase difference reduction circuit 420.

FIG. 15A is a diagram showing an example of an initialization pattern.

FIG. 15B is a diagram showing a waveform of each signal when the phase of the clock signal CLK is delayed from the phase of the dummy pattern signal Dummy.

FIG. 15C is a diagram showing the waveform of each signal when the phase of the clock signal CLK is ahead of the phase of the dummy pattern signal Dummy.

FIG. 16 is a diagram showing a configuration of a system 3 according to a third embodiment of the present invention.

FIG. 17 is a diagram showing a configuration of a phase difference reduction circuit 520.

FIG. 18 is a diagram showing waveforms of signals used in the phase difference reduction circuit 520.

FIG. 19 is a diagram showing a configuration of a phase difference reduction circuit 620.

FIG. 20A is a diagram showing an example of an initialization pattern.

FIG. 20B is a diagram showing a state where the phase of the clock signal CLK ′ matches the phase of the dummy pattern signal Dummy.

FIG. 21A is a diagram showing a configuration of a phase difference reduction circuit 520a.

21B is a diagram showing a configuration of a VCO 524a and a correction circuit 532. FIG.

FIG. 22A is a diagram illustrating a waveform of a signal output from a k-th delay circuit among n delay circuits included in a ring oscillator 524c.

FIG. 22B is a diagram showing a case where the cycle of the clock signal CLK ′ is shorter than the cycle of the data signal Data.

FIG. 23A is a diagram showing a configuration of a conventional synchronization system.

FIG. 23B is a diagram showing a phase shift.

FIG. 24A is a diagram showing a case where the phase of a reference clock signal SysCLK completely matches the phase of a data signal.

FIG. 24B is a diagram showing a case where a phase shift T occurs between the phase of the reference clock signal SysCLK and the phase of the data signal.

FIG. 24C: When the frequency of the reference clock signal is high,
FIG. 9 is a diagram illustrating a case where a phase shift T occurs between the phase of a reference clock signal SysCLK and the phase of a data signal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 System 10 Clock generator 20 Semiconductor integrated circuit 22 Phase difference reduction circuit 24 Internal circuit 30 Controller

Claims (15)

[Claims] 1. A first signal between a clock signal and a data signal.
A semiconductor integrated circuit, comprising: a phase difference reducing circuit configured to reduce a phase difference between the clock signal; 2. A delay amount determining circuit that determines a first delay amount such that a second phase difference between the clock signal and the dummy pattern signal is reduced; 2. The semiconductor integrated circuit according to claim 1, further comprising: a variable delay circuit that delays one of the clock signal and the data signal according to a delay amount of one. 3. The delay amount determination circuit further determines a second delay amount such that the first phase difference between the clock signal and the data signal is reduced, and the variable delay circuit includes: 3. The semiconductor integrated circuit according to claim 2, wherein one of said clock signal and said data signal is delayed according to said second delay amount. 4. The semiconductor integrated circuit according to claim 2, wherein the dummy pattern signal is a signal that changes at least once from a first logic level to a second logic level. 5. The data signal is input to the phase difference reduction circuit via a data line, and the dummy pattern signal is output via the data line before the data signal is input to the phase difference reduction circuit. 3. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is input to the phase difference reduction circuit. 6. A system including a first semiconductor integrated circuit and a second semiconductor integrated circuit, wherein the first semiconductor integrated circuit includes an output circuit that outputs a data signal to the second semiconductor integrated circuit. The second semiconductor integrated circuit receives the data signal output from the first semiconductor integrated circuit, and reduces a first phase difference between a clock signal and the data signal; Receiving the data signal with the first phase difference between the signal and the signal reduced. 7. A delay amount determining circuit that determines a first delay amount such that a second phase difference between the clock signal and the dummy pattern signal is reduced, and 7. The system according to claim 6, further comprising: a variable delay circuit that delays one of the clock signal and the data signal according to a delay amount of one. 8. The delay amount determination circuit further determines a second delay amount so that the first phase difference between the clock signal and the data signal is reduced, and the variable delay circuit 8. The system of claim 7, wherein one of the clock signal and the data signal is delayed according to the second delay amount. 9. The system of claim 7, wherein the dummy pattern signal is a signal that changes at least once from a first logic level to a second logic level. 10. The first semiconductor integrated circuit and the second semiconductor integrated circuit are connected to each other via a data line, and the data signal is transmitted from the first semiconductor integrated circuit via the data line to the first semiconductor integrated circuit. The dummy pattern signal is transferred to the first semiconductor integrated circuit via the data line before the data signal is transferred from the first semiconductor integrated circuit to the second semiconductor integrated circuit; 8. The system according to claim 7, wherein the data is transferred to the second semiconductor integrated circuit. 11. A method for reducing skew between a clock signal and a data signal, the method comprising: (a) reducing a first phase difference between a clock signal and a data signal; Receiving the data signal with the first phase difference reduced from a clock signal. 12. The step (a) comprises: (a-1) determining a first delay amount such that a second phase difference between the clock signal and the dummy pattern signal is reduced; (A-2) delaying one of the clock signal and the data signal according to the first delay amount. 13. The step (a) includes: (a-3) a step of further determining a second delay amount such that the first phase difference between the clock signal and the data signal is reduced. The method according to claim 12, further comprising: (a-4) delaying one of the clock signal and the data signal according to the second delay amount. 14. The method of claim 12, wherein the dummy pattern signal is a signal that changes at least once from a first logic level to a second logic level. 15. A method for reducing skew between a clock signal and a data signal in a semiconductor integrated circuit connected to a data line, comprising: Receiving a pattern signal; (b) receiving the data signal via the data line in a second period; and (c) based on a phase difference between the clock signal and the dummy pattern signal. Reducing the phase difference between the clock signal and the data signal.