JPH1165697A - Clock-switching system for cpu - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain clock-switching system of a CPU for guaranteeing the maximum time since the CPU is set to clock stop until the clock actually stops, and making the time longer than a time to execute all the instructions for setting the CPU to a low power consumption mode. SOLUTION: This system is provided with an oscillation circuit 5 which oscillates a high speed clock to be supplied to a CPU 1, a clock setting circuit 2 which outputs a setting change signal from the high speed clock to stop based on the input of a clock setting signal from the CPU, when the present clock state is the high speed clock, a timer 3 which outputs a timer expiration signal after the lapse of a previously set time since the clock stop of the CPU, until the execution of more than one instruction groups for obtaining a low power consumption mode based on the input of the setting change signal, and a clock switching circuit 6 which supplies a high-speed clock from the oscillation circuit 5 to the CPU at normal times, and switches the high-speed clock to a stop, based on the input of the timer expiration signal from the timer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock switching system for a CPU, and more particularly to reducing power consumption and simplifying software.

[0002]

2. Description of the Related Art In recent years, portable devices such as laptop computers and mobile phones have become widespread. Most of them are powered by batteries, which is competing on how to extend battery life. Most of the internal circuits are made of CMOS, and the power consumption increases as the internal signal change increases. Therefore, when there is no processing to be performed normally, the internal clock is stopped to reduce the power consumption. We are trying to reduce it.

In particular, CPUs which are almost always included in such portable devices usually consume large power,
Stopping the clock when there is little processing is a widely practiced technique. In addition, a clock oscillator for a fast clock and a clock oscillator for a slow clock are prepared, and when there is little processing, the oscillator for the fast clock is stopped, and the CPU is operated with the slow clock or the clock is stopped. For example, Japanese Patent Application Laid-Open Nos. 7-20964 and 5-73176 disclose that a high-speed clock oscillator is started by an interrupt signal when the operation of the CPU becomes necessary.
As described above, the CPU and the circuit for generating the clock often exist separately.

[0004] Further, the CPU itself is stopped, and even if the clock is stopped, a slow clock is often used for a clock. This is because when the clock is returned from the stop to the fast clock, it takes time until the oscillation of the fast clock rises, and a slow clock is used to measure the rise time.

Further, there are two known methods for reducing the power consumption of the CPU. One method is to stop an external clock. In this case, a method of externally switching a clock is provided, and the clock is stopped according to the setting from the CPU. The other is a method of setting the CPU itself to a mode with low power consumption. In this mode, the clock inside the CPU is stopped or a part of the power is turned off. Normally, the CPU is provided with an instruction to enter such a mode for reducing power consumption.
For example, assume that the name is a STOP instruction. When this command is executed, the power consumption can be reduced by stopping the clock in the CPU or turning off a part of the power. Further, when this instruction is executed, the next instruction is not executed until an external event such as an interrupt comes. By doing so, access to an external device is not performed. In general, the power consumption of an external device (for example, a RAM or a ROM) rapidly increases when accessed. In some cases, it may be necessary to enter a special CPU mode before executing the STOP instruction. For example, what normally operates in the form of a microprocessor must be changed to single-chip operation. Further, there is a case where an external port or the like is in an output state or a setting of a peripheral circuit is required. In such a case, a plurality of instructions for entering the low power consumption mode are executed, and the last one is a STOP instruction.

[0006]

As described above, the CP
There are often separate circuits for generating U and its clock. At this time, the setting from the CPU to the external clock switching circuit is an independent event from entering the mode with low power consumption inside the CPU. Therefore, if the clock is stopped immediately after the CPU instructs the stop of the clock, the CPU may stop while accessing an external device. In this,
Although the power consumption of the CPU itself decreases, the power consumption increases because the external device remains in the access state.

On the other hand, when an instruction group for putting the CPU into the mode with low power consumption is executed, the operation of the CPU normally stops when the last STOP instruction is executed.
This is to prevent subsequent access to the external device. However, at this time, the oscillator for generating the external fast clock remains operating, so that the power consumption for operating the oscillator is wasted. Also, if an interrupt occurs during execution of an instruction group, it is necessary to perform normal processing after the interrupt, but the clock may be stopped after returning from the interrupt routine. Furthermore, if interrupts are disabled here, STOP
Unless an interrupt occurs after the instruction, the continuation cannot be executed, and the instruction following the STOP instruction cannot be executed forever.

Therefore, the present invention has been made in view of the above points, and guarantees a minimum time from when the CPU clock is stopped to when the CPU clock is actually stopped. It is another object of the present invention to provide a CPU clock switching system capable of reducing power consumption and simplifying software.

[0009]

In order to achieve the above object, a clock switching system for a CPU according to the present invention comprises:
An oscillating circuit that oscillates a high-speed clock as a CPU clock supplied to the PU, and a clock setting signal that indicates a setting change to stop the clock output from the CPU when the current clock state of the CPU is the high-speed clock. A clock setting circuit for outputting a setting change signal from a high-speed clock to a stop, and one or more instructions for setting the CPU to stop the clock based on the input of the setting change signal and then setting a low power consumption mode A timer that outputs a timer expiration signal after a preset time longer than the execution of the group, and a CPU clock that is supplied to the CPU, usually supplies a high-speed clock from the oscillation circuit and expires the timer from the timer. Clock switching circuit that switches from high-speed clock to stop based on signal input Is shall.

Further, the CPU clock switching system of the present invention turns on / off the oscillation of the high-speed clock by the oscillation circuit.
It further includes a high-speed clock oscillation control circuit that controls off,
The timer counts a low-speed clock that is slower than the externally supplied high-speed clock when the timer receives a setting change signal from high-speed clock to stop from the clock setting circuit, and the timer expires when a predetermined count is reached. A signal is output to the high-speed clock oscillation control circuit in addition to the clock switching circuit to stop the oscillation of the oscillation circuit.

[0011] The processing of the CPU in the CPU clock switching system of the present invention includes the step of setting a clock stop for the clock setting circuit, and after setting the clock stop, a timer expiration signal from the timer. Executing one or more instructions for setting the mode to the low power consumption mode before being output.

Further, the clock switching circuit of the CPU clock switching system of the present invention outputs a stop switching signal when switching from a high-speed clock to a stop, and outputs an external interrupt source to the CPU from an external interrupt source before stopping the clock. An interrupt inhibiting circuit that inhibits input of an interrupt signal, and releases input inhibition of an interrupt signal from the external interrupt source to the CPU based on input of a stop switching signal output from the clock switching circuit; and In the processing by the CPU, an interrupt disable setting signal is output to the interrupt disable circuit to inhibit input of an interrupt signal from an external interrupt source before the step of setting a clock stop for the clock setting circuit. It further has steps.

[0013]

FIG. 1 is a block diagram of a clock switching circuit according to the present embodiment. In FIG. 1, 1 is a CPU.
A CPU that operates in response to the supply of the clock 103,
The clock switching circuit 6 generates the CPU clock 103. Specifically, as the CPU clock 103, for example, a high-speed clock 108 of 20 MHz, for example, 3
Either the low-speed clock 106 of 2.768 kHz or the stop 109 is selected. The switching of the CPU clock 103 is performed in consideration of the clock phase so that the CPU clock 103 has no glitch. By default,
The high-speed clock 108 is assumed.

The clock switching operation will be described. First, the CPU 1 sends the external interrupt source 11 to the interrupt prohibiting circuit 7 using the interrupt prohibition setting signal 113.
The CPU 1 is set so that the interrupt signal 112 is not generated even when 1 comes. In such a state, the CPU 1
Sets a clock change in the clock setting circuit 2 through the clock setting signal 100. Generally, the clock setting circuit 2 is in the form of a register. The clock setting circuit 2 is supplied with the current clock state 102 from the clock switching circuit 6, and the clock state 102
Are the high-speed clock 108, the low-speed clock 106, the stop 1
09 is supplied via a 3-bit bus, and only one bit is asserted according to the state of the clock at that time.

When the current clock state 102 is the high-speed clock 108, the CPU 1
When a change to stop is set in the clock setting circuit 2 through 0, the clock setting circuit 2 outputs a clock high speed → stop signal 101. When the timer 3 receives the clock high speed → stop signal 101 from the clock setting circuit 2,
The low-speed clock 106 is counted, and when the count reaches a predetermined count, the timer expiration signal 104 is output to the clock switching circuit 6.
Output to It is assumed that the count number is longer than the execution time for executing one or more instructions for causing the CPU 1 to enter a mode for reducing power consumption. Here, the reason why the low-speed clock 106 is used is that when the CPU 1 is set to stop while operating at the low-speed clock 106, only the low-speed clock 106 can be used because the high-speed clock 108 does not oscillate. .

The high-speed clock oscillation control circuit 4 includes a timer 3
, The high-speed clock oscillation ON / OFF signal 107 is turned off and output to the oscillation circuit 5. In response to this, the oscillation circuit 5 stops oscillation and reduces power consumption. Further, the clock switching circuit 6 receives the timer expiration signal 104 and switches from the high-speed clock 108 to the stop 109 as the CPU clock 103.
This switching timing prevents glitches from appearing in the CPU clock 103. At the same time, the clock switching circuit 6 outputs a stop switching signal 114 to the interrupt inhibiting circuit 7, and the external interrupt source 111 sends the interrupt signal 11 to the interrupt inhibiting circuit 7 as it is.
2 is set to be input to the CPU 1. Thus, the CPU clock 103 stops.

On the other hand, conversely, the CPU clock 10
When switching from the stop 109 to the high-speed clock 108 as 3, the following operation is performed. When the processing must be started as the CPU 1 by pressing a key or by an alarm clock or the like, those signals are integrated and input to the high-speed clock oscillation control circuit 4 as an external event 110. Usually, the external event 110 and the external interrupt source 111 are the same, but there may be different conditions depending on the case. The high-speed clock oscillation control circuit 4 receives this signal, turns on the high-speed clock oscillation 0N / OFF signal 107, and causes the oscillation circuit 5 to oscillate the high-speed clock 108. Normally, a crystal oscillator takes several ms to oscillate. This is measured using the low-speed clock 106. After this time has elapsed, the high-speed clock oscillation control circuit 4 outputs to the clock switching circuit 6 a signal 105 whose oscillator has risen.

The clock switching circuit 6 receives this signal and
High-speed clock 1 from stop 109 as U clock 103
Switch to 08. At this time as well, the CPU clock 103 is switched in consideration of the clock phase so that no glitch appears on the CPU clock 103. When switching to the high-speed clock 108, the clock switching circuit 6 stops the current clock state 102 109
From the state corresponding to the high-speed clock 108.
At this time, the external event 110 and the external interrupt source 111
Are the same signal, the signal from the external interrupt source 111 is input to the CPU 1 as the interrupt signal 112.
When the CPU clock 103 switches to the high-speed clock 108, an interrupt routine is usually executed immediately.

FIG. 2 shows an operation flowchart when the CPU 1 switches the CPU clock 103 from the high-speed clock 108 to the stop 109. First, the CPU clock 10
When the user wants to switch 3 from the high-speed clock 108 to the stop 109, the process comes to START in step 200. Next, the process proceeds to step 201, where the interrupt disable setting signal 113 is sent to the interrupt disable circuit 7 of FIG.
To prevent an interrupt from the external interrupt source 111. This usually takes the form of writing a specific value to a specific register. Next, the process proceeds to step 202, in which the clock setting circuit 2 in FIG. Usually, this is also done by writing a specific value to a specific register.

Further, the process proceeds to step 203, where the CPU 1
Execute (one or more) instructions to place the in a low power mode. The last instruction is a STOP instruction,
When this instruction is executed, the CPU 1 stops executing the instruction until an external event 110 such as an interrupt occurs, and reduces the power consumption inside the CPU 1. This last ST
After the execution of the OP instruction is completed, a timer expiration signal 104 is output from the timer 3 in FIG.
Switch to. Therefore, the oscillation of the high-speed clock 108 and the external clock using the high-speed clock 108 are stopped, and the inside of the CPU 1 also enters the low power consumption mode, so that the power consumption becomes extremely low. After step 203, an instruction to be executed after the clock returns to the high-speed clock 108 is written.

Therefore, according to the present embodiment, the CP
By guaranteeing the minimum time from when the U clock is stopped to when it is actually stopped, the CPU is set to the low power consumption mode during that time, while interrupts are prevented from entering during that time, and the clock is stopped. The power consumption can be reduced and the software can be simplified by automatically allowing an interrupt at the same time as switching to.

[0022]

As described above, according to the present invention, the CPU
An oscillation circuit that oscillates a high-speed clock as a CPU clock supplied to the CPU, and a clock setting signal that indicates a setting change to stop the clock output from the CPU when the current clock state of the CPU is the high-speed clock. A clock setting circuit for outputting a setting change signal from a high-speed clock to a stop, and one or more instructions for causing the CPU to stop the clock based on the input of the setting change signal and then to enter a low power consumption mode And a timer that outputs a timer expiration signal after a preset time longer than that of the timer, and a CPU expiration signal from the timer that normally supplies a high-speed clock from the oscillation circuit as a CPU clock supplied to the CPU. And a clock switching circuit for switching from high-speed clock to stop based on the input of Therefore, when the CPU clock is set to stop, the inside of the CPU is also set to the low power consumption mode, so that the power consumption can be reduced. In addition, software control from the CPU requires such a low power consumption state. It's easy.

In addition, the apparatus further comprises a high-speed clock oscillation control circuit for controlling on / off of high-speed clock oscillation by the oscillation circuit, wherein the timer receives an input of a setting change signal from high-speed clock to stop from the clock setting circuit. When a low-speed clock that is slower than the externally applied high-speed clock is counted and a predetermined count is reached, a timer expiration signal is output to the high-speed clock oscillation control circuit in addition to the clock switching circuit and the oscillation is started. Since the oscillation of the circuit is stopped, the operation of the oscillation circuit is stopped so that power consumption is not wasted.

Further, the CPU sets a clock stop for the clock setting circuit, and after the clock stop is set, enters a low power consumption mode until a timer expiration signal is output from the timer. 1 to do
The step of executing one or more instruction groups can reduce the power consumption of the CPU itself when the clock is set to stop.

Further, the clock switching circuit outputs a stop switching signal when switching from the high-speed clock to the stop, and inhibits the input of an interrupt signal to the CPU from an external interrupt source before stopping the clock. Based on the input of the stop switching signal output from the clock switching circuit, the CP
An interrupt disabling circuit for canceling the inhibition of the input of an interrupt signal to the U, and wherein the CPU sets an interrupt disabling setting signal to the interrupt disabling circuit before the step of setting a clock stop for the clock setting circuit. Is output to inhibit the input of an interrupt signal from an external interrupt source. By disabling the interrupt during the operation of switching to the clock stop, the exception processing as the CPU is reduced, and the control is simplified.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a clock switching system of a CPU according to an embodiment of the present invention.

FIG. 2 is an operation flowchart of a CPU of FIG. 1;

[Explanation of symbols]

 1 CPU 2 Clock setting circuit 3 Timer 4 High-speed clock oscillation control circuit 5 Oscillation circuit 6 Clock switching circuit 7 Interrupt disable circuit

Claims (4)

[Claims] 1. An oscillation circuit for oscillating a high-speed clock as a CPU clock supplied to a CPU, and a clock setting indicating a setting change to stop the clock output from the CPU when the current clock state of the CPU is the high-speed clock. A clock setting circuit that outputs a setting change signal from a high-speed clock to a stop based on a signal input; and a low power consumption mode after the CPU sets the clock to stop based on the input of the setting change signal. 1
A timer for outputting a timer expiration signal after a lapse of a preset time longer than the execution of one or more instruction groups; and a CPU which supplies a high-speed clock from the oscillation circuit as a CPU clock to be supplied to the CPU. A clock switching circuit for switching from a high-speed clock to a stop based on the input of a timer expiration signal from the CPU. 2. A high-speed clock oscillation control circuit for controlling ON / OFF of oscillation of a high-speed clock by the oscillation circuit, wherein the timer receives an input of a setting change signal from high-speed clock to stop from the clock setting circuit. When a low-speed clock that is slower than the externally applied high-speed clock is counted and a predetermined count is reached, a timer expiration signal is output to the high-speed clock oscillation control circuit in addition to the clock switching circuit and the oscillation is started. 2. The CPU clock switching system according to claim 1, wherein the oscillation of the circuit is stopped. 3. The processing in the CPU includes the steps of: setting a clock stop for the clock setting circuit; and setting a low power consumption after the setting of the clock stop until a timer expiration signal is output from the timer. Executing one or more instructions to enter a power mode. 4. The clock switching circuit outputs a stop switching signal when switching from a high-speed clock to a stop, and inhibits input of an interrupt signal from an external interrupt source to the CPU before stopping the clock. The apparatus further includes an interrupt prohibition circuit that releases input prohibition of an interrupt signal from the external interrupt source to the CPU based on the input of the stop switching signal output from the clock switching circuit, and the processing in the CPU includes the following. 4. The method according to claim 3, further comprising a step of outputting an interrupt disable setting signal to the interrupt disable circuit to inhibit the input of an interrupt signal from an external interrupt source before the step of setting the clock stop to the clock setting circuit. CPU clock switching system.