JPH1153528A - Digital image processor and digital image processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an image in which plural images coexist from being read out even when the video timing of an external video input is not matched with that of a video display device in a digital image processor for performing deforming processing to a video input from the outside by using a video memory. SOLUTION: Video memories 11 and 12 for video input storage store the video data of the external video input through a bus switcher 13. A plotter 15 reads out the video data stored in the video memories 11 and 12 for video input storage through the bus switcher 13 and performs deforming processing. The bus switcher 13 is switched only when a flag is set to a swap request flag register 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image processing apparatus for performing a transformation process on an external video input,
More specifically, the present invention relates to a technique for preventing output of an unnatural image in which a plurality of input images are mixed.

[0002]

2. Description of the Related Art In a digital image processing apparatus that performs a transformation process on an external digital video input,
For random access to the input video data, all the video data for one screen is stored in the video memory and then the video data is read. For this reason, double buffering is usually performed using video memory for two screens, and control is performed so that writing / reading to / from the video memory is switched on a screen basis.

[0003]

SUMMARY OF THE INVENTION In a digital image processing apparatus provided with a double-buffered video memory for storing an external video input, the video timing of the image display apparatus for displaying the output of the digital image processing apparatus is determined. If the video timing of the external video input signal to the digital image processing device is out of sync, the switching of the double buffered video memory will occur during the screen display while reading the video memory. Therefore, a plurality of images are read in a mixed state.

For this reason, usually, a system is constructed by combining expensive video equipment which requires external synchronization, or a mechanism for performing synchronization using a field memory or the like is mounted before the double buffer input. In the latter case, the cost of parts becomes higher.

In a digital image processing apparatus for three-dimensional graphics, if complicated drawing is performed, the time required to complete drawing of one screen may be longer than the display time of one screen. In such a case, even if the video timing of the external digital video input matches that of the image display device, an image in which a plurality of input images are mixed cannot be read unless the double buffer switching of the input digital video is suppressed. It is inevitable that they will be issued.

The present invention has been made in view of such a problem, and it is possible to prevent the reading of an image in which a plurality of images are mixed even when the external video input and the video timing of the video display device do not match. It is an object to provide a digital image processing apparatus and method.

Further, the present invention provides a digital image processing apparatus capable of preventing reading of an image in which a plurality of images are mixed, even in an apparatus in which the time required to complete drawing of one screen may be longer than the display time of one screen. And a method.

[0008]

A digital image processing apparatus according to the present invention comprises a plurality of image storage means for storing video data of an external video input, and a video data stored in the plurality of image storage means which is read and transformed. It is provided with a transformation processing device for performing processing, and a flag for requesting switching of a plurality of image storage means, and switching the plurality of image storage means only when this flag is set.

A digital image processing method according to the present invention is characterized in that video data of an external video input is stored in a plurality of image storage means, and when the video data stored in the image storage means is read and subjected to a deformation process, a plurality of image data are stored. A flag for requesting switching of the image storage means is provided, and the plurality of image storage means are switched only when this flag is set.

According to the digital image processing apparatus and method of the present invention, switching of a plurality of image storage units is performed only when a flag requesting switching of the plurality of image storage units is set. That is, after one screen of video data has been written to one of the plurality of image storage units, switching of the plurality of image storage units is performed after the above-described flag is set, and the start point of the next image is set. Then, the writing of the video data is started again. If the next image starts while waiting for the flag to be set, all input video data for one screen is ignored.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a digital image processing apparatus to which the present invention is applied. The digital image processing apparatus 1 performs a transformation process on an external video input and outputs it to a display device.

The digital image processing apparatus 1 includes a video memory 11 (X
Plane) and 12 (Y plane). Then, the video memories 11 and 12 for video input storage are connected to the ports X and Y of the bus switching device 13 by bidirectional bus lines. The video memory 11 for storing video input
And 12 may be housed in separate packages or may be housed in the same package. Further, it may be a separately accessible portion of the screen display video memory 16 described later. Further, in the digital image processing apparatus 1, parts other than the video memory may be constituted by one chip. The bus switching device 13 has four ports A, B, X, and Y.
= X and B = Y, or A = Y and B = X
Can be connected. The port A is connected to the input of the drawing device 15, and the port A is connected to the output of the video input storage video memory controller 14. Therefore, when A = X and B = Y, the output of the video input storage video memory 11 is supplied to the drawing device 15 and the output of the video input storage video memory controller 14 is output to the video input storage video memory 1.
2 is supplied. Conversely, if A = Y and B = X,
The output of the video memory 12 for storing video input and
5 and the output of the video input storage video memory controller 14 is supplied to the video input storage video memory 11.

The video memory for video input / storage 14 stores video data for video input / storage 11,
Write to 12. Further, a video timing signal such as a vertical synchronizing signal is created from an external video input and supplied to the double buffer control unit 19.

The drawing device 15 performs a deformation process by randomly reading each of the video data stored in the video input storage video memories 11 and 12, and writes the video data into the screen display video memory 16. Here, the drawing device 15
Is managed by a command generated by an application running on a computer (not shown). The drawing device 15 generates a drawing end notification each time drawing of one screen is completed, and sends it to the double buffer switching request generation unit 17. Further, it generates a video timing signal of an external display device (image display device) and sends it to the double buffer switching request generation unit 17. The video data written to the screen display video memory 16 by the drawing device 15 is read out in synchronization with the video timing signal of the display device, and supplied to the display device.

Double buffer switching request generator 17
Sets the flag of the swap request flag register 18 (ON) upon receiving the drawing end notification. The drawing end notification may be provided by the application directly to the double buffer switching request generation unit 17. Then, the flag is reset (OFF) at the start of the next screen. Here, the start of the next screen is detected using a video timing signal or using a drawing start command generated by an application.

When the flag of the swap request flag register 18 is set,
When a video timing signal is received from the video memory controller 14 for storing video input, the value of the double buffer switching control register 20 is changed.

Double buffer switching control register 20
Switches the connection state of the bus switching device 13 to A = X and B = Y or A = Y and B = X according to the value of the register. That is, when the register value is "X", A = X and B = Y, and when the register value is "Y", A = Y and B = X.

Next, the operation of the apparatus shown in FIG. 1 will be described.

The video data of the external video input is sent to the port B of the bus switching device 13 via the video input storage video memory controller 14, and the bus switching device 13
Video memory 11 for storing video input according to the connection status of
Or 12. That is, A = X and B = Y
If A = Y and B = X, the video data is stored in the video memory 12 for video input storage.

On the other hand, the drawing device 15 processes the image while reading the video data of the screen already stored in the video input storage video memory 12 or 11, and draws the image on the screen display video memory 16. At this time, A = X,
And if B = Y, video memory 11 for storing video input
From A, and if A = Y and B = X, read from the video memory 12 for video input storage.

In order to be able to store the next image even while the video data of the stored screen is being read, the video memory for storing the video input is double buffered and a bus switching device provided in the middle of the memory bus. 13 enables instantaneous reconnection (replacement of the front and back of the buffer).

FIG. 2 shows an operation algorithm of the double buffer switching request generator 17. First, in step S1, it is determined whether or not the start point of the image is present. If it is the start point of the image, the swap request flag register 18 is reset (OFF) in step S2. Next, when the end of drawing of one screen is detected in step S3, the swap request flag register 18 is set (ON) in step S4.

In this algorithm, it is only necessary to set a double buffer switching request flag (swap request flag) by a method such as register writing at the end of rendering of one screen, and no synchronization processing such as polling is required. The swap request list flag is reset before starting the next drawing. Since this reset can be automatically performed by detecting a video timing signal such as a vertical synchronizing signal or the like, consideration at the program level is not necessarily required.

FIG. 3 shows an operation algorithm of the video memory controller 14 for storing video input and the double buffer control unit 19.

First, the value of the double buffer switching control register 20 is set to "X" (step S11). That is, the connection state of the buffer switching device 13 is set to A = X and B = Y. Next, it is determined whether or not it is the image start point of the external video input (step S12). Whether or not the image is the image start point is determined by detecting a video timing signal of an external video input.

If it is determined in step S12 that it is the image start point, the value of the double buffer switching control register 20 is checked in step S13 (step S1).
3). If the value is "X", it is written into the video memory 11 (X side) for storing video input (step S1).
4) If the value is "Y", write to the video input storage video memory 12 (Y side) (step S15). First, since the value of the double buffer switching control register 20 is set to “X” in step S11, the value is written to the video input storage video memory 11. While writing to the video input storage video memory 11, reading is performed from the video input storage video memory 12, and while writing to the video input storage video memory 12,
Reading is performed from the video memory 11 for video input accumulation.

Video memory 11 or 1 for storing video input
When the writing to image No. 2 is continued and the end point of the image is detected (Yes in step S16), it is determined whether or not the swap request flag register 18 is set (ON) (step S17). That is, it is determined whether or not a switching request has been sent from the double buffer switching request generator 17.

Then, the swap request flag register 18
If it is determined that is set, step S1
The exchange of the double buffer is performed in 8-S20. That is,
In step S18, the value of the double buffer switching control register 20 is referred to.
In step 19, “Y” is set, and if the value is “Y”, step S
At step 20, "X" is set. Thereby, the bus switching device 1
3 is inverted, and the exchange of the double buffer is executed.

As described above, in this embodiment, the buffer exchange is performed after the detection of the double buffer exchange request flag. First, after capturing an image of one screen on the back side (video memory which is not read by the drawing device), wait for the swap request flag register to be set, and after detecting that the swap request flag register has been set, set the front and back sides of the double buffer. The replacement is performed, and the capture of the next image on the back surface is started again. Even if the next image starts while waiting for the setting of the swap request flag, the capture of one screen is skipped because the screen is not captured. For this reason, the drawing apparatus can continuously read the same image as long as the drawing processing continues.

FIGS. 4 to 6 show examples of timings for writing and reading (drawing) to and from the video memories 11 and 12 for storing video input.

FIG. 4 shows a case where the video input is synchronized with the display device. The video input is used for generating the next image with a delay of one screen.

FIG. 5 shows a case where the video input and the display device are synchronized, but the drawing time is longer than the display time of one screen. The video input is also used every other screen in accordance with the display image generation speed. .

FIG. 6 shows a case where the video input is not synchronized with the display device. The video input is written to the memory every other screen, and the same input image is used twice for drawing.

In the above description, the digital image processing apparatus 1 has two video input storage video memories. However, the digital image processing apparatus 1 may have three or more video input storage video memories. Good.

[0036]

As described in detail above, according to the present invention, a synchronized video input enables normal reading without image omission, and also allows a synchronized video input to be used even when video input is not synchronized. In addition, although the update rate of the input image is reduced, it is possible to prevent an unnatural image including a plurality of images from being displayed.

Therefore, the present invention can be applied to a device in which the generation of an effect image is not necessarily completed within an image display time, such as a drawing device using three-dimensional graphics technology. Since the update of the image storage unit is suppressed, it is possible to avoid displaying an unnatural image in which a plurality of images are mixed by continuously using the same input image.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a digital image processing device to which the present invention has been applied.

FIG. 2 is a flowchart showing an operation algorithm of a double buffer switching request generator of FIG. 1;

FIG. 3 is a flowchart showing an operation algorithm of a memory controller and a double buffer control unit for video input accumulation of FIG. 1;

FIG. 4 is a diagram showing an example of timings of writing and reading to and from the video input storage video memory of FIG. 1;

FIG. 5 is a diagram showing another example of the timing of writing and reading to and from the video input storage video memory of FIG. 1;

FIG. 6 is a diagram showing still another example of the timing of writing and reading to and from the video memory for video input storage of FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Digital image processing apparatus, 11, 12 ... Video input / storage video memory, 13 ... Bus switching apparatus, 15 ... Drawing apparatus, 17 ... Double buffer switching request generation part, 1
8: Swap request flag register, 19: Double buffer control unit, 20: Double buffer switching control register.

Claims (4)

[Claims] 1. A digital image processing apparatus for performing a transformation process on an external video input, comprising: a plurality of image storage means for storing video data of the external video input; and a plurality of image storage means for storing the video data of the external video input. A deformation processing device that reads out video data and performs a deformation process; and a flag that requests switching of the plurality of image storage units, wherein the plurality of image storage units are switched only when the flag is set. A digital image processing device characterized by the following. 2. The digital image processing apparatus according to claim 1, wherein the flag is set when the transformation processing apparatus completes the transformation processing of one screen. 3. The digital image processing apparatus according to claim 1, wherein the flag is reset at the time of starting a next screen transformation process. 4. When the video data of the external video input is stored in a plurality of image storage means, and when the video data stored in the image storage means is read out and subjected to a deformation process, switching of the plurality of image storage means is performed. A digital image processing method, wherein a request flag is provided, and the plurality of image storage units are switched only when the flag is set.