JPH114148A - Phase difference detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enlarge the range of phase difference detection between a first digital signal group and the second digital signal group and also to make a circuit whole digital so as to enhance integrated conversion. SOLUTION: The phase difference detecting circuit detects phase difference between the two digital signal groups consisting of a frame pulse, sub-frame pulse and a clock. First and second timing correcting circuits 16 and 18 respectively shift the phases of first and second sub-frame pulses 102 and 105 so as to generate first and second timing correcting outputs 107 and 109. First and second frequency dividing circuits 17 and 19 respectively frequency-divide the first the second frequency-dividing outputs by m (m is an integer more than two) with the first and the second frame pulses 101 and 104 as reference so as to generate first and second frequency-division outputs 108 and 110. A phase comparing circuit 20 detects phase difference between the first and the second frequency-division outputs 108 and 110 so as to generate a phase comparison output 111.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a phase difference detecting circuit for detecting a phase difference between digital signals used in a digital microwave communication device or the like.

[0002]

2. Description of the Related Art A conventional phase difference detecting circuit of this type is disclosed in Japanese Patent Application Laid-Open No. Hei 5-191237 (title of the invention: phase difference detecting circuit). FIG. 5 shows a configuration diagram of this phase difference detection circuit. The phase difference detection circuit comprises a first digital signal group synchronized with each other, a first frame pulse, and a first input clock included in the first frame pulse period. The group includes a second frame pulse having the same configuration as that of the first digital signal group and a second input clock, and detects a phase difference between the first digital signal group and the second digital signal group. Such a phase difference between digital signal groups is obtained by, for example, branching the same digital signal group,
This occurs when the delay amount of the signal propagation path after branching differs.

In the phase difference detection circuit of FIG. 5, a first input clock is input to a first input terminal 1 and a second input clock is input to a second input terminal 2.
When an input clock is input, an exclusive OR circuit (EX-
The waveforms of the output signals of the OR) 6 and the D flip-flop (DF / F) 7 change depending on the phase difference between the input signals. DF
The output signal of / F7 is smoothed by the first integrator 8, and the selection signal is output to the selector 11 by the voltage comparator 9.
A first frame pulse whose phase is synchronized with the first input clock is input to the third input terminal 3, and a second frame pulse whose phase is synchronized with the second input clock is input to the fourth input terminal 4. Either the EX-OR 6 or the output signal of the RS flip-flop 10 is supplied to the selector 11 by a selection signal.
, And smoothed by the second integrator 12 and output to the output terminal 13 as a phase difference output signal.

FIG. 6 is a diagram showing a relationship between a phase difference between a first input clock and a second input clock and a phase difference output signal in the phase difference detection circuit of FIG. In FIG. 6, when the phase difference is in the range of −−１ bit and + ／ bit with respect to 0, the phase difference output signal changes linearly, leading and lagging of the phase (positive / negative of the phase difference), phase difference Both show that the phase difference can be detected well.

[0005]

The phase difference detection circuit according to the prior art described above uses an integration circuit, so that the phase difference signal is an analog voltage, and all circuits cannot be constituted by digital circuits. However, there is a disadvantage that high integration is difficult.

The range of the phase difference which can be detected is ± 検 出.
There is a problem that it is difficult to detect a phase difference even if there is a slight difference in the amount of delay between digital signals. In particular, when the transmission capacity is increased, the period of one bit is shortened, so that it becomes more difficult to detect a phase difference between digital signals.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a phase difference detecting circuit which solves the above-mentioned disadvantages of the prior art, digitizes all circuits, and can detect a phase difference between wide digital signals of several tens of bits. To provide.

[0008]

According to the phase difference detection circuit of the present invention, a first digital signal group synchronized with each other is composed of a first frame pulse and 1 / n of the first frame pulse.
A first sub-frame pulse having a period (n is an even number of 2 or more) and a plurality of first input clocks included between two adjacent first sub-frame pulses;
The digital signal group includes a second frame pulse, a second sub-frame pulse, and a second input clock having the same configuration as the first digital signal group, and the first digital signal group and the second digital signal group A phase difference detection circuit for detecting a phase difference, wherein a first timing correction circuit for shifting a phase of the first sub-frame pulse to generate a first timing correction output; and a first timing correction circuit based on the first frame pulse. When the timing correction output is m (m is 2
A first frequency divider circuit that divides the frequency by the above integer to generate a first frequency divided output, a second timing correction circuit that shifts the phase of the second subframe pulse to generate a second timing corrected output, The second frame based on two frame pulses
A second frequency dividing circuit for dividing the timing correction output by m to generate a second frequency divided output, and a phase for detecting a phase difference between the first frequency divided output and the second frequency divided output to generate a phase comparison output A comparison circuit.

One of the phase difference detection circuits further includes a phase conversion circuit which samples the phase comparison output with the clock corresponding to the first input clock or the second input clock to generate a phase difference output signal in clock units. A configuration can be provided.

In one of the phase difference detection circuits, the phase comparison circuit supplies the first frequency-divided output to a first input terminal and supplies the second frequency-divided output to a second input terminal for output. An inverted output exclusive-OR circuit for generating the phase comparison output at a terminal, wherein the phase conversion circuit supplies the phase comparison output to a first input terminal, and the phase conversion circuit corresponds to the first input clock or the second input clock. It is possible to adopt a configuration that is an inverted output OR circuit that supplies a clock to a second input terminal and generates the phase difference output signal at an output terminal.

In another one of the phase difference detection circuits, the phase comparison circuit supplies the first divided output to a first input terminal and supplies the second divided output to a second input terminal. An exclusive-OR circuit for generating the phase comparison signal at an output terminal thereof, wherein the phase conversion circuit supplies the phase comparison output to a first input terminal and outputs the phase comparison signal to the first input clock or the second input clock. It is possible to adopt a configuration that is an AND circuit that supplies a clock to the second input terminal and generates the phase difference output signal at the output terminal.

Another one of the phase difference detection circuits is such that each of the first and second timing correction circuits inverts the logic of the input clock, and inputs the inverted input clock to a clock input. And a D flip-flop that supplies the subframe pulse to a data input terminal and generates the timing correction output from an output terminal.

Each of the first and second timing correction circuits converts the inputted sub-frame pulse into one.
It is possible to adopt a configuration in which each of the timing correction outputs is generated by shifting by a / 2 pulse width.

[0014]

The phase difference detecting circuit according to the present invention is characterized in that all the circuits are constituted by digital circuits, so that high integration by a semiconductor IC or the like is possible.

Further, since the phase comparison between digital signals is performed using subframe pulses for dividing a frame,
The range of the phase difference that can be detected is several tens of bits or more,
There is an effect that the phase difference can be easily detected even if there is a large difference in the amount of delay between the signals to be compared in phase. This method
Since the number of frequency divisions is smaller than when the clock is frequency-divided and used for phase comparison, there is also an effect that the circuit scale is reduced.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a phase difference detection circuit according to the present invention. FIG. 2 is a timing chart of a digital signal group supplied to the phase difference detection circuit of the present embodiment.

First, before describing the configuration and operation of the phase difference detection circuit of the present embodiment, a group of digital signals supplied to the phase difference detection circuit will be described with reference to FIG. The digital signal group includes a frame pulse, a subframe pulse, and a clock. The frame pulse is a reference for transmitting a digital signal in a digital microwave communication device or the like. When transmitting the signal, a unique signal is added to monitor the quality of the signal to be transmitted. The frame pulse serves as a reference for where the additional signal is. The sub-frame pulse is created by subdividing the period of the frame pulse,
Form a subframe. Normally, the number of sub-frame pulses is n (n is an even number, n
= 4) exists. There are a plurality of clocks in the subframe period. The frame pulse, the subframe pulse, and the clock are synchronized with each other.

The phase difference detection circuit according to the present embodiment splits, for example, the same digital signal group into two digital signal groups and, after branching, passes through the signal propagation paths having different delay amounts. It is used to detect a phase difference between digital signal groups. Therefore, in the future, the digital signal group that has passed through the first signal path is referred to as a first digital signal group, a first frame pulse, a first subframe pulse, and a first input clock, and has passed through the second signal path. The digital signal group is referred to as a second digital signal group, a second frame pulse, a second subframe pulse, and a second input clock. Also, the phase difference detection circuit (a part of the circuit) to which only the signal of the first digital signal group acts is given the title of "first", and the name of the circuit to which only the signal of the second digital signal group acts. The name will be given a “second” crown. It is apparent that the sub-frame pulse in the digital signal group may be generated by period division of the frame pulse immediately before being input to the phase difference detection circuit in FIG. 1 even if it does not exist first. is there.

Referring to FIG. 1, the first timing correction circuit 16 for the first digital signal group in the phase difference detection circuit shifts the phase of the first sub-frame pulse 102 supplied to the fifth input terminal 14. As a result, a first timing correction output 107 is generated. That is, the first timing correction circuit 16 inputs the first sub-frame pulse 102 to the data terminal D of the DF / F 26, and outputs the first input clock 103 supplied to the input terminal 1 to the D terminal via the inverting element 22. −
It is input to the clock terminal C of the F / F 26. Then D-
At the output terminal Q of the F / F 23, a first timing correction output 107 in which the phase of the first sub-frame pulse 102 is shifted by ビ ッ ト bit is generated. This phase shift is a process for preventing a problem in the phase (timing) relationship between the first sub-frame pulse 102 and the first frame pulse 101 in the first frequency dividing circuit 17 described later.
In other words, if the rising point of the first input clock 103 coincides with the change point of the signal of the first frame pulse 101 and the signal of the first subframe pulse 102, the first input clock 10
3, the first timing correction circuit 16 delays the phase of the first timing correction output 107 from the first sub-frame pulse 102 by ビ ッ ト bit (see FIG. 3 described later).

The first frequency dividing circuit 17 uses the first frame pulse 101 supplied to the third input terminal 3 as a reference and converts the first timing correction output 107 supplied from the first timing correction circuit 16 to m (m is The first divided output 108 is divided by (an integer of 2 or more). That is, in the embodiment of FIG. 1, a D flip-flop with reset (RD-F / F) 24 is used as the first frequency dividing circuit 17, the first frame pulse 101 is input to the reset terminal R, and the clock terminal By inputting the first timing correction output 107 to C and connecting the data terminal D and the − output terminal (−Q), the first timing correction output 107 based on the first frame pulse 101 is divided by two. A first divided output 108 is provided at output terminal Q. Since the initial value of the first frequency dividing circuit 17 is determined by the first frame pulse 101, there is no uncertain element of the frequency dividing circuit, and the waveform of the first frequency divided output 108 is always determined for the first frame pulse 101. . Note that the frequency division number may be set to an even number other than 2. Further, as the first frequency dividing circuit 17, a flip-flop with a set-reset or a counter that performs a similar function can be used.

In the phase difference detection circuit shown in FIG. 1, for the second digital signal group, a second timing correction circuit 18 having the same function as the first timing correction circuit 16 is supplied from the sixth input terminal 15 to the second sub-frame pulse 105. Enter the second
The second input clock 106 is input from the input terminal 2 and
A second timing correction output 109 is generated by shifting the phase of the sub-frame pulse 105 by 1/2 bit. Also,
A second frequency divider 19 having the same function as the first frequency divider 17 inputs the second frame pulse 104 from the fourth input terminal 4,
The second timing correction output 10 from the second timing correction circuit 18 is based on the second frame pulse 104.
9 is divided by 2 to produce a second divided output 110.

The first divided output 108 and the second divided output 110
Are compared by a phase comparator 20 using an inverted output exclusive OR circuit (EX-NOR) 28, and the phase comparator 2
0 is the phase difference between the two, that is, the first frame pulse 101
And the phase difference corresponding to the phase difference between the second frame pulse 104 and the phase comparison output 111 are generated (see FIG. 3). A phase comparison circuit 111 using an inverted output OR circuit (NOR) 29 generates a phase comparison output 111 and a phase difference count clock 113 which is an output of the inversion element 22 in the first timing correction circuit 16.
Supplied to Then, the phase conversion circuit 21 takes NOR between the phase comparison output 111 and the phase difference counting clock 113 (samples the “L” level time of the phase comparison output 111 with the clock 113), and outputs the phase comparison output to the output terminal 13. A phase difference output signal 112 having the number of clocks proportional to the “L” level time of 111 is generated. Here, the clock supplied to the phase conversion circuit 21 is a phase difference forming clock 113.
The present invention is not limited to this, and a clock obtained from any place in this circuit may be used.

Note that even if an exclusive OR circuit (EX-OR) is used for the phase comparison circuit 20 and an AND circuit is used for the phase conversion circuit 21 at the same time, the first frame pulse 101 and the second frame pulse 104 The phase difference output signal 112 can be generated with the number of clocks proportional to the phase difference.

FIG. 3 is a signal waveform diagram of each section in the present embodiment. (A) shows the case where the phase difference between the first digital signal group and the second digital signal group is 3 bits, and (b) shows the case where the phase difference is 0.5 bits.

Hereinafter, the operation of the phase difference detection circuit according to the present embodiment will be described in more detail with reference to FIGS.

Referring to FIG. 3A, the first frame pulse 101 and the second frame pulse 104 have a delay difference (phase difference) due to the same signal passing through different transmission paths.
Has occurred. However, since the positions of the frame pulses 101 and 104 are found from the signal being transmitted, the phase relationship between the transmitted digital signal group and the frame pulse 101 or 104 is always constant.
Therefore, the first frame pulse 101 and the second frame pulse 104 are out of phase by the delay difference of the transmission path.

FIG. 3A shows a case where the second frame pulse 104 has a bit number (same as the clock number) and a 3-bit phase lag with respect to the first frame pulse 101. In the figure, the first frame pulse 101, the first sub-frame pulse 102 and the first input clock 103 are synchronized with each other, and the first frame pulse 101 and the first sub-frame pulse 102 are synchronized at the rising edge of the first input clock.
There is a change point. Further, the pulse position of the first sub-frame pulse 102 is located at the pulse position of the first frame pulse 101. This pulse width is 1 bit. The period of the first subframe is 1 / n (n is an even number) of the period of the first frame, and two adjacent first frame pulses 101
There are n first subframe pulses 102 in between.

The first sub-frame pulse 102 and the first input clock 103 are input to a first timing correction circuit 16, which corrects the first sub-frame pulse 102 by one.
The first timing correction output 107 is generated by shifting by / 2 bits. The first timing correction output 107 is input to the first frequency dividing circuit 17 and is divided by 2 after the initial value is determined by another input, that is, the first frame pulse 101. Therefore, the first frequency-divided output 108 divided by 2 is fixed without any uncertainties.

Similarly to the first frequency dividing circuit 17, the second frequency dividing circuit 19 outputs the second timing correction output 109 obtained by shifting the second sub-frame pulse 105 by ビ ッ ト bit to the second timing correcting circuit 18 like the first frequency dividing circuit 17. The frequency is divided by two based on the frame pulse 104, and a second frequency divided output 110 is output.

The phase comparison circuit 20 shown in FIG.
28, the first divided output 108 and the second
When the EX-NOR of the frequency divided output 110 is obtained, a phase comparison output 111 having an “L” level by a phase difference is generated. The phase conversion circuit 21 is composed of a NOR 29, receives the phase comparison output 111 and an inverted signal (phase difference count clock) 113 of the first input clock 103, and performs a NOR operation. Then, when the phase comparison output 111 is “L” and the phase difference forming clock 113 is “L”, the phase difference output signal 1 becomes “H”.
12 is generated at the output terminal 13. As described above, since the “H” pulse is output by the phase difference, the number of “H” pulses becomes three when the phase difference is 3 bits. And the phase difference between the second frame pulse 104 and the second frame pulse 104 can be easily understood.

FIG. 3B shows a case where the phase of the second frame pulse 104 is delayed by 0.5 bit in the number of bits with respect to the first frame pulse 101. When the phase difference is within 0.5 bits, the width at which the phase comparison output 111 becomes “L” is within 0.5 bits, and the phase difference conversion circuit 21 compares the phase comparison output 111 with the inverted signal of the first input clock 101. Therefore, the phase difference output signal 112 has no pulse since there is no overlap of "L".

FIG. 4 is an explanatory diagram of the maximum detectable phase difference in the present embodiment.

The first to sixth rows in FIG. 4 are diagrams in which the first frame period is divided into four first subframes. That is, two adjacent first frame pulses 101
Are equally divided by five second sub-frame pulses 102. For the sake of simplicity, it is assumed that a first input pulse 103 of 10 bits exists in the period of the first subframe. In general, the number of bits in one frame is several hundred bits,
The number of bits of the subframe is several tens of bits. The first timing correction output 107 is the first subframe pulse 102
The pulse has the same period as that of the pulse and is delayed by 1/2 bit. The first divided output 108 is the same as the cycle of the first subframe.

Since the phase difference detection circuit of FIG. 1 detects the phase difference between the first frame pulse 101 and the second frame pulse based on the phase difference between the first divided output 108 and the second divided output 110. Under the conditions up to the sixth row in FIG. 4, the number of clocks (the number of bits) in the first frequency-divided output 108 is the maximum detectable phase difference (in this case, 10 bits). That is, if the phase difference between the first frame pulse 101 and the second frame pulse exceeds 0.5 bits and is within the period of the subframe, it is possible to determine how many bits are different.
An increase in the phase difference can be handled by increasing the number of divisions of the subframe. The first divided output 108 on the seventh row and the second divided output 110 on the eighth row in FIG.
This is an example in which the timing correction output 107 and the second timing correction output 109 are each frequency-divided by 4, and the maximum value of the detectable phase difference is twice the above.

Now, the above-described phase difference will be applied to an actual transmission state. If the distance difference between the coaxial transmission lines is 100 m, the difference between the delay amounts is about 500 ns. If the signal transmission speed is 50 MHz, it is 1 bit / 20 ns, and if the difference in delay amount is 500 ns, the difference is 25 bits.
If the signal transmission speed is 10 MHz, 1 bit is 100
Since it is ns, the difference is 5 bits.

[0037]

As described above, according to the present invention, the first digital signal group synchronized with each other is composed of the first frame pulse and the first frame pulse n (n is an even number of 2 or more).
A second digital signal group is composed of a first sub-frame pulse having a double period and a plurality of first input clocks included in the period of the first sub-frame pulse. The second frame pulse and the second
Consisting of a sub-frame pulse and a second input clock,
A phase difference detection circuit for detecting a phase difference between the first digital signal group and the second digital signal group, the first timing generating a first timing correction output by shifting a phase of the first subframe pulse. A correction circuit, a first frequency-dividing circuit that divides the first timing correction output by m (m is an integer of 2 or more) based on the first frame pulse to generate a first frequency-divided output, A second timing correction circuit that shifts the phase of the frame pulse to generate a second timing correction output, and a second timing correction circuit that divides the second timing correction output by m with respect to the second frame pulse to generate a second divided output. Since the circuit includes a divide-by-2 circuit and a phase comparison circuit that detects a phase difference between the first divided output and the second divided output to generate a phase comparison output, all circuits are configured by digital circuits. , There is an effect that it is easily highly integrated.

Further, the present invention has an effect that a phase difference of several tens of bits can be detected by a digital signal by taking a logical sum of the above-mentioned phase comparison output or a logical product in another modification.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a phase difference detection circuit according to the present invention.

FIG. 2 is a timing chart of a digital signal group supplied to the phase difference detection circuit of the present embodiment.

FIG. 3 is a signal waveform diagram of each section in the present embodiment.

FIG. 4 is an explanatory diagram of a maximum detectable phase difference in the present embodiment.

FIG. 5 is a configuration diagram of a conventional phase difference detection circuit.

FIG. 6 is a diagram illustrating a relationship between a phase difference between a first input clock and a second input clock and a phase difference output signal in the phase difference detection circuit of FIG. 5;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 1st input terminal 2 2nd input terminal 3 3rd input terminal 4 4th input terminal 13 output terminal 14 5th input terminal 15 6th input terminal 16 1st timing correction circuit 17 1st divider circuit 18 2nd timing correction Circuit 19 Second frequency divider 20 Phase comparator 21 Phase converter 22, 25 Inverting element 23, 26 D flip-flop (DF / F) 24, 27 Reset flip-flop (RD-
F / F) 28 Inverted output exclusive OR circuit (EX-NOR) 29 Inverted output OR circuit (NOR)

Claims (6)

[Claims] A first digital signal group synchronized with each other is adjacent to a first frame pulse and a first subframe pulse having a period of 1 / n (n is an even number of 2 or more) of the first frame pulse. A plurality of first input clocks included between the two first subframe pulses,
The second digital signal group includes a second frame pulse, a second subframe pulse, and a second input clock having the same configuration as the first digital signal group, and the first digital signal group and the second digital signal group A phase difference detection circuit for detecting a phase difference between the first and second sub-frame pulses.
A first timing correction circuit for generating a timing correction output, and dividing the first timing correction output by m (m is an integer of 2 or more) based on the first frame pulse to obtain a first timing correction circuit.
A first frequency divider for generating a frequency-divided output, a second timing corrector for shifting the phase of the second sub-frame pulse to generate a second timing-corrected output, and the second timing based on the second frame pulse A second frequency dividing circuit for dividing the corrected output by m to generate a second frequency divided output;
A phase difference detection circuit, comprising: a phase comparison circuit that detects a phase difference between a divided output and the second divided output to generate a phase comparison output. 2. The semiconductor device according to claim 1, further comprising a phase conversion circuit for sampling the phase comparison output with the first input clock or the clock corresponding to the second input clock to generate a phase difference output signal in clock units. 2. The phase difference detection circuit according to 1. 3. The phase comparison circuit supplies the first divided output to a first input terminal and supplies the second divided output to a second input terminal to generate the phase comparison output at an output terminal. An inverted output exclusive OR circuit, wherein the phase conversion circuit supplies the phase comparison output to a first input terminal and supplies the first input clock or a clock corresponding to the second input clock to a second input terminal. 3. The phase difference detection circuit according to claim 2, wherein the phase difference detection circuit is an inverted output OR circuit that generates the phase difference output signal at an output terminal. 4. The phase comparison circuit supplies the first frequency-divided output to a first input terminal and supplies the second frequency-divided output to a second input terminal to generate the phase comparison signal at an output terminal. An exclusive OR circuit, wherein the phase conversion circuit supplies the phase comparison output to a first input terminal, and supplies the first input clock or a clock corresponding to the second input clock to a second input terminal. 3. The phase difference detecting circuit according to claim 2, wherein the AND circuit generates the phase difference output signal at an output terminal. 5. Each of the first and second timing correction circuits is provided with an inverting element for inverting the logic of the input clock, and the inverted input clock is supplied to a clock input terminal, and the subframe pulse is supplied to the clock input terminal. 2. The phase difference detection circuit according to claim 1, further comprising: a D flip-flop supplied to a data input terminal and generating the timing correction output from an output terminal. 6. The timing correction circuit according to claim 1, wherein each of the first and second timing correction circuits shifts the input sub-frame pulse by a half pulse width to generate the timing correction output. Item 6. The phase difference detection circuit according to Item 5.