JPH1140781A - Non-volatile semiconductor memory device array and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: Provided is an array of nonvolatile semiconductor memory devices capable of reducing the size of a cell without causing a program disturb problem, and a method of manufacturing the same. A method of manufacturing a nonvolatile semiconductor memory device includes:
Forming a plurality of second conductivity type bit lines 33a and 33b on the surface of the semiconductor substrate 31;
a, forming a plurality of first lines in a direction perpendicular to the first and second lines, forming a second line between the first lines, removing a part of the first and second lines, and removing each bit. Forming a plurality of program gates 35 and a plurality of floating gates 38 between the lines 33a and 33b;
Forming a plurality of word lines 40 covering a plurality of floating gates 38 in a direction perpendicular to the bit lines 33a and 33b; and connecting a program gate 35 between the bit lines 33a and 33b and
a, forming a plurality of program lines 44 arranged in parallel with 33a and 33b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device, and more particularly to an array of a nonvolatile semiconductor memory device having a cell structure of a simple stacked structure and requiring no metal contact, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Generally, a flash EEPROM (Flash EEPROM) is used.
Electrically Erasable Programmable Read Only Memo
ry) and the effective cell size (effective cell) of a memory cell that determines the degree of integration of a nonvolatile semiconductor memory such as an EEPROM.
l size) is determined by two factors: cell size and cell array structure. The smallest cell structure in a memory cell is a simple stacked-gate structure. Recently, as the application of a nonvolatile semiconductor memory to a flash EEPROM, a flash memory card, and the like has been expanded, research and development on the nonvolatile semiconductor memory have been performed.

A non-volatile semiconductor memory such as a flash EEPROM or an EEPROM is stored on a data storage medium (mass st).
The biggest problem when using it as an orage media is that the cost-per-bit of the memory is very high. In addition, portable (portabl
e) Low power consumption chip for product application
Is required. To lower the cost per bit,
Research on multibit-per-cell has been actively conducted recently.

The degree of integration of a conventional nonvolatile semiconductor memory is
There is a one-to-one correspondence with the number of molycells. On the contrary
Therefore, a multi-bit cell has one or more bits per memory cell.
By storing the above data, the size of the memory cell can be reduced.
Can increase the amount of data stored without reducing
You. To implement multi-bit cells, each memory cell
Three or more threshold voltage levels
 level) needs to be programmed. For example, one
To store 2-bit data in a cell, 2 ^Two=
4, ie, each cell using four threshold voltage levels
Is programmed. At this time, there are four steps of threshold voltage levels.
Bells are logically 00, 01, 10, and 11
Corresponding to the state. The best in multi-level programs
The big challenge is that each threshold voltage level is statistically distributed
This distribution value is about 0.5V.
You. Therefore, adjust each threshold voltage level precisely
More thresholds by reducing the distribution value
Programmable voltage levels stored in one cell
The number of data bits also increases.

As one method for reducing the voltage distribution, there is a method of performing programming while repeating programming and inquiry (verification). In this method,
A series of program voltage pulses are applied to the cell to program the nonvolatile semiconductor memory cell at the desired threshold voltage level. Then, a read operation is performed between each voltage pulse to query whether the cell has reached a desired threshold voltage level. During each query, if the queried threshold voltage level value reaches a desired threshold voltage level value, the programming process is terminated.

[0006] In such a method of repeatedly performing the program and the inquiry, it is difficult to reduce the distribution of the error of the threshold voltage level caused by the finite program voltage pulse width. Further, when an algorithm for repeating the program and the inquiry is implemented in a circuit, there is a problem that the area of the peripheral circuit of the chip increases and the program time increases.

FIG. 1A is a cross-sectional view of a structure of a general simple stacked nonvolatile semiconductor memory device, and FIG. 1B is a symbol of a general nonvolatile semiconductor memory cell. As shown in FIG. 1A, a floating gate 3 is formed on a p-type semiconductor substrate 1 via a tunnel oxide film 2, a control gate 5 is formed on the floating gate 3, and a floating gate 3 is formed between the control gate 5 and the floating gate 3. A dielectric film 4 is formed between them. On the surface of the p-type semiconductor substrate 1 on both sides of the floating gate 3, an n-type source region 6a and a drain region 6b are formed.

In the general simple stacked nonvolatile semiconductor memory cell thus configured, the effective cell size and the coupling constant value of the control gate 5 are small. Therefore, the smaller the size of the effective cell, the smaller the coupling constant. Therefore, in order to prevent the coupling constant from decreasing, the ONO (Oxide Nitri
Although it is conceivable to form the film with a de oxide film, the manufacturing process is complicated and a high annealing process is required.

As shown in FIG. 1B, each nonvolatile semiconductor memory cell includes a floating gate 3 and a control gate for controlling the amount of charge supplied to the floating gate 3 for programming, as described in detail with reference to FIG. 1A. 5
And a field effect transistor for reading (or querying) the amount of charge carriers supplied to the floating gate 3 during programming.

The field-effect transistor includes a floating gate 3, a source 6a, a drain 6b, and a channel region 7 disposed between the drain 6b and the source 6a. In the nonvolatile semiconductor memory cell thus configured, when a voltage sufficient to cause programming is applied to the control gate 5 and the drain 6b, a current flows between the drain 6b and the source 6a. The current is compared with a reference current, and when the current reaches a value equal to or smaller than the reference current, a program completion signal is generated.

Hereinafter, a conventional nonvolatile semiconductor memory device will be described with reference to the drawings. FIG. 2A is a circuit configuration diagram of a conventional nonvolatile semiconductor memory device, and FIG. 2B is a circuit configuration diagram of a conventional nonvolatile semiconductor memory device having a simple lamination structure and requiring no metal contact. FIG. 1 is a circuit diagram of a conventional nonvolatile semiconductor memory device in which a source and a drain are separated and a metal contact is not required.

As shown in FIG. 2A, a plurality of metal bit lines 9 are arranged at a constant gap in a column direction, and a plurality of word lines 10 are arranged in a direction perpendicular to the plurality of metal bit lines 9. One common source line 1 for every two word lines in the same direction as the plurality of word lines 10
1 is arranged. The drains 6b of the two nonvolatile semiconductor memory cells are connected to a metal bit line 9, and the sources 6a of the memory cells are connected to a common source line 11. As a result, one metal contact 8 is required for each of the two cells. Therefore, taking the metal contacts into consideration, the effective size of the memory cell becomes very large. That is, a general nonvolatile semiconductor memory array is composed of cells of the minimum size of a simple stacked structure, but the actual effective size is limited by the pitch of the metal contacts 8.

In order to reduce the number of metal contacts, that is, to realize an ideal array consisting of cells having a simple stacked structure without metal contacts, in an adjacent cell along the program word line direction, It is necessary to solve a problem that a program disturb phenomenon that unselected cells are programmed or erased occurs. FIG. 2B shows an asymmetric channel-separated cell (spl) having an array structure without metal contacts, which can prevent the program disturb phenomenon.
It-channel cell) is shown. In this memory cell array, a selection gate 12 is used. In this case, the disturb phenomenon at the time of programming by hot electron injection is prevented, and the problem of excessive erasure, which is another problem of the cell having a simple stacked structure, is solved.

A non-volatile semiconductor memory cell array as shown in FIG. 2B has a plurality of word lines 10 arranged on a semiconductor substrate (not shown) with a certain gap therebetween.
And a plurality of bit lines 13 arranged in a direction perpendicular to the plurality of word lines 10 so as to form a plurality of squares with a certain gap therebetween, and one square for each square.
And a plurality of nonvolatile semiconductor memory cells arranged one by one.

Each non-volatile semiconductor memory cell in FIG. 2b is provided with a floating gate 3, a control gate 5 for adjusting the amount of charge supplied to the floating gate 3 for programming, and the floating gate 3 during programming. A field effect transistor for reading (or querying) the amount of charge carriers. The field effect transistor has a floating gate 3, a source 6a, a drain 6b, and a drain 6b /
And a channel region 7 located between the sources 6a.

The control gate 5 of each nonvolatile semiconductor memory cell is connected to an adjacent word line 10, and the source 6a of the nonvolatile semiconductor memory cell in one square and the drain 6b of the nonvolatile semiconductor memory cell in the adjacent square are connected. , And the bit line 13. The selection transistor 12 is connected to each bit line 13,
For example, the metal contact 8 is connected to the selection transistor 12 for every 32 or more nonvolatile semiconductor memory cells in the column direction. Therefore, the size of the effective cell can be reduced.

However, also in this case, there is a problem that the size of the unit cell increases due to the gate structure of the selection transistor. In particular, programming using tunneling during low power operation is not possible. This is because, as can be easily inferred from the drawing, two cells adjacent in the direction of the word line 10 receive exactly the same bias condition.

In order to enable a tunnel program,
A cell having a simple stacked structure as shown in FIG.
Arrays without metal contacts have been proposed. That is, a plurality of metal data lines 9 are arranged with a certain gap in the column direction, and a plurality of metal data lines 9 are arranged.
In the same direction as above, bit lines separated from the source line 15 and the drain line 14 are arranged.

The source 6a of the nonvolatile semiconductor memory cell is connected to the source bit line 15, and the drain 6b is connected to the drain bit line 14. One metal contact 8 is connected to each metal data line 9. The control gate 5 is connected to the source bit line 1
5 is connected to a word line 10 orthogonal to the drain bit line 14. However, in the above structure, an increase in the size of the unit cell due to the separation of the bit lines cannot be avoided.

FIG. 3b is a structural sectional view showing a conventional non-volatile semiconductor memory device of a channel separation type having an isolation gate. As shown in FIG. 3B, a p-type semiconductor substrate 1
Floating gate 3 on top of tunnel oxide film 2
Is formed, the control gate 5 is formed on the floating gate 3, and the select gate 17 is formed on the control gate 5, the floating gate 3 and the semiconductor substrate 1 via the insulating film 16. Control gate 5
A dielectric film 4 is formed between the floating gate 3 and the floating gate 3. A source 6 a offset from the floating gate 3 is formed on the surface of the semiconductor substrate 1 on one side of the floating gate 3. Drain 6b is formed on the surface of semiconductor substrate 1.

FIG. 4A is a structural sectional view of a conventional nonvolatile semiconductor memory device of a channel separation type, and FIG. 4B is a structural sectional view of a conventional nonvolatile semiconductor memory device showing a section in a channel width direction.

As shown in FIG. 4A, a conventional non-volatile semiconductor memory device of a channel separation type has a p-type semiconductor substrate 1.
Floating gate 3 on top of tunnel oxide film 2
Is formed, and control gate 5 is formed on floating gate 3. Dielectric film 4 is formed between floating gate 3 and control gate 5. A source 6a offset from the floating gate 3 is formed on the surface of the semiconductor substrate 1 on one side of the floating gate 3, and a drain 6b is formed on the surface of the semiconductor substrate 1 on the other side of the floating gate 3.

In the nonvolatile semiconductor memory device, as shown in FIG. 4B, a field oxide film 18 for insulating cells from one another is formed on the semiconductor substrate 1 with a certain gap in the channel width direction. Gate insulating film 19 is formed on semiconductor substrate 1 between oxide films 18.
The floating gate 3 is formed on the gate insulating film 19 so as to cover a part of the adjacent field oxide film 18.
A dielectric film 4 is formed on a predetermined region of the floating gate 3, and a control gate 5 is formed on the dielectric film 4. A gate cap insulating film 20 is formed on the control gate 5, an insulating film sidewall 21 is formed on both sides of the control gate 5 and the gate cap insulating film 20, and the surface of the field oxide film 18 and the gate cap insulating film 2 are formed.
The erase gate 17 is formed on 0. A tunnel oxide film 22 is formed between the floating gate 3 and the side surface of the adjacent erase gate 17.

[0024]

However, this kind of conventional nonvolatile semiconductor memory device has the following problems.

Although an ideal array of simple stacked cells without metal contacts can provide the smallest effective cell size, in practice the program disturb problem causes such an ideal array. It is difficult to realize a memory cell array.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an array of a nonvolatile semiconductor memory device capable of reducing a cell size without causing a program disturb problem and a method of manufacturing the same. The purpose is to provide.

[0027]

In order to achieve the above object, an array of a nonvolatile semiconductor memory device according to the present invention comprises a floating gate, a control gate, a source / drain region, and a plurality of memory cells arranged in a matrix. A memory cell, a plurality of word lines connected to the plurality of control gates in row units, a plurality of sets of bit lines connected to the source / drain regions in a direction intersecting the plurality of word lines; And a plurality of program lines parallel to the bit lines and assigned to at least one of the bit lines of each set of each memory cell, and floating of two adjacent memory cells connected to each of the program lines. A plurality of program gates capable of programming gates To.

Further, according to the method of manufacturing a nonvolatile semiconductor memory device of the present invention having an array as described above, a plurality of bit lines of the second conductivity type are provided at a constant interval on the surface of the semiconductor substrate of the first conductivity type. Forming a field insulating film, a first conductive layer, and a buffer insulating film on the semiconductor substrate; and forming a field insulating film having a certain gap in a direction perpendicular to the bit line. Forming a plurality of first lines on each of which a conductive layer and a buffer insulating film are stacked; forming a gate insulating film on an exposed region of the semiconductor substrate; and sidewalls of the first conductive layers on the first lines Forming a tunnel oxide film on the gate insulating film between the first lines, forming a plurality of second lines as a plurality of second conductive layers, and forming the first line and the second line on the gate insulating film. A plurality of program gates each comprising a first conductive layer of a first line and a plurality of floating gates each comprising a second conductive layer between each bit line by selectively removing portions of the lines. Forming a gate, forming a dielectric film on the entire surface of the semiconductor substrate including the floating gates, forming a third conductive layer and a cap insulating film on the dielectric film; Selectively removing a part of the conductive layer and a part of the cap insulating film to form a plurality of word lines covering a plurality of floating gates in a direction perpendicular to the bit lines with a constant gap; Forming a sidewall insulating film on both side walls of the line, and forming a contact hole by removing a part of the buffer insulating film disposed on the program gate; Serial is connected to the program gate through the contact hole between each bit line, and characterized in that it comprises a step of forming a plurality of program lines the disposed in parallel with bit lines.

[0029]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing an array of a nonvolatile semiconductor memory device according to an embodiment of the present invention;

FIG. 5A is a circuit diagram of a nonvolatile semiconductor memory device according to one embodiment of the present invention, and FIG. 5B is a cross-sectional view in the channel direction of the nonvolatile semiconductor memory device according to one embodiment of the present invention. FIG. 5C is a cross-sectional view in the channel width direction of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

As shown in FIG. 5A, the nonvolatile semiconductor memory device is supplied to a floating gate 38, a program gate 35 for supplying charges to the floating gate 38 for programming, and a floating gate 38 for programming. A control gate 40 for adjusting the amount of charge, a program current path region for reading (or querying) the amount of charge carriers provided to the floating gate 38 during programming, and a cell region of the nonvolatile semiconductor memory device 45 (see FIG. 6A and FIG. 6B), and a monitor current path region for monitoring a current path between the source and the drain.

As shown in FIGS. 6A and 6B, the non-volatile semiconductor memory device array is an ideal array circuit that does not require metal contacts, and a program line 44 is connected to a program gate 35 of each cell of the array circuit. Is connected. More specifically, the array circuit includes a plurality of EEPROM cells (nonvolatile semiconductor memory elements) 30 arranged in a matrix and having a floating gate 38, a control gate 40, a program gate 35, and a source / drain. . The array circuit is connected to the control gate of each EEPROM cell 30 in the row direction and has a plurality of word lines 40 arranged with a certain gap in the row direction and a plurality of word lines 40 with a certain gap in the column direction. A plurality of bit lines 33a, 33b connected to the source / drain regions so as to be orthogonal to the word lines 40 of the
And one for each cell bit line.
Each of the program lines 44 is connected to a program gate 35. An EEPROM cell 30 is arranged in a nonvolatile semiconductor memory cell area 45 surrounded by each word line 40 and each bit line 33a, 33b. The program gates 35 may be arranged in a matrix, one for each cell, as shown in FIG. 6A, or one program gate 35 between floating gates 38 of two adjacent cells as shown in FIG. 6B. They may be placed and shared. In the case of FIG. 6B, the floating gates 38 of the cells on both sides adjacent to each other can be programmed from the program gate 35.

An example in which a cell and a layout of a nonvolatile semiconductor memory device according to an embodiment of the present invention are embodied on a semiconductor substrate will be described below. FIG. 7 is a layout diagram of an array of a nonvolatile semiconductor memory device according to an embodiment of the present invention, FIG. 8A is a structural cross-sectional view of the nonvolatile semiconductor memory device taken along line II of FIG. 7, and FIG. FIG. 9A is a structural cross-sectional view of the nonvolatile semiconductor memory device taken along the line II-II of FIG. 7, FIG. 9A is a structural cross-sectional view of the nonvolatile semiconductor memory device taken along the line III-III of FIG. 7, and FIG. −
FIG. 4 is a cross-sectional view of the structure of the nonvolatile semiconductor memory element taken along line IV.

As shown in FIGS. 7 and 8A, the word line 40 is connected to the control gate 40 of each cell. (In the present embodiment, since the control gate is formed integrally with the word line, the same reference numeral is used. I do.)
The bit lines 33a and 33b are formed so as to be orthogonal to the word lines 40 and to be formed in the semiconductor substrate 31 with a certain gap or to be concave, and have a conductivity type (N ⁺ ) opposite to that of the semiconductor substrate 31. Having. The program line 44 is arranged in parallel with the bit lines 33a and 33b. The program gate 35 is connected to the word line 4
0 and each cell region 45 are arranged in a matrix.

The structure of each section in the layout diagram of the nonvolatile semiconductor memory device of FIG. 7 will be described in detail. FIG.
As shown in the figure, no contact is formed in the cross-sectional portion on the word line 40, and the diffusion (buried) bit lines 33a, 33
A plurality 3b is formed on the surface of the semiconductor substrate 31 with a certain gap therebetween. Each diffusion bit line 33a,
An isolation oxide film 37 is formed on the diffusion bit lines 33a and 33b along the 33b, and a gate oxide film 37a is formed on the semiconductor substrate 31 between the isolation oxide films 37. A floating gate 38 is formed on a part of the gate oxide film 37a and a part of the isolation oxide film 37, and a dielectric film 39 is formed on the floating gate 38 so as to cover the floating gate 38. A word line (control gate) 40 is formed on the isolation oxide film 37 and the dielectric film 39 so as to cross the floating gate 38. A cap insulating film 41 is formed on the word line 40, and a program line 44 is formed on the insulating film 41 above the floating gate 38 with a gap. 5b and 8
As shown in a, the program line 44 is arranged so as to be parallel to the bit lines 33a and 33b.

As shown in FIGS. 5C and 8B, a gate oxide film 37a is formed on the semiconductor substrate 31 with a predetermined gap, and a floating gate 38 is formed on the gate oxide film 37a. A field oxide film 34 is formed on the semiconductor substrate 31 between the adjacent floating gates 38, a program gate 35 and a tunnel oxide film 37b are formed on the field oxide film 34, and a part of the program gate 35 and a tunnel are formed. Oxide film 3
A buffer oxide film 36 is formed on 7b. Tunnel oxide film 37b is arranged on both side walls of program gate 35, and buffer oxide film 36 is divided into two portions by etching a predetermined portion. On the floating gate 38, a dielectric film 39 is formed.
A word line (control gate) 40 is formed on 9, and an insulating film 41 is formed on the word line 40. On the buffer oxide film 36, sidewall insulating films 43 are formed on both side walls of the insulating film 41 and the word line (control gate) 40. A program line 44 connected to the program gate 35 via a portion etched between the buffer oxide films 36 is formed on the insulating film 41 and the program gate 35.

In the sectional view taken along the diffusion bit line 33a shown in FIG. 9a, isolation oxide films 37 and field oxide films 34 are alternately formed on the diffusion bit line 33a. Field oxide film 34 has a greater thickness than isolation oxide film 37. Word lines 40 are formed on the isolation oxide film 37 at regular intervals.

In the cross-sectional view between the word lines 40 shown in FIG.
3a and 33b are formed with a certain gap (not shown), an isolation oxide film 37 is formed on the bit lines 33a and 33b, and a field oxide film 34 is formed on the entire surface of the semiconductor substrate 31. (Field oxide film 3
4 is not shown in FIG. 9b). Field oxide film 3
4, a program gate 35 is formed with a certain gap, and a program line 44 is formed on a predetermined region on the program gate 35.

Next, a method of manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described with reference to the accompanying drawings. 10a to 9g are cross-sectional views illustrating a manufacturing process of a nonvolatile semiconductor memory device according to one embodiment. In each drawing, the left drawing shows a cross section along the word line 40,
The right drawing shows a cross section along the program line 44.
In the present embodiment, the program gate 35 is formed before the floating gate 38 so that the program gate 35 is located below the floating gate 38. By forming the program gate 35 in this manner, it is possible to perform programming through the side surface of the program gate 35.

As shown in FIG. 10A, a photosensitive film 32 is applied to a p-type semiconductor substrate 31, and the semiconductor substrate 3 is formed at a constant gap.
Exposure and development steps are performed so that
Is selectively patterned. Then, using the patterned photosensitive film 32 as a mask, high-concentration n-type impurity ions are implanted into the exposed surface of the semiconductor substrate 31 at regular intervals to form a plurality of bit lines 33a and 33b. Then, the bit lines 33a and 33b are diffused into the semiconductor substrate 31 by a diffusion process so that the bit lines 33a and 33b fall into the semiconductor substrate 31 or become concave.

As shown in FIG. 10B, the photosensitive film 32 is removed. At this time, in order to prevent the size of the cell from being increased due to the diffusion of the N ⁺ diffusion bit lines 33a and 33b serving as the source / drain to the side surfaces, a high temperature low pressure deposition (HLD) is performed.
After forming the spacer, n-type ions may be implanted to form the bit lines 33a and 33b in a diffusion process.

Next, a first oxide film and a first oxide film are formed on the entire surface of the device.
After sequentially depositing polysilicon and a second oxide film, a photosensitive film is applied, and the first oxide film, the first polysilicon film, and the second oxide film are anisotropically etched in a single photolithography process. Bit line 3
A field oxide film 34, a program gate 35, and a buffer oxide film 36 are formed between 3a and 33b. At this time, the field oxide film 34, the bit lines 33a,
By performing anisotropic etching so that 33b is formed,
A first line including a field oxide film 34, a program gate 35, and a buffer oxide film 36 is formed. At this time, a region excluding the field oxide film 34 (first line) and the N ⁺ bit lines 33a and 33b is used as a channel region.

As shown in FIG. 10C, a gate oxide film 37a and an isolation oxide film 37 are formed on the entire surface of the device by a thermal oxidation process. When performing the thermal oxidation process, the bit lines 33a,
Since impurity ions having a high doping concentration are implanted on 33b, a relatively thick isolation oxide film 37 is formed.
Here, the isolation oxide film 37 sufficiently functions as an etching prevention film for the bit lines 33a and 33b at the time of etching the second polysilicon in a later process. When the thermal oxidation process is performed, the side wall surface of the program gate 35 disposed between the field oxide film 34 and the buffer oxide film 36 is also oxidized, and the tunnel oxide film 37b for programming is formed on the side wall surface of the program gate 35. Is formed. Next, a second polysilicon is formed on the entire surface of the device by vapor deposition so as to fill an active region between the isolation oxide film 37 and the field oxide film 34, and then the field oxide film 34, the program gate 35, and the buffer are etched back. The second polysilicon on the first line made of the oxide film is removed, and as a result, a conductive second line for forming the floating gate is formed only between the first lines.

As shown in FIG.
A mask is arranged between the a and 33b in parallel with the bit lines 33a and 33b, and a part of the first and second lines on the bit lines 33a and 33b is removed by anisotropic etching to form a matrix. Program gate 35 arranged
And a floating gate 38 is formed. Thereafter, a dielectric film 39 is formed above the semiconductor substrate 31 so as to cover the floating gate 38. At this time, the dielectric film 39
Preferably, an oxide film or an oxide film / nitride film / oxide film (ON
O). Then, a third polysilicon and an insulating film 41 are formed on the entire surface of the device by vapor deposition.

As shown in FIG. 11A, by masking the active region between the isolation oxide film 37 and the field oxide film 34,
A part of the third polysilicon and the insulating film 41 is anisotropically etched to form a word line (control gate) 40 orthogonal to the bit lines 33a and 33b. Thereafter, an oxide film is formed on the word line 40 and the insulating film 41 by vapor deposition, and a sidewall spacer 43 is formed on the side surface of the insulating film 41 and the word line 40 by anisotropic etching. Further, the buffer oxide film 36 formed on the program gate 35
Is removed by etching to form a contact hole 42 exposing a predetermined region on the program gate 35.

As shown in FIG. 11B, a polysilicon or metal layer is formed on the entire surface of the device by vapor deposition, is in contact with the program gate 35, and has the bit line 33a,
A portion of the polysilicon or metal layer is anisotropically etched so that one program line 44 parallel to 33b is formed for each bit line 33a, 33b. At this time, the program gate 35 may be formed such that only one program gate is allocated to two nonvolatile semiconductor memory cells. In order to reduce program coupling by the program line 44, the program gate 35 may be used.
May be formed alternately.

The operation of the nonvolatile semiconductor memory device manufactured as described above will be described below. First, the operation of monitoring simultaneously with the program will be described.
Here, in order to perform the program and the monitoring at the same time, the selected cell (see FIGS. 6A and 6B) in the nonvolatile semiconductor memory cell region 45 must satisfy the two conditions of the program operation and the monitoring operation at the same time. The point is that it must be done. That is, since the monitoring operation is the same as the reading operation, the conditions of the program operation and the reading operation must be satisfied at the same time.

In the monitoring operation, the word line 40 and the bit lines 3 orthogonal to the word line 40 are
The condition is that a reading voltage is applied to 3a or 33b. For example, a positive voltage (8V) is applied to the word line 40, a voltage (1V) for sensing is applied to the selected bit line 33a or 33b, and the other bit line 33a or 3 of the selected memory cell is applied.
A ground voltage is applied to 3b. As a result, a monitor current flows through the memory cell via the source and the drain (see FIG. 5A).

In the program operation performed at the same time, the word line 40 and the program line orthogonal to the word line 40 are arranged so that tunneling occurs between the program gate 35 and the floating gate 38 via the tunnel oxide film 37b. The condition is that a bias voltage for programming is applied to 44.

At this time, if the cell is an n-channel type memory cell, the word line 4 is set so that electrons are injected from the program gate 35 to the floating gate 38.
A positive voltage (8V) is applied to 0, and a negative voltage (-8V) is applied to the program line 44. Here, by applying an appropriate voltage to the unselected word line 40 and the program line 44, the disturb phenomenon of the unselected cells can be prevented.

In the erasing operation of the nonvolatile semiconductor memory element of the present embodiment, the gate insulating film 37 of the memory cell is used.
a from the floating gate 38 to the semiconductor substrate 3
The erase operation is performed by moving the electric charge to 1 or the erase operation is performed by moving the electric charge from the floating gate 38 to the program gate 35 through the tunnel oxide film 37b. When erasing is performed on the semiconductor substrate 31, the gate insulating film 37a has a thickness appropriate for tunneling, for example, 1
Preferably, it is formed to a thickness of about 0 nm. In this case, a negative voltage (-8 V) or a ground voltage (0 V) is applied to the word line (control gate) 40, and a positive voltage is applied to the bit line 33a or 33b as a drain. Alternatively, a negative voltage (−8 V) or a ground voltage (0 V) is applied to the word line (control gate) 40 and a positive voltage is applied to the semiconductor substrate 31. In the case where erasing is performed by the program gate 35, since all the programming and erasing are performed by the program gate 35, the operation should be performed in consideration of the reliability or durability of the tunnel oxide film 37b.

[0052]

According to the first and second aspects of the present invention,
Since one program line is formed for each program gate, program coupling between the program gate and the floating gate is reduced, and the cell size can be reduced without causing a program disturb problem.

According to the third aspect of the present invention, it is possible to easily manufacture an array of cells having a high integration degree and a simple stacked structure. According to the fourth aspect of the present invention, the step of forming the bit line can be simplified by forming the bit line in a concave shape on the surface of the semiconductor substrate and using it as the source and drain regions of the cell.

According to the fifth aspect of the present invention, since the tunnel oxide film for programming is formed together with the gate oxide film during the thermal oxidation process, the number of steps in the process can be reduced. According to the invention described in claim 6, the gate oxide film formed on the bit line is thicker than the gate oxide film formed below the floating gate.
The bit line can be protected when a part of the second conductive layer is removed.

According to the seventh aspect of the present invention, since the second line serving as the floating gate is formed by etching back, the process of forming the floating gate and the program gate can be simplified.

According to the invention, program coupling between the program gate and the floating gate can be reduced.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view of a structure of a general simple stacked nonvolatile semiconductor memory device, and FIG. 1B is a symbol of a cell of a general nonvolatile semiconductor memory device.

FIG. 2A is a circuit diagram of a conventional nonvolatile semiconductor memory device, and FIG. 2B is a circuit diagram of a conventional nonvolatile memory device having a simple stacked structure and requiring no metal contact.

FIG. 3A is a circuit configuration diagram of a conventional nonvolatile semiconductor memory device in which a source and a drain are separated and a metal contact is not required, and FIG. 3B is a conventional nonvolatile semiconductor memory device of a channel separation type having an isolation gate. FIG.

4A is a structural sectional view of a conventional non-volatile semiconductor memory element of a channel separation type, and FIG. 4B is a structural cross-sectional view of a conventional non-volatile semiconductor memory element showing a cross section of a in a channel width direction.

5A is a circuit diagram of a unit cell of the nonvolatile semiconductor memory device of the present invention, FIG. 5B is a cross-sectional view of the nonvolatile semiconductor memory device of the present invention in the channel direction, and FIG. FIG. 4 is a cross-sectional view of a semiconductor memory element in a channel width direction.

6A is a first array circuit configuration diagram of the nonvolatile semiconductor memory device of the present invention, and FIG. 6B is a second array circuit configuration diagram of the nonvolatile semiconductor memory device of the present invention.

FIG. 7 is an array layout diagram of the nonvolatile semiconductor memory device of the present invention.

8A is a structural cross-sectional view of the nonvolatile semiconductor memory device of the present invention taken along line II of FIG. 7, and FIG. 8B is a structural cross-sectional view of the nonvolatile semiconductor memory device of the present invention taken along line II-II of FIG. FIG.

9A is a cross-sectional view of the structure of the nonvolatile semiconductor memory device of the present invention taken along line III-III in FIG. 7, and FIG. 9B is a sectional view taken along line IV-IV in FIG.
FIG. 2 is a cross-sectional view of the structure of the nonvolatile semiconductor memory device of the present invention along a line.

FIGS. 10A to 10D are process cross-sectional views of the nonvolatile semiconductor memory device of the present invention.

11A and 11B are cross-sectional views illustrating a process of a nonvolatile semiconductor memory device according to the present invention.

[Explanation of symbols]

 Reference Signs List 31 semiconductor substrate 32 photosensitive film 33a, 33b bit line 34 field oxide film 35 program gate 36 buffer oxide film 37 isolation oxide film 37a gate oxide film 37b tunnel oxide film 38 floating gate 39 dielectric film 40 word line (control gate) 41 insulating film 42 contact hole 43 sidewall spacer 44 program line 45 cell region of nonvolatile semiconductor memory device

Claims (8)

[Claims] A plurality of memory cells each having a floating gate, a control gate, and a source / drain region and arranged in a matrix; a plurality of word lines connected to the plurality of control gates in row units; A plurality of sets of bit lines connected to the source / drain regions in a direction intersecting the word lines of at least one of the bit lines parallel to the plurality of bit lines and in each set of each memory cell. A nonvolatile semiconductor memory device, comprising: a plurality of assigned program lines; and a plurality of program gates connected to the respective program lines and capable of programming floating gates of two adjacent memory cell cells. Array of. 2. The method according to claim 1, wherein the program line is arranged above each memory cell, and the program gate is arranged between floating gates of each pair of memory cells, with two adjacent memory cells as a pair. An array of the nonvolatile semiconductor memory device according to claim 1. 3. A step of forming a plurality of second conductivity type bit lines on the surface of the first conductivity type semiconductor substrate with a predetermined gap therebetween; and forming a field insulating film, a first conductive layer, and Forming a buffer insulating film; and forming a plurality of first lines in which a field insulating film, a first conductive layer, and a buffer insulating film are stacked so as to have a certain gap in a direction perpendicular to the bit line. Forming a gate insulating film on the exposed region of the semiconductor substrate; forming a tunnel oxide film on a side wall of the first conductive layer of the first line; and forming the gate insulating film between the first lines. Forming a plurality of second lines as a second conductive layer on the film; selectively removing each of the first line and a part of the second line to form a second line between each bit line; Is the first line A plurality of program gates comprising a first conductive layer of
Forming a plurality of floating gates each comprising a second conductive layer; forming a dielectric film on the entire surface of the semiconductor substrate including the floating gates; a third conductive layer and a cap on the dielectric film Forming an insulating film; and selectively removing a part of the third conductive layer and the cap insulating film to form a plurality of word lines covering a plurality of floating gates in a direction perpendicular to the bit lines. Forming a side wall insulating film on both side walls of each of the word lines; and forming a contact hole by removing a part of the buffer insulating film disposed on the program gate. A plurality of bit lines connected to the program gate through the contact holes between the bit lines and arranged in parallel with the bit lines; Process and array manufacturing method of the nonvolatile semiconductor memory device characterized by comprising forming a program line. 4. In the step of forming the bit line,
4. The non-volatile semiconductor memory according to claim 3, wherein the bit line is formed so as to be diffused in the semiconductor substrate and become concave after the second conductivity type impurity is injected into the surface of the semiconductor substrate. A method for manufacturing an array of elements. 5. The method according to claim 3, wherein the gate oxide film and the tunnel oxide film are formed simultaneously in a thermal oxidation process. 6. The non-volatile semiconductor device according to claim 3, wherein a gate oxide film formed on the bit line is formed thicker than a gate oxide film formed below the floating gate. A method for manufacturing an array of memory elements. 7. In the step of forming the second line, after forming a second conductive layer so as to fill a space between the first lines, a part of the second conductive layer is removed by etch-back. 4. The method according to claim 3, wherein a second line is formed between the first lines. 8. The non-volatile memory according to claim 3, wherein in the program line forming step, two adjacent bit lines are paired and one program line is formed between the two bit lines. Of manufacturing an array of volatile semiconductor memory elements.