JPH1140777A - Integrated circuit and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit for integrating a memory cell consisting of a MOS transistor and a capacitor with a high density and a large scale using a simple structure. SOLUTION: Bit lines BL1 and BL2 orthogonally cross word lines WL1, WL2, WL3, and WL4 at the cell array of DRAMs, and a DRAM cell consisting of a MOS transistor and a MOS capacitor C are provided near the intersection point. The area between the memory cells is insulated and separated by a trench of a first groove being formed on a semiconductor substrate in a direction in parallel with the word lines WL1, WL2, WL3, and WL4, and by a field shield structure being obtained by burying a capacitive insulation film and field shield electrodes FS1, FS2, and FS3 into the trench. A second trench exists between the memory cells and between field shield structures in parallel with the bit lines, and an insulator is buried here to separate the insulators.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit used as a storage device in which a memory cell comprising a MOS transistor and a MOS capacitor (capacitance element) is provided on a main surface of a semiconductor substrate.

[0002]

2. Description of the Related Art A conventional integrated circuit in which a memory cell composed of a MOS transistor and a MOS capacitor is integrated on the main surface of a semiconductor substrate has a large integration density due to a reduction in the area occupied by the MOS capacitor on the main surface of the semiconductor substrate. An integrated circuit can be realized. A conventional technique for this purpose is a stack capacitor extending above the main surface or a trench capacitor formed by digging a hole called a trench from the main surface. As described in detail in JP-A-5-175448 and JP-A-5-175448, the surface area is increased as a rough surface. In these conventional capacitor structures, the unit memory cell is composed of one MOS transistor and one MOS capacitor, and has an insulating separator between adjacent memory cells. Further reduction in area is required. Prior art for solving this problem is disclosed in Japanese Patent Application No. 8-331.
No. 402, MOS capacitors of adjacent memory cells are formed on both side surfaces of one trench, that is, each trench is shared by adjacent memory cells to realize each MOS capacitor. Was.

[0003]

This prior art significantly improves the integration density of memory cells as compared with the prior art, but is required for electrically stable characteristics because the MOS capacitor electrode area is one side of the trench. In order to obtain a large volume value, it is necessary to form a deep trench, and there is a difficulty in manufacturing. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an integrated circuit in which a memory cell including a MOS transistor and a capacitor is integrated at a high density on a large scale with a simple structure.

[0004]

SUMMARY OF THE INVENTION An integrated circuit according to the present invention comprises:
A memory cell comprising a MOS transistor and a capacitor is arranged in a matrix on one main surface of a semiconductor substrate, the memory cells are insulated and separated from each other, and adjacent capacitors between the memory cells are trenches formed from the substrate surface;
An integrated circuit comprising: a capacitor insulating film buried in the trench; and a fixed potential field shield electrode capacitively coupled to a semiconductor surface on one side of the trench via the insulating film. Is formed. This minute unevenness is, for example, I
EEE Transactions on Elect
ron Devices Vol. 42, no. 2, p
Implemented in spherical surface polysilicon (HSG) technology detailed on pages 295-300. More preferably, the semiconductor substrate is provided with a low-concentration one-conductivity-type epitaxial layer on one surface of a high-concentration one-conductivity-type single-crystal silicon substrate, wherein the trench penetrates the epitaxial layer and the bottom thereof is the high-concentration single-crystal base. The memory cells having a shape extending into the body, the memory cells arranged in a matrix form a memory cell array with bit lines extending in a row direction and word lines extending in a column direction, and the trench extends in parallel with the word line. The memory cells between the trenches extend parallel to the bit lines and are insulated and separated by another trench filled with an internal insulator.

The electric potential of the field shield electrode is a reference electric potential of an externally supplied power supply or the electric potential of the single crystal base. Further, a reverse conductivity type region exists on the surface of the epitaxial layer between one conductivity type in the trench portion, and the reverse conductivity type region has a conductive connection to a drain or a source of the transistor.

According to a semiconductor device of the present invention, in a semiconductor device having a plurality of MOS transistors and a trench capacitor on a main surface of a semiconductor substrate of one conductivity type, the transistors and the capacitors are insulated from each other at the surface. The structure is a field shield structure, and the field shield electrode of the field shield structure and the electrode of the capacitor are the same. Preferably, the trench capacitor has a double diffusion region of one conductivity type semiconductor region diffused from the trench portion and an opposite conductivity type region in the semiconductor region.

[0007]

According to the semiconductor device of the present invention, the gate electrode of the trench capacitor structure is a common field shield electrode for insulation isolation between memory cells. High density integration is possible because the capacitance is formed by the shield electrode. Further, by forming an HSG of phosphorus-containing polysilicon on the inner wall surface of the trench after the trench processing and forming an N-type region on the side surface of the trench by diffusion from the HSG, a MOS capacitor characteristic of a trench structure having an increased surface area can be obtained. . Furthermore, in a structure in which the substrate is formed of a high-concentration P-type single-crystal substrate and a P-type epitaxial layer on the upper surface thereof, and the bottom of the trench reaches the high-concentration substrate, the accumulated charge does not occur at the bottom, so that a very small current leakage occurs. Can be avoided. That is, according to the present invention, the technology of insulating film isolation in the bit line direction, trench field shield in the word line direction, and the wall capacitor formed by the field shield electrode and the semiconductor surface of the trench wall are integrated. Thereby, a high-density large-scale DRAM device is realized. Furthermore,
Since the gate electrode of the trench capacitor is formed in the same process as the field shield electrode, the vertical structure of the integrated circuit is simplified, the characteristics are not degraded due to interlayer interference, and the manufacturing process is simplified, so the cost is high. There are advantages too.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, in order to better understand the above-mentioned features of the present invention, an embodiment of the present invention will be described with reference to the drawings.

FIGS. 1A and 1B are a plan view and a circuit diagram, respectively, illustrating an embodiment of the present invention. As shown in FIG.
In a DRAM cell array, bit lines BL1, BL2 and word lines WL1, WL2, WL3, WL4 are orthogonal to each other, and a DRAM cell comprising a MOS transistor Q and a MOS capacitor C is provided near each intersection. Between each memory cell, word lines WL1, WL2, WL3, W
It is insulated and separated by a trench which is a first groove formed in the semiconductor substrate in a direction parallel to L4 and a field shield structure obtained by embedding a capacitive insulating film and field shield electrodes FS1, FS2 and FS3 in the trench. . In the direction parallel to the bit line, there is a second trench between each memory cell and between the field shield structures, and this is buried with an insulator to perform insulator isolation.

FIG. 1B shows an equivalent circuit of the partial frame a in FIG. 1A. As shown in FIG.
Field shield electrodes FS1, FS2, FS3 extending in parallel with L1, WL2, WL3, WL4 are one electrode of a capacitor of the DRAM cell and are connected to a fixed potential.
The other electrode of the capacitor is a source or drain region extending from the transistor on the side of the trench. Therefore, in the DRAM cell of this embodiment, the capacitors of the DRAM cells adjacent to each other in the bit line direction face both sides of the first trench in which the field shield electrode is buried, via the shared field shield electrode. Isolation zones Z1 and Z2 between memory cells parallel to the word line direction are second trenches filled with an insulator.

FIGS. 2A to 2D are cross-sectional views showing main steps for explaining the manufacturing method according to the embodiment.
Each figure is a cross-sectional view taken along the line bb 'of FIG.
1 are denoted by the same reference symbols. In this embodiment, a P-type epitaxial layer 202 having a specific resistance of 0.5 to 10 Ωcm and a thickness of 1 to 8 μm is formed on one main surface of a high-concentration P-type silicon single crystal substrate 201 having a specific resistance of 0.010 to 0.050 Ωcm. The semiconductor substrate provided is used. As shown in FIG. 2A, silicon dioxide films (SiO ₂ films) 203, 203 ′, and 2 ′ are formed on the main surface of the epitaxial layer 202.
03 "is used as an etching mask to form a trench 204 extending vertically and horizontally in the bit line direction and the word line direction and reaching the high-concentration substrate 201. With the formation of the trench, the epitaxial layer 202 becomes an epitaxial region every predetermined cell formation region. 202 'and 202 ". After the formation of the trench, silicon oxide as an insulator is buried in the trench portion by performing thermal oxidation, vapor phase growth, surface polishing, and the like. Thereafter, the portion of the trench 204 extending in parallel with the word line forming the field shield structure is insulated. Remove objects. Insulators 205 'and 205 "remain in the second trenches 204' and 204" which are divided by the first trench 204 and are parallel to the bit line direction, and perform insulation isolation between memory cells in the word line direction. Another trench isolation band is formed. These trenches 204, 204 ', 20
4 "surrounded by epitaxial regions 202 'and 202".
Constitutes a DRAM cell for every two bits sharing a contact formed in the subsequent steps,
The cell regions are insulated and separated at 204 'and 204 "[FIG. 2 (A)].

FIGS. 2B to 2D show processing steps for forming a capacitor in the trench 204 parallel to the word line direction and from which an insulator has been removed. That is, the trench 20
From the hole of No. 4, the epitaxial region 202 ',
202 ″ to 10 17-19 high-concentration P-type region 20
6 ', 206 "and 1 on the inside which is the respective trench side.
0 to 18 to 20 power high-concentration N-type regions 207 ', 207 "
Is formed by double diffusion, and then a capacitor insulating film 208 is formed in the trench 204. This thermal diffusion method is shown in FIG.
As shown in FIG.
The same polysilicon growth and heat treatment as in the publication are performed to form a rough surface with minute irregularities on the wall surface. In this embodiment, boron is contained at about 10 18 power at the initial stage of polysilicon growth, and then polysilicon containing phosphorus up to about 10 20 power is grown and heat-treated to form irregularities and double formation. Perform diffusion. Polysilicon irregularities p1, p2, p3
.. Have N-type conductivity because the phosphorus concentration is higher than that of boron, and N-type regions 207 ',
207 ".

In the double diffusion P and N regions, the capacitor portion of the DRAM cell is used as a Hi-C cell (Japanese Patent No. 1387295).
), Which are lower in concentration than the high-concentration P-type single-crystal silicon substrate 201, so that the P-type regions 206 ′ and 20
Both the 6 ″ and the N-type regions 207 ′, 207 ″ remain on the side surfaces of the trench 204 in the epitaxial regions 202 ′, 202 ″, and the base 201 reaches the bottom surface of the trench 204.
Terminates at the interface between the surface of the semiconductor device and the epitaxial regions 202 'and 202 ". The capacitor insulating film 208 is an ONO film having a three-layer structure of a silicon dioxide film 209-a silicon nitride film 210-a silicon dioxide film 211 (Japanese Patent No. 1235264). The effective film thickness in terms of a silicon dioxide film is controlled at 30 to 100 °.

Next, as shown in FIG. 3A, an inner groove of the capacitor insulating film 208 of the trench 204 is filled with polysilicon containing phosphorus to form a field shield electrode 212 extending in the word line direction. The field shield electrode 212 forms the MOS capacitors of the adjacent memory cells with the N-type regions 207 and 207 'on both sides of the trench and the insulating film 208 interposed therebetween, and also forms the epitaxial regions 202' and 202 ". The substrate 201 to be insulated and separated from the insulating film 208 form an insulating separation band having a field shield structure, and are connected to a fixed potential (predetermined power supply potential, GND or substrate potential) in the integrated circuit.
Therefore, the field shield electrode 212 is also a common electrode of the MOS capacitors of the adjacent memory cells of the epitaxial layers 202 'and 202 "which are insulated from each other.

On the main surfaces of the epitaxial regions 202 'and 202 ", the gate structure of the MOS transistor is formed by the silicon dioxide gate insulating films 213, 213' and 213" and the polycrystalline silicon word lines WL1 and WL2, respectively. Formed on the surfaces of the P-type epitaxial regions 202 'and 202 "on both sides of the word lines WL1 and WL2.
N-type diffusion regions 214 and 21 each having a depth of 0.1 μm by arsenic implantation and diffusion serving as drain and source regions of an OS transistor.
4 ', 215 and 215' are provided. N-type region 21 on one field shield structure side of each transistor
4, 214 'operate as one electrode of a capacitor and are connected to N-type regions 207' and 207 "in this embodiment. The other N-type regions 215 and 215 'are the same epitaxial regions 202' and 215 ', respectively. 202 "shared with the MOS transistor of the adjacent DRAM cell
This is a contact region to the bit line in the mold region. The contact region is formed of an insulating film 216, 217, 21 on the diffusion region of the field shield structure transistor and the word line.
After the formation of 8,219, the surfaces of the N-type regions 215, 215 'are exposed.

FIG. 3B shows a final step of this embodiment, in which a thick interlayer insulating film 220 of phosphorus-boron-silicate glass (BPSG) is deposited on the main surface, and the contact protection films 221 and 222 are formed. Phosphorous plugs and ions are implanted into the inner opening, the conductive plugs 223, 223 'formed by laminating titanium-titanium nitride-tungsten are buried, and wiring is further processed with aluminum to form the bit line BL1. These wiring forming processes are known in the art, and the N-type region 21 is formed by plug ion implantation.
5,215 'are provided with high-concentration N-type regions 224,224' due to the intrusion of phosphorus from plugs 222,222 '.
Improve current path characteristics between AM cells and bit lines. The MOS transistors Q ₁₁ and Q ₂₁ and the MOS capacitors C ₁₁ and C ₂₁ forming the field shield structure in FIG.
(B), MOS transistors Q ₃₁ and Q ₄₁ are formed in epitaxial regions 202 ′ and 202 ″ sharing N-type regions 215 and 215 ′, respectively, and bit lines B
Connected to L1.

According to the above-described embodiment, since the capacitor of the DRAM cell is formed on one side surface of the trench 204 in which the field shield electrode 212 is buried, and the side surface has a minute uneven surface formed by the so-called HSG technique. In a trench having an epitaxial region width of 1 μm and a depth of 7 μm, a capacitor area of 14 square microns or more, which is two to three times the normal area, is obtained, and a sufficient storage capacity as a DRAM cell is realized. Therefore, the DRAM cell structure of the present invention has a simpler structure and manufacturing method than the conventional cell structure, has a small cell size, improves the integration density, realizes a large-scale integrated circuit, and increases the capacitance value of the MOS capacitor. DRAM with stable operation is realized.

In this embodiment, a P-type epitaxial layer 202 is formed on a high-concentration P-type silicon single crystal substrate 201.
And an epitaxial region 20 for accommodating a DRAM cell by reaching the bottom of the trench to the base 201.
Since the 2 ', 202 "is insulated and isolated, there is no formation of a charge storage layer or a current leakage path at the bottom of the trench caused by the conventional trench isolation, the information retention time characteristic of the DRAM cell is improved, and the leakage current between active regions is reduced. In addition, it is possible to eliminate a malfunction and an increase in standby current.In addition, in this embodiment, a design rule is adopted in which the insulating separation band of the word line is designed with an insulating separating band and the intersection with the field shield electrode is avoided. As a result, the word line and the field shield electrode can be formed by the same polycrystalline silicon processing step, that is, the so-called single-layer polysilicon process, which further simplifies the manufacturing process and improves the economic efficiency. In the embodiment, the field shield electrode and the word line are formed of polycrystalline silicon. However, tungsten silicide, refractory metal, etc. It can be implemented in a laminated structure with single or polycrystalline silicon.

In this embodiment, the field
The potential of the shield electrode is fixed to the reference potential (GND) of the power supply, the base potential (Vbb), or an intermediate potential between the power supply potential and GND. However, when the field shield electrode is fixed at the power supply potential (Vcc), electron charges are induced on the side surface of the P-type epitaxial region facing the field shield electrode, and the N-type MOS transistor has a source or drain N-type. In order to form an inversion layer that is electrically coupled to the
It is possible to omit both the N-type region and the N-type and P-type regions formed by diffusion from the trench wall surface serving as the counter electrode of the shield electrode.

Further, in this embodiment, the word line and the field shield electrode are formed in separate steps, but the word line and the field shield electrode are interconnects extending in parallel and mainly composed of polysilicon. It is also possible to form with.

Although the embodiments of the present invention have been described above, the present invention allows the material and conductivity type of each step to be changed as necessary. Therefore, the technical scope of the present invention is as described in the above embodiments. The present invention is not limited to this, and the patent right for this invention extends to all the semiconductor devices described in the claims.

[0022]

According to the semiconductor device of the present invention, the gate electrode of the trench capacitor structure is a field shield electrode common to the insulation isolation between the memory cells, and one side having a small HSG of the trench structure and the field shield are formed. Since the capacitance is formed by the electrodes, high-density integration is possible. Also,
By forming an HSG of polysilicon containing phosphorus on the inner wall surface of the trench after the trench processing, and forming an N-type region on the side surface of the trench by diffusion from the HSG, a MOS capacitor characteristic of a trench structure having an increased surface area can be obtained. Furthermore, in a structure in which the substrate is formed of a high-concentration P-type single-crystal substrate and a P-type epitaxial layer on the upper surface thereof, and the bottom of the trench reaches the high-concentration substrate, the accumulated charge does not occur at the bottom, so that a very small current leakage occurs. Can be avoided.

Further, since the gate electrode of the trench capacitor is formed in the same step as the field shield electrode, the vertical structure of the integrated circuit is simplified, the characteristics are not degraded by interlayer interference, and the manufacturing process is simplified. Therefore, there is also an advantage of high economic efficiency.

[Brief description of the drawings]

FIG. 1 is a plan view and a circuit diagram illustrating an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating each processing step in one embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating each processing step in one embodiment of the present invention.

[Explanation of symbols]

WL1, WL2, WL3, WL4 word lines BL1, BL2 bit line FS1, FS2, FS3 field shield electrode _{C 11, C 12, C 21} , C 22 capacitors _{Q 11, Q 12, Q 21} , Q 22, Q 31, _{Q 32, Q 41, Q 42} M
OS transistor Z1, Z2 Trench

Claims (13)

[Claims] A memory cell comprising a MOS transistor and a MOS capacitor is arranged in a matrix on one main surface of a semiconductor substrate, the memory cells are insulated from each other, and capacitors adjacent to each other between the memory cells are separated from the surface of the substrate. An integrated circuit, comprising: a side surface of the formed isolation trench; and a field shield electrode capacitively coupled to the semiconductor surface on the side surface via a capacitance insulating film buried in the trench. An integrated circuit, characterized by having a rough surface. 2. The integrated circuit according to claim 1, wherein said rough surface is formed by crystal grains of polycrystalline silicon forming a trench surface provided in said semiconductor substrate. 3. The integrated circuit according to claim 2, wherein said polycrystalline silicon contains phosphorus and is electrically connected to a surface of said one side semiconductor substrate on one side and to a region of a reverse conductivity type of a drain or a source of said transistor. An integrated circuit, wherein a reverse conductivity type region is formed. 4. The integrated circuit according to claim 1, wherein said semiconductor substrate is provided with a low-concentration one-conductivity-type epitaxial layer on one surface of a high-concentration one-conductivity-type silicon single-crystal substrate, and said trench is formed in said semiconductor substrate. An integrated circuit having a shape extending from a surface of an epitaxial layer into the high-concentration one-conductivity-type silicon single-crystal substrate. 5. The integrated circuit according to claim 1, wherein the memory cells arranged in rows and columns are bit lines extending in a row direction and word lines extending in a column direction.
Forming an array, wherein the trenches extend parallel to the word lines, and the memory cells between the trenches extend parallel to the bit lines and are insulated and separated by other trenches filled with an internal insulator. Integrated circuit. 6. The integrated circuit according to claim 1, wherein the potential of said field shield electrode is a potential of a power supply supplied from outside. 7. The integrated circuit according to claim 1, wherein the electric potential of said field shield electrode is a reference electric potential of a power supply supplied from the outside. 8. The integrated circuit according to claim 1, wherein the potential of said field shield electrode is the potential of said silicon single crystal base. 9. The integrated circuit according to claim 4, wherein a double diffusion region of one conductivity type region and a reverse conductivity type region is provided on one side surface of the epitaxial layer. An integrated circuit, wherein the region has a conductive connection to a drain or a source of the transistor. 10. A MOS transistor and a MOS capacitor are used as memory cells. The memory cells are insulated and separated from each other, and the adjacent MOS capacitors are formed on the side surfaces and the side surfaces of a trench dug from the main surface of the one conductivity type substrate. A method of manufacturing an integrated circuit in which a field shield electrode is insulated and separated via an insulating film, wherein polycrystalline silicon having a rough surface containing phosphorus is deposited on the side surface of the trench after the formation of the trench. Manufacturing method. 11. The method for manufacturing an integrated circuit according to claim 10, wherein said field shield electrode and said MOS are provided.
A method for manufacturing an integrated circuit, wherein a word line serving as a gate electrode of a transistor is formed in the same step. 12. The integrated circuit manufacturing method according to claim 11, wherein said field shield electrode and said word line are wiring materials containing polycrystalline silicon formed in the same step. Production method. 13. The method for manufacturing an integrated circuit according to claim 10, wherein said semiconductor substrate is a low-concentration one-conductivity-type silicon epitaxial layer on one main surface of a high-concentration one-conductivity-type silicon single-crystal substrate. Forming an integrated circuit.