JPH11352916A - Display device - Google Patents

Abstract

(57) Abstract: To reduce or eliminate EMI noise emitted from a PDP display device and noise propagating in the PDP display device. SOLUTION: An input terminal of a scan electrode control signal generator 2 and an output terminal OT of a display control unit 1 for outputting a display start instruction signal k.
1A is connected via a signal line 72, and the output terminal of scan electrode control signal generator 2 and the input terminal of scan electrode driver 52 are connected via signal line 82. Scan electrode control signal generator 2 and scan electrode driver 52 are arranged close to each other. The display start instruction signal k includes a start signal RST and a reference clock signal j1, and the signal line 72 includes two signal lines transmitting the signals k and j1. An input terminal of the address electrode control driver 54 and an output terminal OT for outputting the composite address data d
2 are connected via a signal line 84. The ground line of the signal line 84 is grounded via the switch 11. The switch 11 is turned on only during the address period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a display device, and more particularly to a technique for reducing noise emitted and propagated in the display device.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing an example of the configuration of a PDP display device described in FIG. 9 of JP-A-7-160218. As shown in FIG. The display control unit 50P, the PDP display unit 55P, the video processing unit 70P, and the power supply circuit 56P are roughly classified.

As shown in FIG. 10, a video processing unit 70P
Receives analog video signals r, g, b, horizontal synchronizing signal h, and vertical synchronizing signal v as input signals, performs predetermined processing on these signals, and performs digital image data R, G, B (hereinafter simply referred to as “ Image data R, G, and B), a clock signal T, a horizontal synchronizing signal H, and a vertical synchronizing signal V, and output these.

FIG. 11 shows an example of a specific configuration of the video processing section 70P. In FIG. 11, for example, regarding the analog video signal r, the amplifier 65Pa amplifies the analog video signal r input from the preceding-stage circuit (not shown) at a predetermined magnification and outputs the amplified signal. The analog / digital (A / D) converter 66Pa converts the amplified analog video signal r, which is an input signal, into image data R and outputs it. Similarly,
Amplifier 65Pb, 65Pc and analog / digital (A /
D) The analog video signals g and b, which are input signals, are converted into digital image data G and B by the converters 66Pb and 66Pc, respectively. Then, the image data R,
G and B are input to the video processor 67P and output after being subjected to various processes for improving image quality.

[0005] Further, the video processor 67P receives the horizontal synchronizing signal h and the vertical synchronizing signal v as input signals, converts them into digital signals, and generates and outputs a horizontal synchronizing signal H and a vertical synchronizing signal V. At the same time, the video processor 67P restores and outputs the clock signal T based on the horizontal synchronization signal H in a PLL circuit (not shown) in the video processor 67P.

Thereafter, as shown in FIG. 10, each of the above image data R, G, B, horizontal synchronizing signal H, vertical synchronizing signal V
And the clock signal T are input to the display control unit 50P.

[0007] The display control unit 50P includes input image data R, G, and B, a clock signal T, a horizontal synchronization signal H,
Based on the vertical synchronizing signal V, a scan electrode control signal a, a common electrode control signal c, and composite address data d to be described later are generated and output.

FIG. 12 is a block diagram showing an example of a specific configuration of the display control unit 50P. The outline of the signal processing in the display control unit 50P will be described with reference to FIG.

First, a timing signal generator 60P shown in FIG. 1 receives a clock signal T, a horizontal synchronizing signal H and a vertical synchronizing signal V as input signals, and outputs a timing signal of each block (video display frame). A start signal RST indicating the head and count frequencies (or reference clock signals) j1 and j2 are generated and output.

The counter 61P receives the start signal RST.
And count frequency j1 as an input signal, counts and outputs a counter value j3 from zero.

The first ROM 62P stores in advance a signal waveform for one frame of a predetermined control signal d2 for controlling the address electrode. The first ROM 62P receives a 5-bit signal corresponding to a counter value j3 as an input signal. Is read out.

Similarly, a 15-bit scan electrode control signal a corresponding to a counter value j3 as an input signal is read from the second ROM 63P. From the third ROM 64P, a 15-bit common electrode control signal c corresponding to the counter value j3 as an input signal is read. In addition, as for the range of the value of the counter value j3 which is the address signal, j1 =
If 10 MHz and one frame = 1666.66.7 μsec, 0 ≦ j3 ≦ 166667.

The data converter 57P receives the image data R, G, and B as input signals, and in one frame,
The image data R, G, and B each consisting of 10 bits are converted into ten bit plane data, and the bit plane data is stored (stored) in one of the first memory 58P and the second memory 59P. I do. Such first and second
The memories 58P and 59P each have a 15-bit control line 8
5P and 48-bit data lines 86P are provided.
Operated at double speed.

Next, in the subsequent frame, the data converter 57P reads the bit plane data stored in the previous frame from the first or second memory 58P, 59P, and sequentially performs a predetermined process on the data, It generates 80-bit address data d1 and outputs it.
The address data d1 is combined with the above-described predetermined control signal d2 for controlling the address electrodes to form the combined address data d.

At this time, the data converter 57P alternately repeats the above-mentioned storage processing and readout processing for the first and second memories 58P and 59P for each video display frame unit, thereby obtaining image data R and G. , B are processed continuously.

The data converter 57P converts 48-bit data read at the cycle of the clock signal T into data having an 80-bit width, and outputs the data at a cycle that is half the cycle of the clock signal T. Has also been implemented.

With the above processing, the display control section 50P outputs the composite address data d, the scan electrode control signal a, and the common electrode control signal c.

The PDP 51P in the PDP display section 55P shown in FIG. 10 includes a plurality of scanning electrodes, a common electrode paired with each of the plurality of scanning electrodes, and formed in parallel with each other. And address electrodes formed in a direction perpendicular to the vertical direction. The PDP 51P shown in FIG.
The illustration of the three electrodes is omitted in FIG.

Then, as shown in FIG.
Scan electrode driver 52 to which predetermined voltage e is supplied from 6P
P generates and transmits / receives various signals, converts the amplitudes of various signals using the above-described scan electrode control signal a as an input signal, and supplies a predetermined voltage to a scan electrode connected to its output terminal.

Similarly, a predetermined voltage i is supplied from the power supply circuit 56P.
Is supplied to the common electrode driver 53P using the common electrode control signal c as an input signal and the power supply circuit 56P.
Address electrode driver 54 to which a more predetermined voltage f is supplied
P receives the composite address data d as an input signal,
Generates and transmits / receives various signals, performs amplitude conversion of various signals,
Further, a predetermined voltage is supplied to a common electrode or an address electrode connected to each output terminal.

As described above, when a predetermined voltage is applied to each electrode of the PDP 51P, discharge and light emission occur in each light emitting cell of the PDP 51P, and the image data R,
A full-color display image based on G, B (or analog video signals r, g, b) is displayed.

[0022]

In the conventional PDP display device having the above-mentioned structure, the scanning electrode control signal line 82P and the common electrode control signal line 83P are each composed of 15 lines, and the composite address data line 84P is 85 lines. Since it is composed of a single line, the number of lines connecting the display control unit 50P and the PDP display unit 55P is very large. Therefore, (i) the number of parts such as leads and connectors required for connection between the display control unit 50P and the PDP display unit 55P is large, and (ii) P
There is a problem that the volume of the DP display device becomes large.

Further, the PDP display device is often used as a large screen display device of 40 to 70 inches, and in such a large PDP display device, as the size increases, the signal lines 82P, 83P, 84P become larger. (Iii) The signal lines 82P, 83P, 84P
The problem is that the emission of EMI noise (electromagnetic interference noise) from the device becomes significant.

On the other hand, in the conventional PDP display device, (i
v) When switching noise or discharge noise generated in the PDP display unit 55P propagates to the video processing unit 70P via the ground lines of the signal lines 82P, 83P, 84P and causes interference with the analog video signals r, g, b. There is. For this reason, in the conventional PDP display device, there is a problem that the display quality of the PDP 51P is deteriorated due to the interference. In order to reduce the above noise, an electric noise filter or a filter with a built-in metal mesh may be used. However, according to such a measure, further reduction in cost and price of the PDP display device is hindered. I will.

As described above, in the conventional PDP display device,
The performance at the time of driving may be affected by noise emitted from the internal wiring itself or noise propagating through the wiring.

Such a problem is that, regardless of the PDP display device, a signal for driving the display panel is generated from external video data or a clock signal, and the drive signal and various timing signals are sent to the display section of the display panel. It can be said that this is also a problem that can occur with respect to other display devices to be transmitted.

Therefore, the present invention provides the above problems (i) to (i).
(Iv) has been made to solve
A first object is to provide a display device in which emission of noise is reduced or eliminated.

A second object of the present invention is to provide a display device in which the switching noise and the discharge noise propagating from the display unit to other components are reduced and eliminated while realizing the first object. Aim.

[0029]

(1) A display device according to the first aspect of the present invention includes a timing signal generator, and outputs a display start instruction signal generated by the timing signal generator from a first output terminal. A display control unit that generates a second electrode control signal based on the input image data signal and outputs the generated signal from a second output terminal; and at least a first electrode and a second electrode; A display panel in which a light emitting cell is defined by an electrode and the second electrode; a first input terminal; a first electrode connected between the first input terminal and the first electrode to generate a first electrode control signal; A drive unit, a second input terminal, and a display unit having a second electrode drive unit connected between the second input terminal and the second electrode; and a first output terminal of the display control unit. The first input terminal of the display unit is connected to a first signal line via a first signal line. It is connected, characterized in that it is connected via a second signal line and the second input terminal of the display unit and the second output terminal of the display control unit.

(2) The display device according to claim 2 is:
2. The display device according to claim 1, wherein the first electrode driver includes a first electrode control signal generator and a first electrode driver arranged close to each other, and wherein the first electrode driver is provided. 3. The first input terminal of the first electrode control signal generator is connected to the input terminal of the first electrode control signal generator, the output terminal of the first electrode drive unit is connected to the first electrode of the display panel, the first electrode An output terminal of the control signal generator is connected to an input terminal of the first electrode driver via a third signal line including a plurality of signal lines.

(3) The display device according to claim 3 is:
3. The display device according to claim 2, wherein the first electrode control signal generator includes a transmitter that generates and outputs a reference clock signal, and the display start instruction signal includes only a start instruction signal. 4. It is characterized by.

(4) The display device according to claim 4 is:
3. The display device according to claim 2, wherein the display start instruction signal includes a start instruction signal and a reference clock signal.

(5) The display device according to claim 5 is:
The display device according to claim 1, wherein:
The first signal line is made of an optical transmission medium, a light emitting device is provided at the first output terminal of the display control unit, and a light receiving device is provided at a first input terminal of the display unit. And

(6) The display device according to claim 6 is:
2. The display device according to claim 1, wherein a ground line of the first signal line or the second signal line is grounded via a predetermined switch, and the predetermined switch is connected to the first signal line or the second signal line. The closed state is controlled only during a period in which a predetermined signal is transmitted to the two signal lines.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, a three-electrode AC surface discharge type plasma display panel display device (hereinafter simply referred to as "PDP display device") is used as an example of a display device.
Each embodiment of the present invention will be described.

(Embodiment 1) FIG. 1 shows Embodiment 1 of the present invention.
1 is a block diagram schematically showing the overall configuration of a PDP display device according to the present invention. As shown in FIG. 1, in the present PDP display device, the output terminal of the video processing unit 70 is connected to the input terminal of the display control unit 1, and the output terminals OT1A and OT1 of the display control unit 1 are connected.
B, OT2 are input terminals IT1A, IT1 of the PDP display unit 4.
1B, IT2. And each block 7
0, 1, and 4 are connected to a power supply circuit 56,
From 6, a predetermined power is supplied to each block.

The following describes each block 7 of the present PDP display device.
The features of 0, 1, and 4 will be clarified by describing the configurations in detail.

(Video Processing Unit 70) First, the video processing unit 70
Are input with analog video signals r, g, b, a horizontal synchronizing signal h, and a vertical synchronizing signal v. These signals are subjected to predetermined processing, and digital image data R, G,
B (hereinafter simply referred to as "image data R, G, B"), a clock signal T, a horizontal synchronizing signal H, and a vertical synchronizing signal V, and output these signals R to V. Main video processing unit 7
0 corresponds to a conventional video processing unit 70P (see FIG. 11), and the same unit 70P can be used in the present embodiment.

(Display control unit 1) Next, the display control unit 1
The above image data R, G, B, clock signal T, horizontal synchronizing signal H, and vertical synchronizing signal V are input signals, and based on the clock signal T, horizontal synchronizing signal H, and vertical synchronizing signal V,
In addition to generating and outputting a display start instruction signal k described later,
Based on the image data R, G, B, composite address data (second electrode control signal) d described later is generated and output. The display control section 1 is supplied with a voltage of 5 V from the power supply circuit 56.

More specifically, as shown in FIG. 1, each of three input terminals of the timing signal generator 60 is connected to an output terminal for outputting a clock signal T, a horizontal synchronizing signal H, and a vertical synchronizing signal V. Based on the signals T, H, V of
A display start instruction signal k, a timing signal j2, and a count value j3 are generated and output.

This display start instruction signal k is a signal for instructing the start (head) of the display sequence, and the start signal RST
(RST signal) and a reference clock signal j1 (see FIG. 3). The display start instruction signal k is output from the output terminal OT1A and the output terminal OT1B of the display control unit 1. Note that the output terminal OT1A and the output terminal OT1B are collectively referred to as “output terminal OT1 (first output terminal)”.

The timing signal j2 is output to the data converter 57.

The count value j3 is stored in the first ROM 62
Is output to

Here, the first ROM 62 has a predetermined control signal d2 (for example, 5 bits) for controlling the address electrodes.
The signal waveform for one frame (video display frame) is stored in advance, and the predetermined control signal d2 stored at the address designated by the counter value j3 is stored in the first ROM.
62.

From the first ROM 62, signals such as a read instruction signal for each scanning line, a read instruction signal for one screen, a reference clock for display, and the like, which are stored in advance, are transferred to the data converter 57. You. These signals are collectively referred to as “signal t2”.

On the other hand, image data R, G, B of the video display
An output terminal for outputting the timing signal j2 of the timing signal generator 60;
2 is connected to an output terminal for outputting the signal t2, and the data converter 57 outputs the signals R to G, j2,
t2 is input.

Further, the data converter 57 is connected to the first memory 58 and the second memory 59 via a predetermined signal line.

The data converter 57 outputs the timing signal j2
In one processing period (corresponding to a video display frame) based on the image data, the image data R, G, and B of one frame composed of 10 bits are converted into 10 bit plane data, and the data is converted into the first memory 58. Is stored (stored).

In a subsequent processing period, the data converter 57 reads out the stored bit plane data from the first memory 58, and sequentially performs a predetermined process on the data to obtain 80-bit address data d1. And output this. On the other hand, during this processing period, the data converter 57 performs the above-described bit plane data conversion processing on the image data R, G, and B of the frame following the one frame, and converts the obtained bit plane data into the second data. It is stored (stored) in the memory 59. Note that the bit plane data stored in the second memory 59 is stored in the second memory during the processing period following this processing period.
The data is read from the memory 59 and subjected to the above-described address data generation processing, and is output as address data d1 of a frame subsequent to the one frame.

As described above, the data converter 57 converts the converted bit plane data into the first and second memories 58 and 5.
9 and read from the first and second memories 58 and 59 alternately, and the series of processes described above are continuously repeated to generate and output the address data d1. In addition,
The data converter 57 and the first and second memories 58 and 59 according to the first embodiment include a conventional PDP display device 50P.
The data converter 57P (see FIG. 10) and the first and second memories 58P and 59P (see FIG. 12) may be used.

A parallel signal obtained by combining the address data d1 generated by the data converter 57 and the predetermined control signal d2 read from the first ROM 62 is
It is output from the (second) output terminal OT2 of the display control unit 1 as composite address data (second electrode control signal) d. The details of the composite address data d will be described later.

(PDP Display Unit 4) Next, the PDP display unit 4
Will be described.

The PDP 51 (display panel) in the PDP display section 4 includes a plurality of scanning electrodes (first electrodes) and a plurality of common electrodes which are paired with the plurality of scanning electrodes and formed in parallel. And a plurality of address electrodes (second electrodes) formed in a direction perpendicular to both electrodes. The illustration of the three electrodes is omitted in the PDP 51 of FIG.

Then, as shown in FIG. 1, the PDP display unit 4 connected to the input terminal of the scan electrode control signal generator 2
The (first) input terminal IT1A and the (first) output terminal OT1A (the output terminal of the timing signal generator 60) that outputs the display start instruction signal k of the display control unit 1 are connected to the signal line 72 (the first signal line). ), And the output terminal of scan electrode control signal generator 2 and the input terminal of scan electrode driver 52 are connected to signal line 82.
(Third signal line). In particular, this PD
In the P display device, the scan electrode control signal generator 2 and the scan electrode driver 52 are arranged close to each other in order to make the length of the signal line 82 as short as possible.

Each of the plurality of output terminals of the scan electrode driver 52 is connected to one end of the corresponding scan electrode of the PDP 51 via a signal line 92. Further, a predetermined voltage (power) e is supplied to the scan electrode driver 52 from a power supply circuit 56.

Similarly, the input terminal IT1B of the common electrode control signal generator 3, which is the input terminal of the PDP display unit 4, and the output terminal of the display control unit 1 for outputting the display start instruction signal k (the output terminal of the timing signal generator 60) The output terminal OT1B is connected via a signal line 73, and the output terminal of the common electrode control signal generator 3 and the input terminal of the common electrode driver 53 are connected via a signal line 83. In particular, in the present PDP display device, the common electrode control signal generator 3 and the common electrode driver 53 are arranged close to each other in order to make the length of the signal line 83 as short as possible.

Each of the plurality of output terminals of the common electrode driver 53 is connected to one end of the corresponding common electrode of the PDP 51 via a signal line 93. Further, a predetermined voltage (power) i is supplied from the power supply circuit 56 to the common electrode driver 53. Note that, as in the connection form between the conventional PDP 51P and the conventional common electrode driver 53P shown in FIG. 10, one end of each of the common electrodes of the PDP 51 is connected in common to the output terminal of the common electrode driver 53. May be.

In particular, the display start instruction signal k is the start signal R
ST and the reference clock signal j1, the signal line 7
Each of 2 and 73 is composed of two signal lines.

Although not shown, the scan electrode control signal generator 2 and the common electrode control signal generator 3
Are connected to a power supply circuit 56 and are supplied with a predetermined voltage (power).

On the other hand, the (second) input terminal I of the PDP display 4
T2, the input terminal of the address electrode driver 54, and the output terminal OT2 of the display control unit 1 for outputting the composite address data d.
Are connected via a signal line 84 (second signal line), and each of the plurality of output terminals of the address electrode driver 54 is connected via a signal line 94 to one end of each of the address electrodes of the corresponding PDP 51. ing. Further, a predetermined voltage (power) f is supplied to the address electrode driver 54 from a power supply circuit 56.

(Drive Circuit System for Scanning Electrode and Common Electrode (Drive Circuit System for First Electrode)) FIG. 2 shows a more detailed configuration 2a of the scan electrode control signal generator 2 (hereinafter referred to as "scan electrode control signal generator"). FIG. 3 is a timing chart showing a signal processing process in scan electrode control signal generator 2a of FIG.

As shown in FIG. 2, a display start instruction signal k is formed at each of two input terminals (input signal terminal IT1A in FIG. 1) of the counter 612a which is an input terminal of the scan electrode control signal generator 2a. Signal line (one signal line of the first signal line) for transmitting the start signal RST and the reference clock signal j
1 (the other signal line of the first signal line). Further, the output terminal of the counter 612a is connected to the input terminal of the second ROM 63, and the output terminal of the second ROM 63, which is the output terminal of the scan electrode control signal generator 2a, is connected to the input terminal of the scan electrode driver 52 (see FIG. 1). Have been.

As shown in FIG. 3A, when start signal RST is applied at time t0, counter 612 is set at the first rise of reference clock signal j1 after time t0.
The value of a is set to the initial value 0. Then, the counter 61
2a performs an increment count corresponding to the rise of the reference clock signal j1 until the next start signal RST is applied, and outputs the result.

The second ROM 6 using the above count value as an input signal
Numeral 3 stores in advance the signal waveform of the scan electrode control signal (first electrode control signal) a corresponding to the value of the input signal, and the scan electrode control signal a corresponding to the count value is read from the second ROM 63. Output. FIGS. 3D and 3E show examples of signal waveforms a1 and a2 corresponding to, for example, the upper two bits of the 15-bit scan electrode control signal a.

As shown in FIG. 1, the scan electrode driver 52 having the scan electrode control signal a as an input signal generates and transmits / receives various signals based on the scan electrode control signal a.
The amplitude conversion of various signals is performed, and a predetermined voltage is supplied to each scanning electrode connected to the output terminal.

As described above, in the conventional PDP display device,
The counter 61P and the second ROM 63P, which are components corresponding to the scan electrode control signal generator 2a in FIG.
2) is provided in the display control unit 50P (see FIG. 10), whereas in the PDP display device according to the first embodiment, the scan electrode control signal generator 2 (2a)
The scan electrode control signal generator 2 and the scan electrode driver 52 are provided in the P display unit 4 and are arranged close to each other as described above. Therefore, according to the present PDP display device, the wiring length of the signal line 82 which is composed of a plurality of signal lines and transmits the scan electrode control signal a is changed to the signal line 82P which transmits the same signal a in the conventional PDP display device (see FIG. (See 10)
Can be shorter than At the same time, according to the present PDP display device, the number (two) of signal lines 72 connecting the display control unit 1 and the PDP display unit 4 or the scan electrode control signal generator 2 is changed to the conventional PDP display device of FIG. In this case, the number of signal lines 82P (15) connecting the display control unit 50P and the PDP display unit 55P can be significantly reduced. When a ground line attached to each signal line is considered, the signal line 82 in the conventional PDP display device is used.
It can be said that 30 signal lines forming P can be reduced to four signal lines forming signal line 72 in this device.

Therefore, according to the present PDP display device, the EMI noise emitted from the signal lines 72 and 82 is
It can be greatly reduced than that of the conventional PDP display device.
In addition, according to the present PDP display device, the number of parts such as lead wires and connectors required for connecting between the display control unit 1 and the PDP display unit 4 formed on separate substrates is reduced.
It can be greatly reduced as compared with the conventional PDP display device. Therefore, the miniaturization of the PDP display device and the cost reduction of the PDP display device can be further promoted.

Further, according to the present PDP display device, the signal line 82 for transmitting the scan electrode control signal a is connected to the PDP display unit 4.
Can be formed by copper foil pattern wiring on the mounting substrate. Therefore, although the signal line 82 has the same number of signal lines as the signal line 82P of the conventional PDP display device (see FIG. 12), no components such as lead wires and connectors are required. From this viewpoint, the present PDP display device can be reduced in size and cost.

On the other hand, the common electrode control signal generator 3 has the same configuration as the scan electrode control signal generator 2a. FIG. 4 shows a more detailed configuration 3a (hereinafter, referred to as a common electrode control signal generator 3)
FIG. 4 is a block diagram illustrating a “common electrode control signal generator 3a”.

As shown in FIG. 4, similarly to scan electrode control signal generator 2a, two input terminals of counter 613a (input terminals IT in FIG. 1) which are input terminals of common electrode signal generator 3a.
1A, IT1B) include a signal line for transmitting the start signal RST (one of the first signal lines) and a signal line for transmitting the reference clock signal j1 (the other signal line of the first signal line). Is connected. Further, the output terminal of the counter 613a is connected to the input terminal of the third ROM 64, and the output terminal of the third ROM 64, which is the output terminal of the common electrode control signal generator 3, is connected to the input terminal of the common electrode driver 53 (see FIG. 1). Have been.

The common electrode control signal generator 3a performs the same processing as the scan electrode control signal generator 2a based on the start signal RST and the reference clock signal j1, which are input signals, to generate the common electrode control signal c. Output.

As shown in FIG. 1, the common electrode driver 53 having the common electrode control signal c as an input signal generates and transmits and receives various signals based on the common electrode control signal c.
The amplitude conversion of various signals is performed, and a predetermined voltage is supplied to each scanning electrode connected to the output terminal.

As described above, the drive circuit system for the common electrodes of the present PDP display device has the same configuration as the drive circuit system for the scan electrodes. An effect similar to that of the drive circuit system can be obtained.

In particular, according to another specific configuration 2b of scan electrode control signal generator 2 shown in FIG. 5 (hereinafter referred to as "scan electrode control signal generator 2b"), the above effect is further improved. sell. Hereinafter, the scan electrode control signal generator 2b will be described.

As shown in FIG. 5, the input terminal of the counter 612b, which is the input terminal of the scan electrode control signal generator 2b,
1 for transmitting start signal RST of display start instruction signal k
Only the signal line 72 made up of these signal lines is connected.
Further, the other input terminal of the counter 612b is connected to the output terminal of the oscillator 5 provided in the main scan electrode control signal generator 2b. The oscillator 5 can generate and output the above-described reference clock signal j1. Therefore, like the scan electrode control signal generator 2a, the counter 612b receives the start signal RST and the reference clock signal j1 as input signals and outputs an increment count value thereof. Then, from the second ROM 63 using the count value as an input signal,
Similarly to scan electrode control signal generator 2a, scan electrode control signal a is read and output.

P provided with main scan electrode control signal generator 2b
According to the DP display device, the display control unit 1 of FIG.
The display start instruction signal k transmitted to the display unit 4 is a start signal R
Since only ST is used, the number of signal lines 72 can be reduced to one.

Further, the display start instruction signal k is 10 MH
Reference clock signal j which is a high frequency signal of z to 20 MHz
1 (see FIG. 3 (b)) and a start signal R which is a low-frequency signal (about 60 Hz) which is substantially the same as the vertical synchronizing signal V.
Since it is composed of only ST (see FIG. 3A), almost no EMI noise is emitted from the signal line 72.

Of course, the common electrode control signal generator 3 (see FIG. 1) may have the same configuration as the main scan electrode control signal generator 2b. In such a case, the generator 2b
Needless to say, the same effect as described above can be exerted.

As described above, since the structure of the scan electrode and the common electrode and the drive circuit system of both electrodes are the same, if the scan electrode and the common electrode are comprehensively regarded as the "first electrode", , The scan electrode control signal a and the common electrode control signal c can be collectively referred to as “first electrode control signal”, and the scan electrode control signal generator 2 and the common electrode control signal generator 3 are referred to as “first electrode control signal”. The signal generator "can be generically called, and the scan electrode driver 52 and the common electrode driver 53 can be generically called" first electrode driver ". In addition,
The first electrode control signal generator and the first electrode control signal driver will be referred to as a "first electrode driver". Further, the signal line 72 and the signal line 73 can be generically called a “first signal line”, and the signal line 82 and the signal line 83 can be generically called a “third signal line”. The input terminal IT1A and the input terminal IT1B can be generically referred to as “the first input terminal (IT1) of the (PDP) display unit”.

The conventional display control unit 50 shown in FIG.
P and the PDP display unit 55P are connected to each other by 50P and 55P so that signal processing in each is optimally performed.
It is divided and arranged. From such a viewpoint, such a circuit configuration (division method) can be called a centralized processing type division method.

On the other hand, the PD according to the first embodiment
The P display device includes a signal processing circuit of the display control unit 1 and a PD.
By taking into account the three elements of the signal processing circuit of the P display unit 4 and the connection form of the PDP unit 4, an optimized circuit configuration of the entire PDP display device is realized. For this reason, the division form of each circuit in the present PDP display device can be called a distributed processing division method.

(Drive Circuit System for Address Electrode (Second Electrode)) Next, the display control section 1 and the PDP display section 4 are connected to transmit composite address data (second electrode control signal) d ( Second, the configuration of the signal line 84 (see FIG. 1) and the configuration of the address electrode driver (second electrode driver) 54 will be described.

FIG. 6 shows the (first) output terminal OT2 of the display controller 1 for outputting the composite address data d and the address electrode driver 5 which is the (second) input terminal IT2 of the PDP display unit 4.
FIG. 4 is a diagram schematically illustrating a connection form between the input terminal of FIG.
In FIG. 6, only the components necessary for the following description are extracted and shown.

The composite address data d is, as described above,
The 80-bit address data d1 and a 5-bit predetermined control signal d2 are combined. In detail, as shown in FIG. 6, the composite address data d is composed of four parallel control signals in which a predetermined control signal d2 of 5 bits is added to each of 20-bit address data obtained by dividing 80-bit address data d1 into four. (Hereinafter referred to as “composite address data da, db, dc, dd”).

The four composite address data da, d
The address electrode driver 54 includes four divided address electrode drive circuits 541, 542, 54 corresponding to b, dc, and dd.
3,544 (hereinafter, also collectively referred to as “divided address electrode drive circuit 54”).

In FIG. 6, for example, looking at the transmission path of the composite address data da, the data da
The output terminal (output terminal OT2 in FIG. 1) outputs the input terminal (input terminal IT2 in FIG. 1) of the divided address electrode driving circuit 541 via a signal line 841a (second signal line) composed of 25 signal lines. )It is connected to the. Each of the signal lines 841a has a ground line 841b, and the 25 signal lines 841a and the 25 ground lines 841b are collectively referred to as a “signal line 841”. That is, the output terminal for outputting the composite address data da and the divided address electrode driving circuit 54
1 is connected via a signal line 841.

As shown in FIG. 6, the signal lines 8 for transmitting the data db, dc and dd are similarly provided for the transmission paths of the composite address data db, dc and dd.
42a, 843a and 844a and their corresponding ground lines 842b, 843b and 844b.
42, 843, 844 (each a second signal line). " These four signal lines 841, 842, 843, 8
When the signal lines 44 are collectively referred to as a “signal line 84 (second signal line)” (see FIG. 1), the output terminal for outputting the composite address data d and the input terminal of the address electrode driving circuit 54 are connected to the signal line 84. It can be said that they are connected through.

In particular, as shown in FIG.
In the PDP display device according to
b, 842b, 843b, and 844b are all connected to one end of a common switch 11 in the display control unit 1, and the other end of the switch 11 is grounded. The opening / closing operation of the switch 11 is controlled by a signal q. Switch 1
For 1, a mechanical or electrical switch such as a relay, a transistor, or a MOS FET can be used.

In the case of the above configuration, the signal lines 84 are 200 in total including the ground lines.
If each ground line is consolidated into one for each of 1,842,843,844 (the ground line cannot be removed),
The number of signal lines constituting the signal line 84 can be reduced to a total of 104 signal lines.

Next, the PDP 51 having the configuration shown in FIG.
The case of a full color wide type VGA PDP with 53 × 480 pixels (853 pixels per scanning line) will be specifically described.

In a full-color PDP, one pixel is formed of light-emitting cells for three colors of red (R), green (G), and blue (B), so that the total number of light-emitting cells of the PDP 51 is 2559 × 4.
There are 80. That is, the PDP 51 has 2559 address electrodes. Therefore, since each of the four divided address electrode driving circuits 54 is responsible for driving 640 address electrodes, when using an IC that outputs a 64-bit output signal, ten ICs are provided. It consists of. At this time, one IC is designed to handle a 4-bit input signal (address data).
In the case where address data of 8 bits is handled by two ICs, five pairs of ICs are provided for each divided address electrode drive circuit 54. At this time, the address data d1 of 4 bits × 5 pairs = 20 bits is input to each divided address electrode drive circuit 13. If each of the divided address electrode driving circuits 54 executes this input process 32 times, it is possible to handle a 640-bit input signal corresponding to the number of shared address electrodes. Therefore, the divided address electrode driver 54 receives all the address data of one scanning line by performing the input process 32 times for the address data d1 of 80 bits.

Each of the divided address electrode driving circuits 54 receives the composite address data da, db, dc,
dd reception and 5V system image data R, G, B 40V
A process of converting the amplitude into a pulse voltage of up to 70 V and a process of supplying power to each address electrode are performed. By such processing, the PDP 51 is driven for each of the four divided display areas.

As described above, when a predetermined drive voltage is applied to the scan electrode, the common electrode, and the address electrode of the PDP 51, discharge / emission of each light emitting cell occurs, and the image data R, G, B (or analog data) is generated. A full-color display image based on the video signals r, g, b) is displayed.

Now, also in the conventional PDP display device shown in FIG. 10, the signal line 84P has a ground line (not shown). Therefore, the display control unit 50P and the PDP display unit 55P are electrically connected via the ground line. Therefore, switching noise and discharge noise generated in the PDP display unit 55P may propagate to the display control unit 50P and further to the video processing unit 70P via the ground line. Such noise and the analog video signal r,
When interference occurs with g, b, etc., an image based on the image signal causing the interference is displayed, and the display image quality of the PDP 51P is reduced.

On the other hand, the PD according to the first embodiment
In the P display device, as shown in FIG.
b, 842b, 843b, and 844b are grounded via a common switch 11. By opening and closing this switch 11 at an appropriate timing, the propagation of the noise generated in the PDP display unit 4 is suppressed and eliminated. doing. Hereinafter, the opening / closing control of the switch 11 will be described in detail.

First, the display operation of the present PDP display device will be described with reference to an example of a timing chart shown in FIG. 7A shows the timing of application of the frame signal, and the period of the frame signal is 1
Indicates the frame period. FIG. 7B shows the time distribution when one frame is formed by, for example, four subfields, and FIGS. 7C, 7D, and 7E show the light emission preparation period (E) in each subfield. (Reset period), address period, and discharge period.

In the above-described light emission preparation period, address period, and discharge period, the composite address data d is applied to the signal line 84 in FIG.
Is transferred to the address electrode driver 54 via only during the address period. Therefore, during the light emission preparation period and the discharge period, the ground lines 841b, 842b, 843
It is not necessary that b, 844b be grounded.

Therefore, in the present PDP display device, only during the address period, the switch 11 shown in FIG. 6 is controlled to the closed state (ON state) to control the ground lines 841b, 842b, 84
3b and 844b are grounded. On the other hand, during the light emission preparation period and the discharge period, the switch 11 is controlled to the open state (off state) to control the ground lines 841b and 842.
b, 843b are separated from the ground potential.

Accordingly, when the high-level period of the pulse in FIG. 7D corresponds to the ON processing period of the switch 11 and the low-level period corresponds to the OFF processing period, (d) in FIG. This can be regarded as a timing chart for on / off control of the switch 11.
That is, the control signal q of the switch 11 is represented as a digital signal waveform shown in FIG. This control signal q
Is generated in the timing signal generator 60 of FIG. 1 or another timing signal generator and supplied to the switch 11.

As described above, in the present PDP display device, the ground lines 841b and 841 in FIG.
42b, 843b, and 844b are grounded, so that the composite address data d can be appropriately transferred, and the noise is transmitted via the ground lines 841b, 842b, 843b, and 844b during periods other than when the composite address data d is transferred. 1 to the display control unit 1 or the video display unit 70 can be reliably removed. Therefore, it is possible to effectively prevent the image display of the PDP 51 from being deteriorated due to the noise. Further, according to the present PDP display device, the propagation of the noise during the light emission preparation period and the discharge period can be eliminated without using an electric noise filter, a filter with a built-in metal mesh, or the like. Another advantage is that it does not impede the promotion of pricing.

(Modification of Embodiment 1) In this modification,
A PDP display device capable of suppressing and removing EMI noise emitted when transmitting the display start instruction signal k by a separate means will be described. Note that the basic configuration of the PDP display device according to this modified example may be the same as the configuration shown in FIG. 1, and thus the same components will be denoted by the same reference characters and description thereof will be omitted. In particular, the PDP display device according to the present modification has a feature in the transmission form of the display start instruction signal k, and thus the description will be focused on this point.

FIG. 8 is a block diagram showing a configuration of a transmission path when transmitting display start instruction signal k using light as a transmission medium. In FIG. 8, only the components necessary for explaining the characteristic portions of the present PDP display device are extracted and shown. First, a case where the display start instruction signal k includes the above-described start signal RST and the reference clock signal j1 will be described with reference to FIG.

As shown in FIG. 8, in the present PDP display device, a start signal in an output terminal ((first) output terminal OT1A in FIG. 1) for outputting a display start instruction signal k of the display control unit 1 is provided. A light emitting device 6a is provided at an output terminal for outputting RST. On the other hand, the start signal RS of the PDP display unit 4
A light receiver 8a is provided at the input terminal of T (input terminal IT1A in FIG. 1). The light emitting device 6a and the light receiving device 8a are connected by an optical transmission path 7a ((first) signal line 72 in FIG. 1). Of course, the light emitting device 6a is provided at the output terminal of the timing signal generator 60 (see FIG. 1), and the scan electrode control signal generator 2 is provided.
a (or the scanning electrode control signal generator 2 in FIG. 1) may be provided with a light receiver 8a at the input end.

That is, when the start signal RST, which is an electric signal, is input to the light emitting device 6a, the start signal RST is converted into an optical signal and output. The start signal RS which is this optical signal
When T is transmitted through the optical transmission path 7a and is input to the photodetector 8a, the start signal RST is converted into an electric signal and output. Then, the start signal RS converted into the electric signal
T is an input signal of the scan electrode control signal generator 2a (see FIG. 2). Of course, the common electrode control signal generator 3a (FIG. 5)
See also).

Similarly, as shown in FIG. 8, the display controller 1 transmits the reference clock signal j1 as an optical signal.
The light-emitting device 6b provided on the PDP display unit 4 and the light-emitting device 6b provided on the PDP display unit 4 are connected via an optical transmission path 7b.
Therefore, like the start signal RST, the reference clock signal j
1 is transmitted to the optical transmission line 7b ((first) signal line 72 in FIG. 1) after being converted into an optical signal by the light emitting device 6b.
The light is converted into an electric signal again by the light receiver 8b.

As described above, the PDP display device according to the present modification transmits the display start instruction signal k as an optical signal, so that no EMI noise is radiated from the optical transmission lines 7a and 7b.

Further, according to the present PDP display device, since the display control unit 1 and the PDP display unit 4 shown in FIG. 8 are electrically separated, switching noise and discharge noise generated in the PDP display unit 4 are displayed. It does not propagate to the control unit 1. Accordingly, the noise and the analog video signals r, g, b
The display quality of the PDP 51 does not deteriorate due to interference with the PDP 51 or the like.

Next, the display start instruction signal k is changed to the start signal RS.
A PDP display device including only T will be described.

FIG. 9 is a block diagram showing another configuration of a PDP display device for optically transmitting display start instruction signal k. PD using the display electrode control signal generator 2b of FIG.
It corresponds to a P display device.

As shown in FIG. 9, the start signal R of the electric signal
A light emitter 6c for converting ST into an optical signal is provided at an output terminal of the display controller 1 ((first) output terminal OT1A in FIG. 1). On the other hand, an input terminal (the (first) input terminal IT (FIG. 1) of FIG.
1A), a light receiver 8c for converting a start signal RST of an optical signal into an electric signal is provided. The light emitting device 6c and the light receiving device 8c are connected to the optical transmission path 7c ((first) in FIG. 1).
They are connected via signal lines 72). Then, the photodetector 8 which outputs the start signal RST converted into the electric signal again
The output terminal of c is connected to the input terminal of the scan electrode control signal generator 2b described above. Of course, this modified example can be applied to a common electrode control signal generator corresponding to the scan electrode control signal generator 2b.

According to the present PDP display device, it is needless to say that the above-mentioned effect by the optical transmission of the display start instruction signal k can be obtained, and furthermore, the optical transmission path (optical path) necessary for transmitting the display start instruction signal k can be obtained. There is also an effect that the number of transmission media can be minimized (one).

A light source such as an LED or a laser can be used as the light emitters 6a, 6b, 6c. At this time, the light receivers 8a, 8b, 8c are light emitters 6a, 6b, 6c.
An optical sensor suitable for the light source is used. As the optical transmission lines 7a, 7b, 7c, for example, optical fibers can be applied. Further, the light emitted from the light emitters 6a, 6b, 6c is propagated in the air, so that the light receiver 8 of the optical signal can be used.
Communication to is possible. For this reason, the optical transmission lines 7a, 7
Various optical transmission lines (first signal lines) capable of transmitting optical signals emitted from the light emitters 6a, 6b, 6c to the light receivers 8a, 8b, 8c can be used for b and 7c.

In the above description of the first embodiment and the modifications of the first embodiment, a three-electrode AC surface discharge type PDP display device has been described as an example of a display device. Various display devices such as a device and a direct current type PDP display device can be used. That is, any display device may be used as long as it has at least a first electrode and a second electrode and a display panel in which a light emitting cell is defined by at least the first electrode and the second electrode.

[0114]

(1) According to the first aspect of the present invention, the component for generating the first electrode control signal arranged in the display control unit in the conventional display device is arranged in the display unit. . In the conventional display device, the signal line transmitting the first electrode control signal is very long because it is a signal line connecting the display control unit and the display unit. In comparison,
According to the present invention, since the component for generating the first electrode control signal is arranged in the display unit, the wiring length of the signal line can be significantly reduced. In addition, even when the screen of the PDP display device is enlarged, the wiring length of the signal line transmitting the first electrode control signal hardly increases. Therefore, a PDP display device in which noise from the signal line, for example, EMI noise is sufficiently suppressed can be obtained.

(2) According to the second aspect of the invention, the first
Since the electrode control signal generator and the first electrode driver are arranged close to each other, the third signal line including a plurality of signal lines can be shortened. Therefore, the same effect as the above (1) can be obtained.

Further, in the conventional display device, a component corresponding to the first electrode control signal generator is provided in the display control unit, whereas in the present invention, the first electrode control signal generator is provided in the PDP display unit. It is provided in. Therefore, the number of signal lines connecting the display control unit and the display unit (first electrode control signal generator) can be significantly reduced as compared with the conventional PDP display device.

Therefore, according to the present invention, the number of components such as lead wires and connectors required for connecting the display control unit and the display unit can be greatly reduced. Thus, the size of the PDP display device can be reduced, and the cost of the display device can be reduced.

(3) According to the third aspect of the invention, the same effect as the above (2) can be obtained.

In particular, according to the present invention, the display start instruction signal is composed of only a relatively low frequency start instruction signal for instructing the start of the display sequence of the video display frame. When transmitting one signal line, EMI noise is hardly emitted.

(4) According to the fourth aspect of the present invention, since the display start instruction signal includes the start signal and the reference clock signal, the first signal line includes two signal lines. Therefore,
The same effect as the above (2) can be obtained.

(5) According to the fifth aspect of the invention, in particular, the display start instruction signal is optically transmitted through the first signal line made of an optical transmission medium, so that the EM signal is transmitted from the first signal line.
This has the effect that no I noise is emitted.

Further, according to the present invention, since the first signal line is made of an optical transmission medium, the display control unit and the display unit do not have an electrical connection via the first signal line. Therefore, switching noise or discharge noise generated in the display unit when the display device is driven does not propagate to the display control unit via the ground line of the first signal line at all. Therefore, according to the present invention,
The display quality of the display device is not degraded due to the interference between the noise and the analog video signal or the like.

(6) According to the sixth aspect of the invention, the first
Alternatively, only during a period when a predetermined signal is transmitted to the second signal line, the first
The ground line of the signal line or the second signal line is connected to the ground potential. That is, in other periods, the display unit and the display control unit are not electrically connected via the ground line. Therefore, it is possible to effectively avoid a situation in which switching noise or discharge noise generated when the display device is driven interferes with an analog video signal or the like. Therefore, according to the present invention, the display quality of the PDP display device does not deteriorate due to the signal in which such interference has occurred.

In addition, there is no need to provide an electric noise filter or a filter with a built-in metal mesh as in the conventional PDP display device as a countermeasure against the above noise.
Cost reduction and cost reduction of the PDP display device can be promoted.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing an overall configuration of a PDP display device according to a first embodiment.

FIG. 2 is a block diagram showing a configuration of a scan electrode control signal generator.

FIG. 3 is a timing chart showing a signal processing process in a scan electrode control signal generator.

FIG. 4 is a block diagram showing a configuration of a common electrode control signal generator.

FIG. 5 is a block diagram showing another configuration of the scan electrode control signal generator.

FIG. 6 is a diagram schematically illustrating a connection configuration between an output terminal of a display control unit and an input terminal of an address electrode driver.

FIG. 7 is a timing chart schematically showing a driving method of the PDP.

FIG. 8 is a block diagram schematically illustrating a configuration of a PDP display device that optically transmits a display start instruction signal.

FIG. 9 is a block diagram schematically illustrating another configuration of a PDP display device that optically transmits a display start instruction signal.

FIG. 10 is a block diagram schematically showing the entire configuration of a conventional PDP display device.

FIG. 11 is a schematic diagram illustrating a configuration of a video processing unit in a conventional PDP display device.

FIG. 12 is a block diagram schematically illustrating a configuration of a display control unit in a conventional PDP display device.

[Explanation of symbols]

1 Display control unit, 2, 2a, 2b Scanning electrode control signal generator (first electrode control signal generator), 3, 3a Common electrode control signal generator (first electrode control signal generator), 4 (P
DP) display unit, 5 oscillators, 6a, 6b, 6c light emitters, 7a, 7b, 7c optical transmission path (optical transmission medium), 8
a, 8b, 8c light receiver, 11 switch, 51 PD
P (display panel), 52 scan electrode driver (first electrode driver), 53 common electrode driver (first electrode driver), 54
Address electrode driver or divided address electrode drive circuit (second electrode drive unit), 60 timing signal generator,
72, 73 signal lines (first signal line), 82, 83 signal lines (third signal line), 84 signal lines (second signal line), 54
1,542,543,544 divided address electrode drive circuit (second electrode drive unit); 841,842,843,84
4 signal lines (second signal lines), 841a, 842a, 84
3a, 844a signal line (second signal line), 841b, 8
42b, 843b, 844b Ground line (second signal line), a Scan electrode control signal (first electrode control signal), c
Common electrode control signal (first electrode control signal), d, da,
db, dc, dd composite address data (second electrode control signal), d1 address data, d2 predetermined control signal, k display start instruction signal, RST start signal, j1 reference clock signal, IT1, IT1A, IT1B first input terminal , IT2 second input terminal, OT1, OT1A, OT1
B first output end, OT2 second output end, R, G, B
(Digital) image data signal.

Claims (6)

[Claims] 1. A timing signal generator, comprising: a display start instruction signal generated by the timing signal generator;
A display control unit that outputs from the output terminal, generates a second electrode control signal based on the input image data signal, and outputs from the second output terminal; and at least a first electrode and a second electrode; A display panel in which a light emitting cell is defined by at least the first electrode and the second electrode; a first input terminal; and a connection between the first input terminal and the first electrode to generate a first electrode control signal. A first electrode driving unit, a second input terminal, and a display unit having a second electrode driving unit connected between the second input terminal and the second electrode. The first output terminal and the first input terminal of the display unit are connected via a first signal line, and the second output terminal of the display control unit and the second input terminal of the display unit are connected to each other. A display device, which is connected via two signal lines. 2. The display device according to claim 1, wherein the first electrode driving units are arranged adjacent to each other.
An electrode control signal generator and a first electrode driver; wherein the first input terminal of the first electrode driver is connected to an input terminal of the first electrode control signal generator; An output terminal is connected to the first electrode of the display panel, and an output terminal of the first electrode control signal generator is a third signal line including a plurality of signal lines at an input terminal of the first electrode driver. A display device, characterized in that the display device is connected via a. 3. The display device according to claim 2, wherein the first electrode control signal generator includes a transmitter that generates and outputs a reference clock signal, and the display start instruction signal is a start instruction. A display device comprising a signal only. 4. The display device according to claim 2, wherein the display start instruction signal comprises a start instruction signal and a reference clock signal. 5. The display device according to claim 1, wherein the first signal line is made of an optical transmission medium, and a light emitting device is provided at the first output terminal of the display control unit. A display device, wherein a light receiver is provided at a first input terminal of the display unit. 6. The display device according to claim 1, wherein a ground line of the first signal line or the second signal line is grounded via a predetermined switch, and the predetermined switch is connected to the first signal line. The display device is controlled to be in a closed state only during a period when a predetermined signal is transmitted to a signal line or the second signal line.